Electrónica II

Transistores de Efecto de Campo

(FET – Field Effect Transistor)

Leiner Barba Jimenez, PhD

Conceptos y Definiciones
• El transistor de efecto de campo (FET) es un dispositivo de tres
terminales y se utiliza aplicaciones similares a las del transistor BJT.

• Se denominan de efecto de campo porque en el funcionamiento la

señal de entrada crea un campo eléctrico que controla el paso de la
corriente en el dispositivo.

• Son dispositivos unipolares.

Conceptos y Definiciones

Es un dispositivo
controlado por
voltaje.
Conceptos y Definiciones
• Los FET pueden ser tipo p o tipo n

• Para el FET las cargas presentes establecen un campo eléctrico, el cual controla la ruta de
conducción del circuito de salida sin que requiera un contacto directo entre las
cantidades de control y las controladas.

• Uno de las características más importantes del FET es su alta impedancia de entrada.

• Las ganancias de voltaje de ca típicas para amplificadores de BJT son mucho mayores que
para los FET.

• Los FET son más estables a la temperatura que los BJT, y en general son más pequeños
que los BJT, lo que los hace particularmente útiles en chips de circuitos integrados
 TIPOS DE FET
Podemos encontrar tres tipo de transistores de efecto de campo:

• JFET (Junction Field-Effect Transistor)

• MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor)

• MESFET (Metal–Semiconductor Field-Effect Transistor)

 JFET
CONSTRUCCIÓN Y CARACTERÍSTICAS
William Bradford Shockley
Fueron propuestos por Schockley en 1952. (1910-1989) coinventor del
primer transistor y
formulador de la teoría del
“efecto de campo”
Estructura Básica de JFET de canal n empleada en el desarrollo
del transistor y el FET.

Hay 3 Terminales:

• Drenaje (D)
• Fuente (S)
• Compuerta (G)
Aplicando un Voltaje VDS
Se aplica un voltaje positivo VDS a través del canal y
la compuerta está conectada directamente a la
fuente para establecer la condición VGS = 0 V

Se produce la corriente convencional ID

ID = IS

La unión p-n se polariza en inversa a lo largo del

Canal, lo cual produce una corriente de cero
amperes en la compuerta.
 Curva de Característica
A medida que el voltaje VDS aumenta de 0 V a algunos volts, la corriente también lo hará … ley de Ohm.

A medida que VDS se incrementa y se

aproxima un nivel conocido como
Vp, las regiones de empobrecimiento
se ensanchan.

Se reduce notablemente el ancho

del canal, y su resistencia se
incrementa.
Estrangulamiento
• Si VDS se incrementa a un nivel donde pareciera que
las dos regiones de empobrecimiento “se tocarán”, se
produciría una condición conocida como
estrangulamiento.

• El nivel de VDS que establece esta condición se conoce

como voltaje de estrangulamiento, Vp.

• Si VDS aumenta más allá de Vp, la longitud de la región

del encuentro cercano entre las dos regiones de
empobrecimiento crece a lo largo del canal, pero el
nivel de ID permanece igual.

ID = IDSS
Condiciones de Estrangulamiento
• Cuando VDS se incrementa superando Vp,
el transistor se comporta como una fuente
de corriente:
ID = IDSS

• IDSS es la corriente de drenaje máxima del

JFET y se alcanza bajo las condiciones:
VGS = 0 V
VDS > |Vp|
 Qué pasa si VGS < 0
Sabemos que:

El voltaje de la compuerta a la fuente, denotado VGS, es el voltaje de control

del JFET

Para encontrar las curvas del JFET de canal n,

El voltaje de control VGS se debe llevar a rangos negativos para evaluar el

comportamiento del JFET, a partir de VGS = 0 V
 Variar Voltajes VGS y VDS

• Se aplica un voltaje de -1 V entre la

compuerta y la fuente de un bajo nivel de VDS

• El efecto del VGS de polarización negativa es

establecer regiones de empobrecimiento
similares a las obtenidas con VGS = 0 V, pero a
niveles más bajos de VDS

• El resultado de la aplicación de polarización

negativa a la compuerta es alcanzar el nivel
de saturación a un nivel más bajo de VD
 Comportamiento al variar Voltajes VGS y VDS
El nivel de VGS que produce ID = 0
mA está definido por VGS = Vp, con
Vp convirtiéndose en un voltaje
negativo para dispositivos de canal
n y en voltaje positivo para JFET de
canal p.

Resistor controlado por voltaje

𝑟0
𝑟𝑑 =
(1 − 𝑉𝐺𝑆 /𝑉𝑝 )2

donde
ro es la resistencia con VGS = 0 V
rd es la resistencia a un nivel particular de VGS
 Dispositivos de Canal p
• El JFET de canal p se construye
exactamente de la misma manera que
el dispositivo de canal n con los
materiales p y n invertidos.

• Las direcciones de la corriente

definidas están invertidas, del mismo
modo que las polaridades reales de los
voltajes VGS y VDS

• El canal se estrechará al incrementarse

el voltaje positivo de la compuerta a la
fuente.
 Curva Característica
• A niveles altos de VDS la curva
se eleva de repente a niveles
que parecen ilimitados.

• La elevación vertical indica

que ocurrió una ruptura y que
la corriente a través del canal
ahora está limitada
únicamente por el circuito
externo.
 Símbolos

Canal n Canal p
 Resumen de Estados

VGS = 0 V, ID = IDSS Corte 0 < ID< IDSS

ID = 0 A
VGS menor que el nivel de corte
 Características de Transferencia
La ecuación de Shockley define la relación entre ID y VGS

2
𝑉𝐺𝑆
𝐼𝐷 = 𝐼𝐷𝑆𝑆 1−
𝑉𝑝

Cuando VGS = 0 V, ID = IDSS

Cuando VGS = VP, ID = 0 mA

JFET vs BJT
 TAREA

MESFET?
Metal–Semiconductor Field-Effect Transistor
 MOSFET
• Since the late 1970s, MOSFETs have become very popular;

• They are being used increasingly in integrated circuits (ICs). A MOSFET device can be made small, and it
occupies a small silicon area in an IC chip.

• The manufacturing of MOSFETs is relatively simple.

• MOSFETs are currently used for very-large-scale integrated (VLSI) circuits such as microprocessors and
memory chips.

• A MOSFET is a unipolar device. The current flow in a MOSFET depends on one type of majority carrier
(electrons or holes).

• The output current of MOSFETs is controlled by an electric field that depends on a gate control voltage.

• There are two types of MOSFETs: enhancement MOSFETs and depletion MOSFETs.
 Enhancement MOSFETs
There are two types of enhancement MOSFETs: n-channel and p-channel.

• n-channel enhancement MOSFET: NMOS

Physical Structure Schematic

• p-channel enhancement MOSFET: PMOS

Physical Structure Schematic

Four terminals are brought out: the gate terminal (G), the source terminal (S), the drain terminal (D), and
the substrate or body terminal (B)
Two back-to-back diodes, VGS = 0
An NMOS may be viewed as consisting of two diode junctions that are formed between the
substrate and the source and between the substrate and the drain. The hypothetical diodes are in
series and back to back.

These back-to-back diodes

prevent current conduction
from drain to source when a
voltage vDS is applied. In
fact, the path between drain
and source has a very high
resistance (of the order of
1012 Ω)

NMOS Schematic Diode Model

 How does it work?

Positive voltage, VGS, applied to the gate. An n channel is An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a
induced at the top of the substrate beneath the gate resistance whose value is determined by vGS. Specifically, the channel conductance is
proportional to vGS – Vt , and thus iD is proportional to (vGS – Vt )vDS
How does it work?
 Symbols
• n-channel enhancement MOSFET: NMOS

• p-channel enhancement MOSFET: NMOS

 Operation
• An NMOS is operated with positive gate and drain voltages relative to the source.
• A PMOS is operated with negative gate and drain voltages relative to the source.
• Substrates are connected to the source terminal.

Biasing of an NMOS Biasing of a PMOS

 Operation Modes
The NMOS can operate in any of the four operating regions:

• Cutoff Region

• Linear Ohmic
Ohmic Region
• Nonlinear Ohmic

• Saturation Region
Cutoff Region
The gate-to-source voltage VGS is greater than zero but less than the threshold voltage Vt:

0 < VGS <Vt

A positive value of VDS will reverse-bias the right-hand diode, and the drain current iD will be
approximately zero if the gate-to-source voltage VGS is zero:

iD = 0 , if VGS = 0
Linear Ohmic Region
Conditions:

VGS ≥ Vt
0 < VDS << (VGS –Vt)

A positive value of VGS will establish an electric field, which will attract
negative carriers from the substrate and repel positive carriers. As a result, a
layer of substrate near the oxide insulator becomes less p-type, and its
conductivity is reduced. As VGS increases, the surface near the insulator will
attract more electrons than holes and will behave like an n-type channel. The
minimum value of VGS that is required to establish a channel is called the
threshold voltage Vt
Effects of varying VGS and VDS
The drain current at VGS = Vt is very small. For VGS > Vt, the drain current iD increases almost linearly
with VDS for small values of VDS. If the drain-to-source voltage is low (usually less than 1 V), the drain
current iD can be calculated from Ohm’s law, (iD = VDS ⁄ rDS).

The conductance of the channel between the

drain and the source is:

where,
Nonlinear Ohmic Region
Conditions:

VGS ≥ Vt
0 < VDS < (VGS –Vt)

Increasing VDS does not change the depth of the channel at the source
end. However, it increases the drain-to-gate voltage VDG or decreases
the gate-to-drain voltage VGD, and the channel width decreases at the
drain end
Effects of varying VDS
The channel becomes narrower at the drain end with a tapered shape. When VDS becomes
sufficiently large and VGD is less than Vt. The characteristic will be nonlinear. Any further increase in
VDS does not cause a large increase in iD, and the transistor operates in the saturation region.

Other way for iD

where is called the MOS constant whose value depends on the physical parameters
Saturation Region
Conditions: iD-VDS characteristic for a constant VGS (> Vt)

VGS ≥ Vt
VDS ≥ (VGS –Vt)
Output and Transfer Characteristics
Increasing VDS beyond the breakdown voltage, denoted by VBD, causes an avalanche breakdown in the channel, and the drain
current rises rapidly. This mode of operation must be avoided because a MOSFET can be destroyed by excessive power
dissipation.

Output characteristics Transfer characteristics

Kn is a MOS constant
Substrate Biasing Effects
The source-to-substrate pn junction must always be zero or reverse biased, so must always be
greater than or equal to zero; otherwise electrons or holes will flow from the drain to the substrate
rather than the source terminals. The body or the substrate of a MOSFET is often connected to the
ground. In MOSFET circuits, the source and body may not be at the same potential and applications
of will increase the depletion region. In integrated circuits, however, the substrate is usually
common to many MOS transistors. To maintain the cutoff condition for all the substrate-to-channel
junctions, the substrate is usually connected to the most negative power supply in an NMOS circuit
(the most positive in a PMOS circuit).
Depletion MOSFETs
The construction of an n-channel depletion MOSFET is very similar to that of an NMOS. An actual
channel is formed by adding n-type impurity atoms to the p-type substrate. An n-channel depletion
MOSFET is normally operated with a positive voltage between the drain and the source terminals.
However, the voltage between the gate and the source terminals can be positive, zero, or negative,
whereas in an NMOS VGS is positive.

Schematic Diode model

Symbol

Symbol Abreviated symbol

Operation
• The operation of an n-channel depletion MOSFET is similar to that of an NMOS. A
depletion NMOS is off when its gate-to-source voltage VGS is less than Vp.

• The channel is fully established at VGS = 0 for a depletion NMOS and at VGS = VtN for an
enhancement NMOS

iD-VDS characteristic for a constant VGS (> Vp)

 Channel depletion and enhancement
If VGS is negative, some of the electrons in the n-channel area will be repelled from the channel and a depletion
region will be created below the oxide layer. This depletion region will result in a narrower channel. For VGS = 0,
a layer of substrate near the n-type channel becomes less p-type and its conductivity is enhanced.

For VGS < 0 For VGS > 0

Output and Transfer Characteristics
The output characteristics can be divided into three regions: ohmic, saturation, and cutoff.

Drain characteristics Transfer characteristics

 MOSFET Models
Since the drain currents of the enhancement and depletion MOSFETs depend on the gate–source
voltage, they are known as voltage-dependent devices and exhibit similar output characteristics and, the
same model can be applied to both of them with reasonable accuracy.
We need two types of models
for MOSFETs: a DC model
and a small-signal model.

DC signal

Load line
Small-signal vgs superimposed Small-signal gate-source voltage only
DC Models
The large-signal (DC) models of MOSFETs are nonlinear. The drain characteristics were shown in
slice 35 of iD as a function of vDS for different values of vGS describe the large-signal model of a
MOSFET. Thus, MOSFETs can be represented by the simple DC model:

Since the gate-channel has an oxide

layer, the gate current will be
negligibly small.
Small-Signal AC Models
The small-signal behavior of the MOSFET can be represented by a small-signal AC equivalent circuit consisting
of a voltage-dependent current source gmvgs in parallel with an output resistance ro representing a finite slope
of the iD-vDS characteristic. We find vds from:

vds = idro - rogmvgs = idro - µgvgs µg = rogm

open-circuit voltage
gain of the MOSFETs

Norton’s equivalent Thevenin’s equivalent

Small-Signal Output Resistance ro

The small-signal output resistance is the inverse slope of the iD-vDS characteristic in the pinch-down or saturation
region. It can be found as:

Here VM is called the channel modulation voltage and λ = 1/ | VM |, is called the channel modulation length. The
parameter VM is positive for a p-channel device and negative for an n-channel device. Its typical magnitude is
100 V. VM is analogous to the Early voltage VA of bipolar transistors
Transconductance gm
The transconductance is the slope of the transfer characteristic (iD versus vGS) and is defined as the change in
the drain current corresponding to a change in the gate-to-source voltage. It is expressed by

for enhancement MOSFETs for depletion MOSFETs

where where

gmo is the transconductance corresponding to vGS 0, and it varies linearly with vGS