3.5.

SIMULACIÓN EN PROTEUS
3.1 SUMADORES

DSW1(COM1)

U1:B
U1:A 4
1 6
3 5
1
2
3
4

1
2
3
4

2
DSW1 DSW2 74LS86
ON

ON

DIPSW_4 DIPSW_4 74LS86

U2:A
OFF

OFF

1
3 U3:A
8
7
6
5

8
7
6
5

2 1
3
74LS08 2

U2:B 74LS32
4
6
5

74LS08

U1:D
U1:C 12
9 11
8 13
10
74LS86
74LS86
U2:C
9
8 U3:B
10 4
6
74LS08 5

U2:D 74LS32
12
11
13

74LS08

U4:B
U4:A 4
1 6
3 5
2
74LS86
74LS86
U5:A
1
3 U3:C
2 9
8
74LS08 10

U5:B 74LS32
4
6
5

74LS08

U4:D
U4:C 12
9 11
8 13
10
74LS86
74LS86
U5:C
9
8 U3:D
10 12
11
74LS08 13

U5:D 74LS32
12
11
13

74LS08

D5 D2 D1 D3 D4
R1 R2 R3 R4 R5 LED-BIBY LED-RED LED-YELLOW LED-GREEN LED-BLUE
330 330 330 330 330 R6 R7 R8
330 330 330
3.2. APLICACIÓN SUMADORES

A3 A2 A1 A0 B3 B2 B1 B0 C4 S3 S2 S1 S0
0
0
0
0

0
0
0
0

1
0
0
0
0
C4
A3

A2

A1

A0

B3

B2

B1

B0

S3

S2

S1

S0
A1

B1

A2

B2

A3

B3
U25
A0

B0

NOT

U22 U23 U24

XOR XOR XOR
U21
XOR

C4
S1

S2

S3
U6 U11 U16
S0

U7 U12 U17
U1
U2
XOR XOR XOR
XOR XOR XOR
XOR U8 U13 U18
XOR U9 U14 U19
U3 U10 U15 U20
U4
U5
AND AND AND
AND AND AND
AND OR OR OR
AND
OR
 "B" "A"
S3 S2 S1 S0
0
0
0
0

B3 B2 B1 B0 A3 A2 A1 A0
"F" D5 D4 D3 D2
0
0
0
0

0
0
0
0
S3

S2

S1

S0

B3

B2

B1

B0

A3

A2

A1

A0
U25
2 9
A0 F0
23 10
A1 F1
21 11
A2 F2
19 13
A3 F3
1 14
B0 A=B
22 16
B1 CN+4
20 17
3.3. UNIDAD ARITMÉTICA LÓGICA (ALU)

B2 G
18 15
B3 P
CN 1 CN 7
CN U26
NOT
6
S0
5
S1
4
S2
3
S3
8
M
D1 SALIDA DE ACARREO
74LS181
M 0 M
 U5:D
12 U6:D U4:D
11 12 12
13 11 11
13 13 D1
74LS08
R1
74LS08 74LS08 330
LED-BIBY
U7:A
U6:A 1 D2
1 U4:A 3
R2
3 1 2 330
2 3 LED-BIBY
2 74LS08
DSW1(COM1) 74LS08 D3
74LS08
R3
U7:B 330
4 LED-BIBY
U6:B U4:B 6
4 4 5 D4
6 6
R4
5 5 74LS08 330
LED-BIBY
U20:A 74LS08 74LS08
1 U7:C D5
3 9
R5
2 U6:C U4:C 8 330
9 9 10 LED-BIBY
74LS08 8 8
10 10 74LS08 D6
R6
74LS08 74LS08
R12 330
100 Z0 R7
LED-BIBY
D7
R11
330
100
U5:A LED-BIBY
1
3 D8
R10 DSW1 R8
Xo
2
8 OFF ON 1
100 330
X1
7 2 74LS08 LED-BIBY
Z1
6 3
R9
X2 Z2
5 4
100
U3
X3
DIPSW_4
U1 U2 10 9
A1 S1
10 9 10 9 8 6
A1 S1 A1 S1 A2 S2
8 6 8 6 3 2
A2 S2 A2 S2 A3 S3
3 2 3 2 1 15
A3 S3 A3 S3 A4 S4
1 15 1 15
A4 S4 A4 S4
11
B1
11 11 7
U5:B 7
B1
B2
7
B1
B2
4
B2
B3
4 4 4 16
B3 B3 B4
6 16 16
B4 B4
5 13 14
C0 C4
13 14 13 14
C0 C4 C0 C4
74LS08 74LS83
74LS83 74LS83
U5:C
9
8
10
74LS08
R16
100
R15 DSW2 Y0
Y1
8 OFF ON 1
100
7 2
Y2
6 3
R14 5 4
100
R13
DIPSW_4
Y3
100
3.4. MULTIPLICADORES
3.6. Simulaciones en VHDL
3.1 SUMADORES
3.2. APLICACIÓN SUMADORES
3.3. UNIDAD ARITMÉTICA LÓGICA (ALU)
3.4. MULTIPLICADORES