PRINFORME N°3

NOMBRE: RICHARD HENRY PLATA PAXI

CI: 13681399 LP
RU: 1766701
a) APLICACIÓN DE MULTIPLEXORES
PROTEUS
a1

a1) Multiplexores
C

D
A
B

RICHARD HENRY PLATA PAXI

3

U8:B
U8:A
74LS14
74LS14
4

U5:A U1

0
1
1
0
1 6 7
1X0 1Y a
3 5
1X1
2 4
1X2
3
1X3
74LS86
10 9
2X0 2Y b
11
2X1
12

D
A

B
2X2
13
2X3
U6:A 14
B A
1 2
A B
3 1
1E a
2 15
2E
U2 b
c
74LS32 6 74153 7
1X0 1Y c d
5
1X1 e
4
1X2 f
3
1X3 g
U6:B 10 9
2X0 2Y d
4 11
2X1
6 12
2X2
5 13
2X3
74LS32 14
B A
2
A B
1
1E
15
U7:A 2E
U3
1 6 74153 7
1X0 1Y e
3 5
1X1
2 4
1X2
3
1X3
74LS08
10 9
U7:B 2X0 2Y f
11
2X1
4 12
2X2
6 13
2X3
5
14
A
74LS08 2
B
1
1E
15
U6:C 2E
U4
9 6 74153 7
1X0 1Y g
8 5
1X1
10 4
1X2
3
1X3
74LS32
10 9
2X0 2Y
11
2X1
12
2X2
13
2X3
14
A
2
B
1
1E
15
2E
74153

a3
 0
0
1
0
a2) Multiplexores

D
RICHARD HENRY PLATA PAXI

D
A

B
1
U8:A
74LS14

~a

~e
~c
~a

e
c
~b a
U1 U2 U5 ~c b
~d c
4 5 4 5 4 5
X0 Y X0 Y X0 Y ~e d
3 3 3
X1 X1 X1 ~f e
2 6 2 6 2 6
X2 Y X2 Y X2 Y ~g f
1 1 1
X3 X3 X3 g
15 15 15
X4 X4 X4
14 14 14
X5 X5 X5
13 13 13
X6 X6 X6
12 12 12
X7 X7 X7
11 11 11
A A A
10 10 10
B B B
9 9 9

~b
C C C

~f
b

f
7 7 7
E
U3 E
U4 E
U6
4 74HC151 5 4 74HC151 5 4 74HC151 5
X0 Y X0 Y X0 Y
3 3 3
X1 X1 X1
2 6 2 6 2 6
X2 Y X2 Y X2 Y
1 1 1
X3 X3 X3
15 15 15
X4 X4 X4
14 14 14
X5 X5 X5
13 13 13

~d
X6 X6 X6
12 12 12
X7 X7 X7
11 11 11
A A A
10 10 10
B B B
9 9 9

~g
C C C

g
7 7 7
E E E
U7
74HC151 74HC151 4 74HC151 5
X0 Y
3
X1
2 6
X2 Y
1
X3
15
X4
14
X5
13
X6
12
X7
11
C A
10
B B
9
A C
7
E
74HC151

WINCUPL
a1)

QUARTUS II VHDL
VERILOG
a3)
PROTEUS
a3) Multiplexores
D

RICHARD HENRY PLATA PAXI

D
1

U8:A
74LS14
~a

~e
~c
2

e
c

U1 U2 U5
4 5 4 5 4 5
X0 Y X0 Y X0 Y
3 3 3
X1 X1 X1
2 6 2 6 2 6
X2 Y X2 Y X2 Y
1 1 1
X3 X3 X3
15 15 15
X4 X4 X4
14 14 14
X5 X5 X5
13 13 13
X6 X6 X6
12 12 12
X7 X7 X7
0
0
1
0

11 11 11
A A A
10 10 10
B B B
9 9 9
~b

C C C
~f
b

7 7 7
E
U3 E
U4 E
U6
4 74HC151 5 4 74HC151 5 4 74HC151 5
X0 Y X0 Y X0 Y
3 3 3
C

D
A

X1 X1 X1
2 6 2 6 2 6
X2 Y X2 Y X2 Y
1 1 1
X3 X3 X3
15 15 15
X4 X4 X4
14 14 14
X5 X5 X5 ~a
13 13 13
~d

X6 X6 X6 ~b a
12 12 12
X7 X7 X7 ~c b
~d c
11 11 11
A A A ~e d
10 10 10
B B B ~f e
9 9 9
~g

C C C ~g f
g

g
7 7 7
E E E
U7
74HC151 74HC151 4 74HC151 5
X0 Y
3
X1
2 6
X2 Y
1
X3
15
X4
14
X5
13
X6
12
X7
11
C A
10
B B
9
A C
7
E
74HC151
 WINCUPL

QUARTUS II VHDL
QUARTUS II VERILOG
b) APLICACIÓN DE DEMUX/DECOD
b1
PROTEUS
DEMUX

b1) UNIV.RICHARD HENRY PLATA PAXI

U1
23 1 U2:A U2:B
0 22
A
B
0
1
2 1 4
21 3 3 6 U4
1 20
C 2
4 2 5

1 18
D 3
4
5
6 74LS00 74LS00
0 X
E1 5
19 7
0 E2 6
7
8 NAND_4
9
8
10
9
11
10
13
11 U3:A U2:C
14
12 U3:C
15 1 10
13
14
16
17
2
13
12
9
8 9
10 8
Y
15 U3:B U2:D 1
11
74HC154 3 74LS10 13 74LS00
4 6 11 74LS10
5 12

74LS10 74LS00

QUARTUS II VHDL
QUARTUS II VERILOG
b3)

DEMUX
1
0
0
1

b3) UNIV.RICHARD HENRY PLATA PAXI

C

D
A

U1 U3:A U4:A
23 1 1 1 U4:B U5:A
A A 0 U4:C
22 2 2 12 3 4 1
B B 1
21 3 13 2 6 3 10
C
D
20
C
D
2
3
4
5 74LS10 74LS00
5 2
9
8
1 Y
4
18 6 74LS00 74LS00
E1 5
19 7 74LS00
E2 6
8
7 U2:C U2:B
9
8
10 10 4
9 U4:D
11 8 6
10
13 9 5 13
11
12
14
15 1
U2:A
74LS00 13
U2:D
74LS00 12
11
0 Z
13
16 3 11
14
17 2 12 74LS00
15
74HC154 74LS00 74LS00
QUARTUS II VHDL
QUARTUS II VERILOG
d)
PROTEUS
UNIV.PLATA PAXI RICHARD HENRY
A B C D
b7 b6 b5 b3
0
0
0
0
0
1
0

Un error a Introducir
0
1
1
1

U2:C
9
8
Circuito TX 10
b1

74HC86
U2:D
U1:A 12
1 U1:B 11
b2
3 4 13
2 6
5 74HC86
74HC86 U3:A
74HC86 1
3
b3
2

U1:C 74HC86
9 U1:D U3:B
10
8 12
11
4
6
b4
Codigo Corregido
13 5
74HC86
74HC86 74HC86
U3:C
9
8
U2:A b5
10
1 U2:B
3 4 74HC86
U3:D R1
2 6 10k
5 12 U8:A
74HC86 11 1
74HC86 13
b6

b7
2
3
0 A
74HC86
U4:A 74HC266
1
3
b7
2
R2
74HC86 10k
U8:B
Circuito TR 5
4
B
Detector De Error b6
6
1

74HC266
U4:B
4 U4:C R3
6 9 U4:D 10k
5 8 12 U7
0

10 11 1 15 U8:C
A Y0
b7 b6 b5 b4 b3 b2 b1 74HC86 13 2 14 8
74HC86
74HC86
3
B
C
Y1
Y2
Y3
13
12
b5
9
10
1 C
Cod. Hammin Generado 11
b7

b6

b5

b4

b3

b2

b1

Y4
6 10 74HC266
E1 Y5
4 9
U5:A E2 Y6
5 7
U5:B E3 Y7
1
3 4 U5:C 74HC138 R4
2 6 9 10k
5 8 U8:D
0

74HC86 10 12

Cod. Hammin Con Error Generado

74HC86
74HC86
b4
13
11
0 b4
74HC266
U5:D
12 U6:A
11 1 U6:B
13 3 4 R5
2 6 10k
74HC86 5 U9:A
74HC86 1
74HC86
b3
2
3
1 D
74HC266
0
1
0

P3P2P1
Posiscion Del Error
R6
10k
U9:B
5

b2
6
4
0 b2
74HC266

R7
10k
U9:C
8

b1
9
10
0 b1
74HC266

XILIS VHDL
e) TRANSCODIFICADOR
PROTEUS
e) TRANSCODIFICADOR
A1

A0

RICHARD HENRY PLATA PAXI

3

U5:B U5:A
74LS14 74LS14
U1
4

1
0
1
0
6 7

1
1
0
1
1X0 1Y B3
5
1X1
4
1X2
3
U3:B U3:A 1X3
4 1 10 9
2X0 2Y B2
6 3 11
2X1
5 2 12

A3

A2

A1

A0

B3
B2
B1
B0
U3:C 2X2
13
2X3
10 74LS00 74LS00 BCD EX-3 BCD 2421
8 14
A
9 2 A3 A2 A1 A0 B3 B2 B1 B0
B
1
1E
74LS00 15 3 0 0 1 1 0 0 0 0
U4:A 2E
U2
1 6 74153 7 4 0 1 0 0 0 0 0 1
1X0 1Y B1
3 5
1X1
2 4 5 0 1 0 1 0 0 1 0
U4:B U3:D 1X2
3
1X3
4 13 74LS86 6 0 1 1 0 0 0 1 1
6 11 10 9
2X0 2Y B0
5 12 11 7 0 1 1 1 0 1 0 0
2X1
12
2X2
74LS86 74LS00 13 8 1 0 0 0 1 0 1 1
2X3
14 9 1 0 0 1 1 1 0 0
A2 A
2
A3 B
1 10 1 0 1 0 1 1 0 1
1E
15
2E
11 1 0 1 1 1 1 1 0
74153
12 1 1 0 0 1 1 1 1

WINCUPL
QUARTUS II VHDL
QUARTUS II VERILOG
f) APORTE DEL ALUMNO
PROTEUS
Aporte
RICHARD HENRY PLATA PAXI

f
U1
10
1 12
A0
A1
13
1 15
A2
A3
9
0 11
B0
B1
14
0 1
B2
B3
2 7
A<B QA<B
3 6
A=B QA=B
4 5
1 A>B
U2 QA>B
10 74HC85 U3:A F
1 12
A0
A1
1
13 3
1 15
A2
A3
2
1
9
0 11
B0
B1
74LS32
14
B2
1
B3
2 7
A<B QA<B
3 6
A=B QA=B
4 5
1 A>B QA>B
74HC85
0
I0 0
0
 WINCUPL

QUARTUS II VHDL