Documentos de Académico
Documentos de Profesional
Documentos de Cultura
Tesis
Tesis
___________________________________________
TESIS
PRESENTAN:
ASESORES:
OBJETIVOS PARTICULARES
I
JUSTIFICACIÓN
Con nuestro proyecto se resuelven los problemas del control de personal a la hora
de entrada en una instalación que lo requiera, con fechas y horas exactas que
entran, sin tener a una o varias personas a cargo de esta labor, todo es en
automático al pasar la tarjeta RFID. El segundo acceso del Smartphone que se
comunica con el Bluetooth no lo han implementado aun en ninguna empresa, es
por eso que lo consideramos innovador. Estas tecnologías son muy poco usadas
en México, esto puede abrir un nuevo mercado, debido a que se maneja un bajo
costo.
II
RESUMEN
A lo largo de este trabajo se exponen las bases teóricas, técnicas y prácticas que
conllevan la realización de este prototipo.
Este capítulo analizara los resultados finales del desarrollo del proyecto y expondrá
aspectos importante para considerar su posterior mejora e implementación dentro del área
de seguridad.
III
ABSTRACT
Along this work there are exhibited the theoretical, technical and practical bases
that bear the achievement of this prototype.
In this chapter there are exhibited the precedents of the safety systems and some
bases that they characterize to an access control, together with the problematic ones and
general concepts that include the safety and technology.
This chapter will analyze the final results of the development of the project and will
exhibit aspects important to consider its later progress and implementation inside the
IV
HOJA ADMINISTRATIVA
OBJETIVO . . . . . . . . I
JUSTIFICACIÓN . . . . . . . II
RESUMEN . . . . . . . . III
ABSTRACT . . . . . . . . IV
ÍNDICE CAPITULADO . . . . . . V
INTRODUCCION . . . . . . . VII
V
CAPÍTULO 3: DISEÑO DEL SISTEMA DE CONTROL DE ACCESO Y
REGISTRO
CONCLUSIONES . . . . . . . . . pág.80
GLOSARIO . . . . . . . . . . pág.81
ABREVIATURAS . . . . . . . . . pág.83
BIBLIOGRAFIA . . . . . . . . . pág.85
ANEXOS
Índice De Imágenes Y Tablas
Capitulo 1
1.1: Manual de seguridad proporcionado por Grupo Paladín. . . pág.2
1.1.1: Neandertal protegiéndolos. . . . . . . pág.3
1.1.2: Ensamblaje de tanques durante la II guerra mundial. . . pág.5
1.1.3: Categorías de la seguridad física. . . . . . pág.6
1.2.1: Estructura de una base de datos en SQL. . . . . pág.7
1.2.1.1: Herman Hollerith. . . . . . . . pág.8
1.2.1.2: Disquete de 3” ½ y 8”. . . . . . . pág.10
1.2.1.3: Logo de Oracle*. . . . . . . . pág.11
1.2.1.4: Captura de pantalla de funciones de un servidor SQL. . . pág.12
1.2.1.5: Estructura del modelo de base de datos OAI-PMH. . . pág.13
1.3: Ejemplos de biometría: palma de una mano, dactilar e iris. . . pág.15
1.3.1: Diagrama de un sistema de control de accesos comunicado por TCP/IP.
. . . . . . . . . . pág.17
1.5: Portada del manual de medios técnicos de seguridad. . . pág.19
Capitulo 2
2.1: Arduino UNO visto desde arriba. . . . . . pág.22
2.1.1: Resumen de características de alimentación y operación del Arduino UNO.
. . . . . . . . . . pág.23
VI
2.7.1: Cerradura Electrónica sd-997bq. . . . . . pág.34
Capitulo 3
3.10: Capacitores sugeridos por el fabricante del 7805 para corriente directa
. . . . . . . . . pág.45
3.12: Diseño final para l placa de la fuente de 12 volts e corriente alterna . pág.46
VI
3.17: Se muestra la lectura del RFID y la comparación de los datos obtenidos con
los ya registrados. . . . . . . . . pág.50
VI
3.36: Fotografía del gabinete para el lector de RFID. . . . pág.65
3.37: Fotografía del interior del gabinete para el lector de RFID. . . pág.65
Capitulo 4
VI
INTRODUCCIÓN
Con el paso del tiempo dichos registros van cambiando con el surgimiento de
nuevas tecnologías, podemos ver que los registros cambiaron a documentos
escritos a mano, a documentos mecanografiados para pasar después a
documentos digitales, con su respectivo avance se ha hecho más fácil el manejo de
esta información, pero también ha sido necesario implementar nuevas tecnologías
para poder manejar la información de forma más segura y eficiente para poder hacer
mejor uso de la misma.
VII
CAPITULO 1: MARCO CONTEXTUAL: LA SEGURIDAD Y LA TECNOLOGIA
Debido esto ha sido necesario crear medidas y normas de seguridad que aseguran la
integridad física de los elementos de trabajo así como los intereses que persiguen la institución
o dependencias.
1
Enciclopedia Salvat, S. A. Barcelona: Salvat editores.1971
1
Fig. 1.1: Manual de seguridad proporcionado por Grupo Paladin. Recuperado de:
http://www.manualdeseguridad.com.mx/aprende_a_protegerte/ Marzo 2015
2
Fig. 1.1.1: Neandertal protegiéndose.
Recuperado
de:http://3.bp.blogspot.com/_Dwdjcey2PY4/So2iXXHqZ5I/AAAAAAAAXSA/swSarPXTF1A/s320/
Neanderthal-cazando.jpgMarzo 2015
Al aumentar el número de grupos aparecieron individuos que buscaban quedarse con los
recursos que habían obtenido, esto más que nada se observa en los grupos pequeños o que no
eran buenos cazadores, al tener suministros limitados necesitaron medidas que cuidaran lo
poco que obtenían y así apareció nuestro primer elemento de seguridad, un vigilante.
Aun así el papel de él vigía o vigilante permaneció siempre, su trabajo fundamental era, y
es aun, hacer recorridos periódicos en un área asignada para cuidarla, sin más que una fuente
de iluminación y en ocasiones un instrumento de defensa, un arma blanca o de fuego.
3
Fue hasta la segunda guerra mundial que fue necesario nuevos sistemas de protección
además de establecer medidas de control para proteger las fábricas que proporcionaban el
armamento y suministros que apoyaban las operaciones militares, su función era evitar
espionaje, daños, robo y sabotaje.2
2
Edgar Tovar. Teoría de seguridad y protección. [Consulta 4 Marzo 2015]. Disponible
en:http://www.monografias.com/trabajos82/teoria-seguridad-y-proteccion/teoria-seguridad-y-proteccion2.shtml
4
Fig.1.1.2: Ensamblaje de tanques durante la II guerra mundial.
Recuperado de: http://k39.kn3.net/8/D/C/B/3/3/7DF.jpg Marzo 2015
5
Fig. 1.1.3: Categorías de la seguridad física.
Recuperado de: http://www.isaca.org/Images/journal/j0906-seguridad2.gif
Marzo 2015
3
Rafael Camps Paré, Luis Alberto Casillas Santillán, Carme Martín Escofet. Bases de datos. Barcelona: Eureca Media,
SL, 2005. ISBN: 84-9788-269-5
6
Fig. 1.2.1: Estructura de una base de datos en SQL.
Recuperado de: http://www.scottgu.com/blogposts/linq4/step0.jpg
Marzo 2015
4
Herman Hollerith: está considerado como el primer informático, es decir, el primero que logra el tratamiento
automático de la información
7
Fig. 1.2.1.1: Herman Hollerith.
Recuperado de: http://www.biografiasyvidas.com/biografia/h/fotos/hollerith.jpg
Marzo 2015
Para hacer el censo de Estados Unidos de 1880 se tardaron 7 años para analizar la
información para obtener resultados, pero la máquina de Herman Hollerith inventada en 1884
con la cual se manejó la información de él censo de 1890, usando sistemas mecánicos, dio
resultados dos años y medio después, mostrando una reducción significativa del tiempo de
En la década de los 50 se dio origen a las cintas magnéticas que se utilizaron para
satisfacer las necesidades de información de las nuevas industrias. Con este mecanismo se
empezó a automatizar el manejo de la información. Consistía en leer una cinta o más y pasar los
datos a otra cinta simulando un sistema de Backup, que consiste en hacer copias de respaldo
8
para guardar en un medio extraíble la información importante. Estas cintas únicamente podían
ser leídas de forma secuencial y ordenadamente.5
En los 60 nacen los discos de 3 ½ que fueron un adelanto muy efectivo en las tecnologías
que manejan información debido a que no era necesario llevar una secuencia de lectura para
consultar información, además de tardar milisegundos la recuperación de la información. Estos
discos dieron inicio a las bases de datos digitales y las redes de información, los programadores
empezaron a crear métodos de búsqueda de información en estas bases de datos como listas y
árboles de información.
5
Reyes. Evolución de las bases de datos [Blog]. [Consulta: 12 Febrero 2015]. Disponible en: http://evolucion-
bd.blogspot.mx/
9
Fig.1.2.1.2: Disquete de 3” ½ y 8”.
Durante los 70 Edgar Frank Codd6 (1923-1923) en un artículo “Un modelo relacional de
datos para grandes bancos de datos compartidos” (A Relational Model of Data for Large Shared
Data Banks) en 1970, definió el modelo relacional y publico una serie de reglas para la
evaluación de administradores de sistemas de datos dando lugar a las bases de datos racionales.
En base a estos aportes Larry Ellison7 desarrollo la base de datos Oracle, que es un
sistema de administración de bases de datos que se destaca por su estabilidad, escalabilidad y
multiplataforma.
6
Edgar Frank Codd: fue un científico informático Ingles, conocido por sus aportes a la teoría de bases de datos
relacionales.
7
Larry Ellison: Es un americano programador, empresario de internet. Era el director ejecutivo de la compañía
Oracle Corporation.
10
gracias a un proyecto de IBM que desarrolló técnicas para la construcción de bases de datos
llamado System R8 .
A principios de los 90 se crea el lenguaje de alto nivel SQL que está orientado a
consultas. El programa analiza grandes cantidades de información con lo cual especificar los
detalles de operación requeridos es más eficiente. Los grandes distribuidores de bases de datos
empiezan a incursionar con la venta de bases de datos orientados a objetos.
8
System R es un sistema de base de datos experimental, diseñado para demostrar la funcional del modelo
relacional de datos aplicados creado en 1974
9
Oracle: Es el segundo mayor fabricante de software por ingresos, después de Microsoft
11
Fig. 1.2.1.4: Captura de pantalla de funciones de un servidor SQL.
Recuperado de:
http://www.devart.com/dbforge/sql/sqldecryptor/images/screenshot_sql_decryptor_main.png
Marzo 2015
Actualmente existen una gran cantidad de opciones en línea que permiten hacer
búsquedas de información dependiendo de las necesidades del usuario, actualmente es más
10
World Wide Web: Red informática Mundial o comúnmente conocida como la Web.
12
usual el manejo de bases de datos que cumplan con el OAI-PMH11 que permite una gran
cantidad de almacenamiento de información, una mayor visibilidad y acceso científico o
general.
11
Base de Datos. [Consulta: Marzo 2015]. Disponible en: http://www.openarchives.org/pmh/
13
para usos posteriores, también la capacidad de las bases de datos está en constante aumento
con la invención de nuevos discos con mayor capacidad de almacenamiento.
Estos sistemas tienen la función de regular la entra a un recinto, es decir saber quién
está accediendo a un determinado lugar. Esto tiene el propósito de mantener alejadas personas
sin autorización a un área en particular.
Para cumplir con esta función se han usado personal de seguridad o de registro, pero
actualmente esto se lleva a cabo por medios electrónicos que dan mayor seguridad de una
forma más controlada.
Para cumplir con su función es necesario que la persona que intenta acceder posea un
elemento que lo identifique, digamos una tarjeta, una contraseña o un llave, en casos más
sofisticados se puede detectar una cualidad física como huellas dactilares o iris, si la información
del elemento que se está utilizando para acceder es válida para el sistema, este permitirá el
acceso, de lo contario no deberá por ningún motivo permitir el acceso.
14
Fig. 1.3: Ejemplos de biometría: palma de una mano, dactilar e iris.
Recuperado de: http://www.cordobadactilar.com.ar/img/biometriaAplicada.jpg Marzo 2015
Estas herramientas cada vez son más utilizadas en las industrias, para llevar un control de los
trabajadores que ingresan y evitar situaciones de riesgo, podrían ser desde daños a los
trabajadores hasta daños a los elementos o intereses de la empresa misma.
12
Cita tomada del artículo: Control De Acceso Electrónico, Sistema Electrónico Control de Accesos. Disponible n el
sitio web: http://www.empresayseguridad.com/
15
1.3.1 Elementos de un Control de Accesos
Las diferentes partes del control de accesos13 pueden ser agrupados como:
d) Dispositivos de salida: Son los elementos que realizan las acciones que el
controlador dependiendo de las condiciones leídas decide, como abrir puertas,
activar alarmas, cerrar cortinas, etc.
13
Luis Cosentino. Control de accesos. Esquema, historia y esquema básico, Nro. 45(2009). P. 160. Versión digital
disponible en el sitio: http://www.rnds.com.ar/
16
e) Red de comunicaciones: Es la línea de comunicación con la que el controlador
intercambia información con los controladores o con otros canales de información.
Marzo 2015
Debido a las necesidades diferentes de cada instalación además de los elementos necesarios
o requeridos por las mismas, es difícil agruparlas o clasificarlas.
17
Podemos decir que las instalaciones que requieren seguridad dependen de la disposición de
la construcción o de las especificaciones que quiere el comprador, por ejemplo, un conjunto de
oficinas puede ser agrupado en un sistema único de seguridad que al violarse cualquier área de
trabajo suene una alarma, y por el contario, en una planta que cuenta con varias áreas de
trabajo a diferentes condiciones de operación requiere de varias alarmas que indiquen que área
en específico requiere la atención del personal.
Entonces podemos decir que todas las instalaciones requieren seguridad, lo que es variable
es el nivel de seguridad que debe tener la instalación dependiendo de las características del
mismo (digamos temperatura, tamaño, condiciones de operación), y la cantidad de elementos y
sus características de operación (sensores, alarmas, botones de emergencia/alarma, sistemas de
control, módulos de control).
18
El objetivo principal de la seguridad física es mantener la seguridad de las personas que ahí
trabajan, los elementos producidos, los procesos laborales y la propiedad es decir el edificio.
Existen normas y manuales que regulan o dan indicaciones sobre la instalación de sistemas
de seguridad o métodos de seguridad, sin embargo, no se pude determinar una norma estándar
que aplique a todas las instalaciones, un sistema de seguridad tiene que ser desarrollado
dependiendo de los objetivos de seguridad que se desean obtener.
Dependiendo de los riesgos que se observan que pude sufrir una instalación se procede a
determinar elementos de seguridad que evitaran daños al personal o a la institución misma.
19
Entonces determinamos el nivel de seguridad dependiendo del área a proteger, o las
especificaciones que se desean. Como mencionamos no hay una norma que generalice todos los
elementos de seguridad, entonces se toman normas que funcionan o aplican a la instalación
dando una cierta libertad para aplicar elementos de seguridad.
20
CAPITULO 2: ANÁLISIS TÉCNICO DE LOS MODULOS RFIDPARA MAYOR SEGURIDAD
14
(ARDUINO, 2014)“Arduino Uno”. Especificaciones técnicas. Disponible en:
http://arduino.cc/en/Main/arduinoBoardUno
21
Fig. 2.1: Arduino UNO visto desde arriba.
Recuperado de:http://arduino.cc/en/uploads/Main/ArduinoUno_R3_Front.jpg
Marzo 2015
El software de Arduino incluye un monitor de serie que permite que los datos simples
de texto se envíen hacia la placa el Arduino UNO gracias a una biblioteca de
SoftwareSerial. Las terminales RX, TX y LED (pin 13) parpadearán en el tablero cuando se
están transmitiendo datos a través del chip de USB a serie y conexión USB al ordenador.
Se decidió utilizar esta plataforma por la facilidad de programación en el lenguaje C++
de su interfaz y su carga al microcontrolador por medio de un puerto USB. También tiene
una mayor compatibilidad con otros tipos de módulos y complementos. Además de tener
una asignación de puertos de entrada y salida más simple.
22
implementar una rutina de comunicación entre el microcontrolador y los módulos que
proporcionaran la información para procesar y archivar en la base de datos.
Microcontroladores ATmega328
Tensión de funcionamiento 5V
Voltaje de
7-12V
entrada(recomendado)
SRAM 2 KB ( ATmega328 )
EEPROM 1 KB ( ATmega328 )
23
2.2 BASE DE DATOS
Una base de datos es un “Almacén” que nos permite guardar grandes cantidades de
información de forma organizada para que luego podamos encontrar y utilizar fácilmente.
Cada base de datos se compone de una o más tablas que guarda un conjunto de datos.
Cada tabla tiene una o más columnas y filas. Las columnas guardan una parte de la
información sobre cada elemento que queramos guardar en la tabla, cada fila de la tabla
conforma un registro.
Ejemplo Se tiene una Empresa que necesita tener la información de las partes que
utiliza, los Proveedores de la empresa y el detalle de que partes suministra un proveedor.
Se sabe que un proveedor puede suministrar 0 ó más partes y que una parte puede ser
suministrada por 0 ó más proveedores. Nuestra base de datos podría ser vista como lo
ilustra la figura a continuación15 :
15
Marco Antonio Cruz Chávez. Conceptos básicos de base de datos. [Consulta 6 de Marzo 2014]. Disponible
en: http://www.gridmorelos.uaem.mx/~mcruz//cursos/miic/bd1.pdf
24
Fig. 2.2.1: Modelo Relacional de la Base de Datos de Partes-Proveedores y Pedidos
del Ejemplo
25
El uso de las bases de datos nos permitirá, por sus características, asegurar la
información recibida y almacenada para su posterior manejo o consulta. Al ser el objetivo
llevar el control de accesos de los trabajadores en una instalación, además de las áreas
donde pueden acceder, el uso de la base de datos será indispensable para restringir la
entrada a determinadas áreas, saber qué persona accedió a determinada hora y de ser
necesario sancionarla.
16
Lenguajes de programación. [Consulta 6 de Marzo 2014]. Disponible en:
http://es.kioskea.net/contents/304-lenguajes-de-programacion
26
Fig.2.3.1: Ejemplo de un programa simple en lenguaje C++.
Por esto, es de importancia que el lenguaje sea Visual C, al manejar la hoja de cálculo en
Windows Excel.
17
Visual C. [Consulta 6 de Marzo 2014]. Disponible en: http://es.wikipedia.org/wiki/Visual_C%2B%2B
27
2.4 NFC
NFC, es una plataforma abierta pensada desde el inicio para teléfonos y dispositivos
móviles. Su tasa de transferencia puede alcanzar los 424 kbit/s por lo que su enfoque más
que para la transmisión de grandes cantidades de datos es para comunicación instantánea,
es decir, identificación y validación de equipos/personas.
Recuperado: http://www.smythsys.es/6369/que-es-el-nfc-que-estan-poniendo-en-las-
tarjetas-de-credito-ventajas-y-peligros/ Marzo 2014
28
2.4.1.Usos de la tecnología NFC
Pago con el teléfono móvil: sin duda alguna, es la estrella de los usos del NFC. La
comodidad de uso y que el gasto pueda estar asociado a nuestra factura o una cuenta
de banco son armas muy poderosas y esta tecnología está camino de ser el método de
pago del futuro.
Precisamente en España ha finalizado una de las mayores pruebas con esta tecnología
como método de pago. Ha sido en Sitges, con la colaboración de Visa, La Caixa y Telefónica.
2.5 RFID
18
RFID. [Consulta 5 de Marzo 2014]. Disponible en: http://es.wikipedia.org/wiki/RFID
29
Las etiquetas RFID son unos dispositivos pequeños, similares a una pegatina, que
pueden ser adheridas o incorporadas a un producto, un animal o una persona.
Contienen antenas para permitirles recibir y responder a peticiones por radiofrecuencia
desde un emisor-receptor RFID. Las etiquetas pasivas no necesitan alimentación eléctrica
interna, mientras que las activas sí lo requieren. Una de las ventajas del uso de
radiofrecuencia es que no se requiere visión directa entre emisor y receptor,por ejemplo,
como el de infrarrojos.
2.6 TAGS
Las Tags19 o las etiquetas lo podemos encontrar como solo lectura, como por ejemplo
el EM-4100 está diseñado para funcionar con el lector de tarjetas RFID. Es un identificador
pasivo con un ID único de 10 dígitos. Existen 2 tipos de Tags, las activas y las pasivas.
Las Tags RFID activas poseen su propia fuente de poder. Una batería incorporada
energiza el microchip y el transmisor. Pueden recibir y transmitir señales a largas
distancias.
Las Tags pasivas no poseen batería, utilizan la energía del lector. Cuando el Tag
recibe la señal del lector, utiliza la energía recibida para responderle al lector con la
información solicitada. Son menores en tamaño, más livianas y tienen una mayor vida útil.
Existen Tags de lectura y escritura el cual contiene una memoria en su interior en la cual
se pueden almacenar cualquier tipo de información.
19
Tags RFID. [Consulta 5 de Marzo 2014]. Disponible en: http://www.rfidpoint.com/fundamentos/tags-rfid/
30
Fig. 2.6. Diferentes Tipos de Encapsulado de las Tags
Para que las Tags sean leídas necesita estar de 10cm a 5cm del dispositivo lector de
RFID, esto también va a depender del tipo lector, la antena que este contenga en su interior
y del Tag.
31
Dentro de una Tag puede almacenar una gran variedad de datos. La cantidad real de
datos varía en función del tipo de Tag utilizado. Por lo general, esta información se
almacena en un formato de datos específico NDEF de manera se puede leer con fiabilidad
por la mayoría de los dispositivos y teléfonos móviles.
Las Tags se pueden bloquear de tal modo que todos los datos que ahí se han
almacenado no pueden ser borrados ni alterados. Para la mayoría de las Tags es un proceso
unidireccional, así que una vez bloqueada, no podrá ser desbloqueada. La Tag se puede
escribir varias veces antes de ser bloqueada.
20
SECO-LARM. SD-997A-DQ. [Consulta 5 de Marzo 2014]. Disponible en: http://www.seco-
larm.com/DeadbtASp.htm
32
Interruptor magnético sensitivo para determinar la posición de la puerta para
un aseguramiento positivo.
Si la puerta no está cerrada apropiadamente el solenoide va a tratar de asegurar varias
veces y después dejará de trabajar, esto para prevenir que el solenoide se queme. Una
vez que la puerta está cerrada apropiadamente va a asegurar automáticamente.
Se puede usar con un teclado digital para alta seguridad sin usar llave.
Se conecta fácil con el teclado electrónico de SECO-LARM modelo SK-983A.
Conveniente para aplicaciones tipo oficina. Incluye todo el material necesario.
Diseño angosto que permite usarse con la mayoría de puertas de metal.
No limitar orientación de la instalación.
Trabaja por medio de un solenoide.
Acero inoxidable para tener mejor fuerza y larga vida.
Tiempo de retardo ajustable para asegurar la puerta — (0, 3, 5, o 9 seg.).
Poder - 12 VCC, 880mA en activación, 320mA en espera.
Protección de sobre-corriente 1.5 Amp.
Cuerpo de la cerradura (cara de la placa) dimensiones - 77/8"x15/16" (200x32 mm).
Dimensiones de la placa pequeña - 39/16"x1"x11/8" (90x25x3 mm).
Enchufe: cavidad cónica especial de acero inoxidable (grueso 1.5mm~1.8mm).
Proporciona también un cerrojo eléctrico de seguridad para operación "modo salvo" es
decir si cerradura pierde la alimentación se mantiene abierta.
33
Fig. 2.7.1:CERRADURA ELECTRONICA SD-997BQ
34
CAPITULO 3: DISEÑO DEL SISTEMA DE CONTROL DE ACCESO Y REGISTRO
En este capítulo se muestran los elementos de programación, así como los cálculos,
diseños y especificaciones del proyecto, dando una breve explicación de su funcionamiento.
Entre las diferentes aplicaciones del transistor bipolar una de ellas el su uso como
interruptor, en el desarrollo del proyecto se usara esta configuración como un elemento de
control.
21
Luis Prat Viñas. Circuitos y dispositivos electrónicos. Fundamentos de electrónica. 6° edición. México: Alfa
omega, 1999.
35
Está construido por uniones NP, dependiendo de su unión puede ser un NPN o un
PNP en una estructura dual caracterizada por el sentido de la corriente que va de él material
P a N.
Tabla 3.1: Regiones de operación del transistor bipolar. Recuperado de: El libro “Circuitos
y dispositivos electrónicos” de Lluis Prat. Pg. 208. Marzo 2015
36
común que comparta la entra y la salida de la señal. En nuestro caso específico usaremos la
configuración emisor común22.
22
A. Nemane, Donald. Dispositivos y circuitos electrónicos. 4° edición. México: McGraw-Hill. 2012.
23
Luis Prat Viñas. Circuitos y dispositivos electrónicos. Fundamentos de electrónica. 6° edición. México: Alfa
omega, 1999.
37
Fig. 3.3: Idealización del interruptor en sus regiones de corte y saturación. Recuperado
de: El libro “Circuitos y dispositivos electrónicos” de Lluis Prat. Pg. 222. Marzo 2015
Estamos trabajando a una frecuencia baja por lo que usar esta configuración no
mostrara inconvenientes.
𝑖𝐶𝑀𝑎𝑥
𝑖𝐵 =
𝛽𝑇
900 𝑚𝐴
𝑖𝐵 = = 18 𝑚𝐴
50
38
Ahora determinaremos la resistencia de base que asegurara esta corriente, con los
valores de la fuente de activación del transistor, el voltaje que consumirá el diodo interno
del transistor en sus terminales BE y un diodo previo al circuito para evitar que la corriente
se regrese al elemento de control de conmutación. De la formula y sustituyendo valores
El voltaje de ruptura del diodo de base (𝑉𝐷𝐵 ) es igual a 1.1 V y el voltaje del diodo
interno del transistor es igual a 1.8 V. estos valores se deben de consultar en las hojas de
especificaciones de los componentes que se van a utilizar.
39
Fig. 3.4: Diagrama eléctrico del interruptor con el transistor TIP31. Imagen elaborada en
“Schematic” del programa de diseño Eagle. Marzo 2015
Fig. 3.5: Diseño final de la placa para el transistor como interruptor. Elabora en “Board”
del programa de diseño Eagle. Marzo 2015
24
Hambley, Allan R. Electrónica. 2° edición. México: Pearson, 2001.
40
3.2.1 Transformador
41
3.2.2. Diodos
Se deben de considerar los valores de corriente directa y voltaje pico inverso para
evitar que el diodo se caliente, se cortocircuite u opere mal. Esto con el fin de que la fuente
opere correctamente y evitar daños al circuito encargado de regular el voltaje.
42
Fig. 3.8: Algunos tipos de capacitores. Recuperado de:
http://www.factoriadoson.com/wp-content/uploads/2012/12/tipos-condensadores.jpg
Marzo 2015
Dicho de otra forma estos capacitores sirven de filtro. Dependiendo del valor de
estos voltajes será necesario adaptar el valor capacitivo del condensador, su tolerancia al
voltaje y su material de fabricación.
El dispositivo cuenta con tres terminales, una entrada de voltaje no regulado, una
terminal de tierra y una terminal de salida que entrega el voltaje regulado.
25
Boylestad, Robert L. Nashelsky, Louis. Electronic. Teoría de circuitos y dispositivos electrónicos. 10° edición.
México: Pearson: 2009
43
Al seleccionar este componente se debe consultar en sus hojas de especificaciones
cual es el voltaje y corriente máxima que tolera, esto con el fin de asegurar su correcto
funcionamiento de no considerar estos parámetros se llegaran a tener problemas o daños
en el circuito.
El sistema que abre o cierra la cerradura del prototipo usa un voltaje de 12 volts de
corriente directa a poco menos de un ampere. Es necesario elaborar una fuente de voltaje
rectificado con los elementos antes mencionados.
44
dispositivo recomiendan usar un capacitor de acoplo a la entrada del regulador de 0.33 µF
y un capacitor de desacoplo a la salida del amplificador de 0.1 µF. 26
Fig. 3.10: Capacitores sugeridos por el fabricante del 7805 para corriente directa.
Recuperado de: Hojas de especificaciones del KA78XX de FAIRCHILD. Marzo 2015
26
Hojas de especificaciones de la serie KA78XX/KA78XXA de FAIRCHIL Semiconductors. Disponibles en versión
digital en: https://www.fairchildsemi.com/datasheets/lm/LM7805.pdf
45
Fig. 3.11: Diagrama eléctrico de la fuente de 12 volts e corriente alterna. Imagen
elaborada en “Schematic” del programa de diseño Eagle. Marzo 2015
Figura. 3.12: Diseño final para l placa de la fuente de 12 volts e corriente alterna. Imagen
elabora en “Board” del programa de diseño Eagle. Marzo 2015
Este primer control de acceso está diseñado para registrar y dar acceso a los usuarios
que han sido previamente almacenados dentro de la base de datos que haya sido generada.
46
3.3.1 Diagrama Eléctrico Para El Primer Acceso
En el siguiente diagrama se puede observar cómo están conectados los componentes que
utilizaremos para el control de nuestro primer acceso empleando el lector de RFID, el LCD conectado
por I2C y el pulso de activación de la cerradura.
47
Fig. 3.14: Diagrama de flujo para el Primer Acceso. Imagen elaborada en
https://www.draw.io/ Marzo 2015
48
3.3.3 Programación del Arduino UNO
Las librerías SPI.h y MFRC522.h, son claves para el funcionamiento de nuestro lector de
tarjetas RFID, porque con ellas se crea la interfaz entre el Arduino uno y el lector de RFID
Fig. 3.15: Muestra la declaración de las librerías. Imagen tomada del compilador de
Arduino UNO. Marzo 2015
En esta parte del programa almacenaremos en una variable tipo array bidimensional
a los usuarios que ya están registrados y nombraremos como nuevo a la lectura que se
obtiene del lector de RFID, como se muestra en la siguiente figura:
Fig. 3.16: Muestra las variables empleadas para el control de usuarios. Imagen tomada
del compilador de Arduino UNO. Marzo 2015
49
Una vez que los datos son comparados y son correctos se envía en número de
usuario a la PC, la cual ejecutara una serie de sentencias que se describirán en este mismo
capítulo, regresando a Arduino el resultado de esta sentencia.
Fig. 3.17: Se muestra la lectura del RFID y la comparación de los datos obtenidos con los
ya registrados. Imagen tomada del compilador de Arduino UNO. Marzo 2015
Una vez que se han recibido los datos del PC, son comparados, según sea el caso de
comparación será desplegado un mensaje de bienvenida dando acceso a la entrada,
mensaje de retardo el cual también permite acceder y por ultimo desplegara el aviso de
fuera del horario de entrada comunicarse a supervisión.
50
Fig. 3.17.1: Muestra la comparación de los datos recibidos por el PC. Imagen tomada del
compilador de Arduino UNO. Marzo 2015
51
Fig. 3.17.2 Muestra la comparación de los datos recibidos del PC. Imagen tomada del
compilador de Arduino UNO. Marzo 2015
En este subtema veremos cómo es que fue creando el programa que registrara los
datos, tanto de llegada como la base de datos, que se podrá generar en una hoja de Excel.
52
3.3.5 Diagrama De Flujo Del Programa De Vba Para Excel Para El Primer
Acceso
Fig. 3.18: Diagrama de flujo para VBA para Excel. Imagen creada en
https://www.draw.io/ Marzo 2015
53
3.3.6 Programación de VBA para Excel
El entorno que tenemos para nuestra hoja de Excel consta de 3 botones, que realizan
acciones tales como “Abrir Puerto” la cual nos permite iniciar comunicación con Arduino
UNO, el siguiente botón “Horario De Entrada” nos permite indicar cuál será la hora de
entrada y la hora de llegada máxima, el ultimo botón “Agregar Usuario” nos indica cuantas
tarjetas RFID tenemos registradas permitiendo asignarle un nombre, almacenándolo en la
“Hoja2” del mismo libro.
Fig. 3.19: Muestra los botones creados para el usuario. Imagen tomada desde Excel.
Marzo 2015
54
En la macro del botón “abrir puerto” que se encuentra dentro del programa (Véase
en Anexo B),se configuran la velocidad de transmisión y el puerto por el cual serán enviados
y recibidos los datos también se configura la hoja de Excel agregando en las celdas A1, B1 y
C1, “Hr De Llegada”, “Nombre De Usuario” y “Estado De La Llegada”.
Fig. 3.20: Muestra la configuración de la primera hoja y del puerto serie. Imagen tomada
de VBA para Excel. Marzo 2015
Al dar clic en el botón “Horario De Entrada” muestra las siguientes pantallas emergentes.
55
Fig. 3.21: Ventana emergente para introducir la hora de entrada. Imagen tomada de
Excel. Marzo 2015
Fig. 3.22: Ventana emergente para ingresar la hora máxima de llegada. Imagen tomada
de Excel. Marzo 2015
Fig. 3.23: Macro para el botón “Horario de Entrada”. Imagen tomada de VBA para Excel.
Marzo 2015
El botón “Agregar Usuario” al hacer clic sobre el nos muestra las ventanas
emergentes que se muestran a continuación.
56
Fig. 3.24: Ventana emergente para seleccionar el número de usuario. Imagen tomada de
Excel. Marzo 2015
Fig. 3.25: Ventana emergente donde se agrega el nombre de usuario. Imagen tomada de
Excel. Marzo 2015
Una vez ingresados estos datos serán almacenados en la “Hoja2” en la cual de lado
izquierdo nos muestra el numero de ID y de lado derecho el nombre que le fue asignado.
Fig. 3.26: Muestra la base de datos. Imagen tomada de Excel. Marzo 2015
57
La macro para este botón es la siguiente.
Fig. 3.27: Muestra la macro del botón “Agregar Usuario”. Imagen tomada de VBA para
Excel. Marzo 2015
Se creó un segundo acceso para usuarios con mayores privilegios o con un cargo
que requiera mayor responsabilidad, por ejemplo en una empresa de químicos las personas
que tienen el control de aquellos que sean peligrosos o muy especiales.
Fig. 3.28: Diagrama eléctrico para el modulo HC-05 y el ATMEGA 328P. Recuperada del
software de diseño Eagle. Marzo 2015
58
Fig. 3.29: Diseño del PCB para el segundo control de acceso. Recuperada del software de
diseño Eagle. Marzo 2015
59
3.4.2 Diagrama De Flujo Para El Segundo Acceso En Arduino UNO
60
3.4.3 Programación De La Aplicación De Control Del Segundo Acceso
Fig. 3.31: Ventana 1: Screen1. Imagen recuperada del compilador MIT App Inventor 2
http://ai2.appinventor.mit.edu/. Marzo 2015
61
Fig. 3.32: Ventana 2 de control. Imagen recuperada del compilador MIT App Inventor 2
http://ai2.appinventor.mit.edu/. Marzo 2015
62
Fig. 3.33: Ventana 3: Registro. Imagen recuperada del compilador MIT App Inventor 2
http://ai2.appinventor.mit.edu/. Marzo 2015
Fig. 3.34: Ventana 4: Abrir puerta 2. Imagen recuperada del compilador MIT App Inventor
2 http://ai2.appinventor.mit.edu/. Marzo 2015
63
3.4.4 Programación Del Atmega328p Para El Control Del Segundo Acceso
Fig. 3.35: Programa para la apertura de la segunda puerta. Imagen tomada del
compilador Arduino UNO. Marzo 2015
64
3.5 Prototipo Final
Fig. 3.36: Fotografía del gabinete para el lector de RFID. Fotografía tomada por Gómez
Olguín Jhonathan Iván. Marzo 2015
Fig. 3.37: Fotografía del interior del gabinete para el lector de RFID. Fotografía tomada
por Gómez Olguín Jhonathan Iván. Marzo 2015
65
Fig. 3.38: Imagen del funcionamiento del registro dentro de Excel. Imagen tomada por
Gómez Olguín Jhonathan Iván. Marzo 2015
Fig. 3.39: Fotografía de la fuente de 12v con interruptor de cerradura. Fotografía tomada
por Jarquín Manuel Juan. Marzo 2015
66
Fig. 3.40: Fotografía del interior del gabinete de la fuente de 12v y el interruptor de la
cerradura. Fotografía tomada por Jarquín Manuel Juan. Marzo 2015
Fig. 3.41: Fotografía de la fuente de 5v. Fotografía tomada por Jarquín Manuel Juan.
Marzo 2015
67
Fig. 3.42: Fotografía del interior de la fuente de 5v. Fotografía tomada por Jarquín
Manuel Juan. Marzo 2015
Fig. 3.43: Fotografía del control de Bluetooth. Fotografía tomada por Jarquín Manuel
Juan. Marzo 2015
68
Fig. 3.44: Fotografía del interior del control de Bluetooth. Fotografía tomada por Jarquín
Manuel Juan. Marzo 2015
69
CAPÍTULO 4: ANÁLISIS FINAL DEL DESARROLLO Y ARMADO DE PROTOTIPO,
VIABILIDAD ECONÓMICO Y PROYECCIONES A FUTURO.
Este capítulo analizara los resultados finales del desarrollo del proyecto y expondrá
aspectos importante para considerar su posterior mejora e implementación dentro del área
de seguridad.
Evaluar las diferencias entre el prototipo y los controles de acceso ya existentes nos
permitirá ampliar el panorama de la tecnología que estamos utilizando. La tecnología RFID
está dentro de la clasificación de tarjetas inteligentes.
Además los lectores de tarjetas magnéticas en lugares húmedos, cerca de una playa
por ejemplo, son propensos a corroerse, esto obliga a cambiar los lectores constantemente
lo que es además de una desventaja es una pérdida de ingresos.
70
4.1.2 Teclados de contraseña
Los controles de accesos con teclados de contraseña son también muy utilizados no
solo en control de accesos, sino también en sistemas de alarmas y protección. La ventaja
más inmediata es su discreción con la información con la que permite el acceso, las
contraseñas son asignadas al personal autorizado y se puede cambiar cada determinado
tiempo.
Los botones de control de accesos son más que nada un indicador de acceso más
que un control de acceso.
En este sentido se debe tener un control minucioso de las características físicas que
permiten el acceso.
72
4.1.5 Análisis final.
Comparando todos estos elementos podemos ver que todos los sistemas por más
sofisticados que sean o novedosos presentaran inconvenientes. El proyecto al usar tarjetas
inteligentes es más segura que la tecnología e banda magnética, no se daña con la humedad
al estar protegido el circuito inductor por el recubrimiento que arma la tarjeta.
Comparándola con los botones de control podemos ver claramente que la diferencia
radica en la operación y la forma en la que se determinan los accesos, ya hemos mencionado
que los botones más que un control son un indicador de accesos.
No podemos comparar esta tecnología con la biometría como tal ya que trabajan en
diferentes campos de identificación, pero podemos decir que al igual que en la biometría al
ser del tipo de información más específica puede llegar a tener inconvenientes como la
obtención de le información que tenía en caso de extravío.
Con todos estos elementos podemos observar que aunque las opciones a la hora de
escoger son varias, todas estas presentaran ventajas y desventajas (en el caso del prototipo
veremos esto en un capitulo posterior), entonces se escoge la opción que más se ajuste a
las necesidades que buscamos satisfacer, por ejemplo, los controles de acceso de banda
magnético no son viables en un hotel en las orillas de una playa, entonces podemos sustituir
este elemento con tarjetas inteligentes, suponiendo que lo que se quiera utilizar son
tarjetas.
73
4.2 Viabilidad económica
Podemos decir que el prototipo es barato comparado con otras interfaces, pero los
costos siempre varían, no podemos generalizar todo el proyecto a un presupuesto fijo, en
el caso de él armado del prototipo podemos decir que fue barato, ya que fue montado en
gabinetes a distancias cortas y para un numero de accesos limitado, pero cuando
consideramos su instalación en un recinto se consideran más gastos.
Digamos que para instalar el prototipo será necesario ranurar, perforar o modificar
una estructura si no fue considerado el control de accesos desde un principio, entonces
además de la mano de obra de instalación es necesario considerar mano de obra que
modificara el recinto, con ello también van de la mano herramientas y materiales.
74
Fig. 4.2: Esquema de tubería para cableado.
Recuperado de:
http://2.bp.blogspot.com/_LO0sQrBgTnQ/TFnm8b5h6uI/AAAAAAAAADQ/2wEpXi419wk/s
1600/foto+plano+de+chircal.jpg. Consulta 6 Marzo 2015
Otro caso en particular son las tarjetas de acceso RFID, su precio es barato de fábrica,
pero la fábrica esta en Asia, entonces agregando impuestos y gastos de envió el precio se
triplica, entonces la tecnología es “barata” pero conseguirla es “caro”.
27
Norma UL 508 requisitos adicionales para el uso de materiales plásticos/poliméricos en borneros de
conexión y en el espaciado entre componentes eléctricos.
75
Este material es muy fácil de manipular, entonces ninguna norma te permitirá usar
este material en los elementos que protegen al control de accesos, por lo que es necesario
buscar un material resistente permitido para la instalación que además no interfiera con la
lectura de las tarjetas, con esto los gastos de materiales también incrementan.
Otra cosa indispensable es que elemento está permitiendo el acceso, una cerradura
electromagnética, un torniquete, una pluma. Todos estos elementos de acceso tienen un
costo que mientras más sofisticado o nuevo sea el precio es mayor.
Con todas estas consideraciones ya podemos darnos cuenta de que el gasto final del
prototipo funcionando en un recinto no puede ser estimado tan fácilmente.
Entonces es necesaria una investigación del caso específico del área o recinto donde
se instalara el control de accesos.
76
4.3 Mantenimiento del prototipo
Pero, dependiendo de los elementos a los que se ajusta al sistema como los que
mencionamos en el subtema anterior serán necesarias más medidas de mantenimiento,
limpieza y seguridad28. Por ejemplo si el prototipo se adapta a algún tipo de sensor, en los
sensores de presencia en ocasiones insectos se llegan a introducir en el gabinete, entonces
el insecto al moverse en su interior activa el sensor generando falsas alarmas, por lo que es
necesario la revisión y limpieza periódica del sensor.
28
Real Decreto: RD 485/1997. Anexo I, punto 4. España. 2001
29
Real Decreto: RD 1215/1997. Artículo 3, apartado 5. España. 2001
77
Fig. 4.3: Revisión y mantenimiento de una cámara para exteriores.
78
Con esto logrado lo siguiente seria aumentar la cantidad de elementos con los que
puede trabajar el sistema, la base principal es el acceso por RFID con un adicional de un
segundo control de accesos por Bluetooth, pero se debe de expandir estas condiciones,
quizá se busque colocar un sistema de biometría para el segundo control de accesos o que
el accesos por RFID este aquí en vez de en el primer control, etc.
Con la invención de nuevos elementos más sofisticado que permiten los accesos y
regulan los accesos es necesaria la constante mejora del prototipo con los módulos de
control e identificación.
La base de datos también tiene que modificarse según las necesidades del sistema,
de momento solo muestra la hora de acceso, la identidad del usuario y si llego a tiempo,
con retraso o se le denegó el acceso, pero los campos de la base de datos también varían
dependiendo del acceso que está permitiendo, quizá sea necesario conocer la fecha en la
ingreso, la cantidad de veces que ingreso, si hay irregularidad en el uso de la tarjeta, si
intento acceder a un área restringida sin permiso, etc.
Para concluir entonces las posibilidades a futuro son basten y en diferentes áreas,
sean administrativas o de desarrollo e implementación. El límite será hasta que la idea
pierda el enfoque de innovación, siempre es necesario mejorar lo ya existente y usarlo de
base para el desarrollo de nuevas tecnologías.
79
Conclusiones
Con el desarrollo del prototipo hemos observado que es necesario determinar desde
un principio que es lo que deseamos obtener y en base a esto determinamos que podemos
hacer y como lo podemos hacer.
Adentrarse más en las características que deseas que tenga el proyecto en desarrollo
también abre una puerta que muestra los conocimientos que rodea o debe de rodear el
prototipo, normas, especificaciones, bajo qué condiciones funcionara y bajo cuáles no. Con
esto podemos decir que un estudio no puede ser únicamente enfocado a un área en
específico, digamos electrónica, es necesario aprender un poco sobre todo y siempre estar
en constante renovación.
En este proyecto de tesis propusimos un prototipo funcional que usa tecnología RFID
y Bluetooth debido a que no ha sido usada como tal en el área de controles de accesos,
pero siempre habrá proyectos de desarrollo para nuevas tecnologías que se pueden aplicar
a diferentes sectores académicos o industriales.
80
GLOSARIO
Solenoide: Bobina formada por un alambre enrollado en espiral sobre una armazón
cilíndrica, que se emplea en diversos aparatos eléctricos, y que crea un campo magnético
cuando circula una corriente continua por su interior
81
Software: Se conoce como software al equipamiento lógico o soporte lógico de un sistema
informático, que comprende el conjunto de los componentes lógicos necesarios que hacen
posible la realización de tareas específicas, en contraposición a los componentes físicos que
son llamados hardware.
Activo: Un activo es un bien tangible o intangible que posee una empresa o persona
natural.
82
ABREVIATURAS
USB: Bus Universal en Serie (BUS), (siglas del inglés Universal Serial Bus)
TX: Transmisión
RX: Recepción.
83
VCD: Voltaje de Corriente Directa.
ID: Identificación
84
Bibliografías
[5] Reyes. Evolución delas bases de datos [Blog]. [Consulta: 12 Febrero 2015]. Disponible
en: http://evolucion-bd.blogspot.mx/
[6] Edgar Frank Codd: fue un científico informático Ingles, conocido por sus aportes a la
teoría de bases de datos relacionales.
[9] Oracle: Es el segundo mayor fabricante de software por ingresos, después de Microsoft
[10] World Wide Web: Red informática Mundial o comúnmente conocida como la Web.
85
[13] Luis Cosentino. Control de accesos. Esquema, historia y esquema básico, Nro.
45(2009). P. 160. Versión digital disponible en el sitio: http://www.rnds.com.ar/
[15] Marco Antonio Cruz Chávez. Conceptos básicos de base de datos. [Consulta 6 de
Marzo 2014]. Disponible en:
http://www.gridmorelos.uaem.mx/~mcruz//cursos/miic/bd1.pdf
86
[26] Hojas de especificaciones de la serie KA78XX/KA78XXA de FAIRCHIL Semiconductors.
Disponibles en versión digital en:
https://www.fairchildsemi.com/datasheets/lm/LM7805.pdf
87
ANEXO
Fig. A1: Programa completo para el acceso a la primera cerradura. Imagen recuperada
del compilador Arduino UNO. Marzo 2015
Fig. A1.1: Programa completo para el acceso a la primera cerradura. Imagen recuperada
del compilador Arduino UNO. Marzo 2015
Fig. A1.2: Programa completo para el acceso a la primera cerradura. Imagen recuperada
del compilador Arduino UNO. Marzo 2015
Fig. A1.3: Programa completo para el acceso a la primera cerradura. Imagen recuperada
del compilador Arduino UNO. Marzo 2015
Fig. A1.4: Programa completo para el acceso a la primera cerradura. Imagen recuperada
del compilador Arduino UNO. Marzo 2015
Programa VBA para Excel
Fig. A2: Programa completo para el acceso a la primera cerradura. Imagen recuperada
del compilador VBA para Excel. Marzo 2015
Fig. A2.1: Programa completo para el acceso a la primera cerradura. Imagen recuperada
del compilador VBA para Excel. Marzo 2015
Fig. A2.3: Programa completo para el acceso a la primera cerradura. Imagen recuperada
del compilador VBA para Excel. Marzo 2015
DATASHEET
BLUETOOTH TO SERIAL PORT
MODULE
HC05
Overview
HC‐05 module is an easy to use Bluetooth SPP (Serial Port Protocol) module,
designed for transparent wireless serial connection setup.
Serial port Bluetooth module is fully qualified Bluetooth V2.0+EDR (Enhanced
Data Rate) 3Mbps Modulation with complete 2.4GHz radio transceiver and
baseband. It uses CSR Bluecore 04‐External single chip Bluetooth system with
CMOS technology and with AFH (Adaptive Frequency Hopping Feature). It
has the
footprint as small as 12.7mmx27mm. Hope it will simplify your overall
design/development cycle.
www.electronica60norte.com
electronica60norte@hotmail.com
Software features
Slave default Baud rate: 9600, Data bits:8, Stop bit:1,Parity:No parity.
PIO9 and PIO8 can be connected to red and blue led separately. When
master and slave are paired, red and blue led blinks 1time/2s in interval,
while disconnected only blue led blinks 2times/s.
Auto‐connect to the last device on power as default.
Permit pairing device to connect as default.
Auto‐pairing PINCODE:”1234” as default.
Auto‐reconnect in 30 min when disconnected as a result of beyond the
range of connection.
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electronica60norte@hotmail.com
www.electronica60norte.com
electronica60norte@hotmail.com
BLUE LED = ACTIVE (Blinking 500ms period inactive connection, change 1seg
with active connection)
Open a serial terminal and select the serial COM x port number that assigned
Windows to Bluetooth Module.
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electronica60norte@hotmail.com
AT COMMANDS
How to get to AT COMMAND mode
1: Connect KEY pin to VCC.
2: Supply power to module. Then the module will enter into AT MODE. In this
mode you have to use baud rate at 38400. In this way, user should change
the baud rate for SLAVE AND MASTER mode.
How to set this module as “Master‐Host” role
1: Input high level to KEY.
2: Supply power to the module. And the module will enter to AT COMMAND.
3: Set the parameters of the hyper terminal or the other serial tools (baud
rate: 38400, data bit:8, stop bit:1, no parity bit, no Flow Control).
4: Sent the characters “AT+ROLE=1\r\n” through serial, then receive the
characters “OK\r\n”. Here, “\r\n” is the CRLF.
5: Sent the characters “AT+CMODE=1\r\n” through serial, then receive the
characters “OK\r\n”. Here, “\r\n” is the CRLF.
6: Default factory password passkey is: 1243, this must be the same in the
Bluetooth slave module if you want to pair it.
To read passkey use this command: “AT+PSWD?”.
To Reset the password command sent the characters “AT+PSWD=XXXX”.
The password must be 4‐bits.
Features
• Diffused Junction
• High Current Capability and Low Forward Voltage Drop
• Surge Overload Rating to 30A Peak
• Low Reverse Leakage Current
• Lead Free Finish, RoHS Compliant (Note 3)
Mechanical Data
• Case: DO-41
• Case Material: Molded Plastic. UL Flammability Classification
DO-41 Plastic
Rating 94V-0 Dim
Min Max
• Moisture Sensitivity: Level 1 per J-STD-020D
A 25.40 ⎯
• Terminals: Finish - Bright Tin. Plated Leads Solderable per
B 4.06 5.21
MIL-STD-202, Method 208
C 0.71 0.864
• Polarity: Cathode Band
D 2.00 2.72
• Mounting Position: Any
All Dimensions in mm
• Ordering Information: See Page 2
• Marking: Type Number
• Weight: 0.30 grams (approximate)
Maximum Ratings and Electrical Characteristics @TA = 25°C unless otherwise specified
Single phase, half wave, 60Hz, resistive or inductive load.
For capacitive load, derate current by 20%.
Characteristic Symbol 1N4001 1N4002 1N4003 1N4004 1N4005 1N4006 1N4007 Unit
Peak Repetitive Reverse Voltage VRRM
Working Peak Reverse Voltage VRWM 50 100 200 400 600 800 1000 V
DC Blocking Voltage VR
RMS Reverse Voltage VR(RMS) 35 70 140 280 420 560 700 V
Average Rectified Output Current (Note 1) @ TA = 75°C IO 1.0 A
Non-Repetitive Peak Forward Surge Current 8.3ms
IFSM 30 A
single half sine-wave superimposed on rated load
Forward Voltage @ IF = 1.0A VFM 1.0 V
Peak Reverse Current @TA = 25°C 5.0
IRM μA
at Rated DC Blocking Voltage @ TA = 100°C 50
Typical Junction Capacitance (Note 2) Cj 15 8 pF
Typical Thermal Resistance Junction to Ambient RθJA 100 K/W
Maximum DC Blocking Voltage Temperature TA +150 °C
Operating and Storage Temperature Range TJ, TSTG -65 to +150 °C
Notes: 1. Leads maintained at ambient temperature at a distance of 9.5mm from the case.
2. Measured at 1.0 MHz and applied reverse voltage of 4.0V DC.
3. EU Directive 2002/95/EC (RoHS). All applicable RoHS exemptions applied, see EU Directive 2002/95/EC Annex Notes.
0.8
1.0
0.6
0.4
0.1
0.2
Tj, = 25oC
Pulse Width = 300 μs
2% Duty Cycle
0 0.01
40 60 80 100 120 140 160 180 0.6 0.8 1.0 1.2 1.4 1.6
f = 1MHz
40
Cj, CAPACITANCE (pF)
30
1N4001 - 1N4004
10
20
1N4005 - 1N4007
10
0 1.0
1.0 10 100 1.0 10 100
Order Code
LED008 16 x 2 Alphanumeric Display
FRM010 Serial LCD Firmware (optional)
Contents
1 x 16x2 Alphanumeric Display
1 x data booklet
Introduction
Alphanumeric displays are used in a wide range of applications, including palmtop
computers, word processors, photocopiers, point of sale terminals, medical
instruments, cellular phones, etc. The 16 x 2 intelligent alphanumeric dot matrix
display is capable of displaying 224 different characters and symbols. A full list of
the characters and symbols is printed on pages 7/8 (note these symbols can vary
between brand of LCD used). This booklet provides all the technical specifications
for connecting the unit, which requires a single power supply (+5V).
Further Information
Available as an optional extra is the Serial LCD Firmware, which allows serial
control of the display. This option provides much easier connection and use of the
LCD module. The firmware enables microcontrollers (and microcontroller based
systems such as the PICAXE) to visually output user instructions or readings onto
an LCD module. All LCD commands are transmitted serially via a single
microcontroller pin. The firmware can also be connected to the serial
port of a computer.
serout 7,T2400,(“Hello”)
Electrical Characteristics
Timing Characteristics
Timing Chart
Instructions
OUTPUT
COMMON
COMMON OUTPUT
INPUT
COMMON
KCS (TO-220) PACKAGE INPUT
(TOP VIEW)
COMMON
OUTPUT
COMMON
INPUT
description/ordering information
This series of fixed-voltage integrated-circuit voltage regulators is designed for a wide range of applications.
These applications include on-card regulation for elimination of noise and distribution problems associated with
single-point regulation. Each of these regulators can deliver up to 1.5 A of output current. The internal
current-limiting and thermal-shutdown features of these regulators essentially make them immune to overload.
In addition to use as fixed-voltage regulators, these devices can be used with external components to obtain
adjustable output voltages and currents, and also can be used as the power-pass element in precision
regulators.
ORDERING INFORMATION
VO(NOM) ORDERABLE TOP-SIDE
TJ PACKAGE†
(V) PART NUMBER MARKING
POWER-FLEX (KTE) Reel of 2000 µA7805CKTER µA7805C
5 TO-220 (KC) Tube of 50 µA7805CKC
µA7805C
TO-220, short shoulder (KCS) Tube of 20 µA7805CKCS
POWER-FLEX (KTE) Reel of 2000 µA7808CKTER µA7808C
8 TO-220 (KC) Tube of 50 µA7808CKC
µA7808C
TO-220, short shoulder (KCS) Tube of 20 µA7808CKCS
POWER-FLEX (KTE) Reel of 2000 µA7810CKTER µA7810C
10
TO-220 (KC) Tube of 50 µA7810CKC µA7810C
0°C to 125°C
POWER-FLEX (KTE) Reel of 2000 µA7812CKTER µA7812C
12 TO-220 (KC) Tube of 50 µA7812CKC
µA7812C
TO-220, short shoulder (KCS) Tube of 20 µA7812CKCS
POWER-FLEX (KTE) Reel of 2000 µA7815CKTER µA7815C
15 TO-220 (KC) Tube of 50 µA7815CKC
µA7815C
TO-220, short shoulder (KCS) Tube of 20 µA7815CKCS
POWER-FLEX (KTE) Reel of 2000 µA7824CKTER µA7824C
24
TO-220 (KC) µA7824C
Tube of 50 µA7824CKC
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright 2003, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
schematic
INPUT
OUTPUT
COMMON
absolute maximum ratings over virtual junction temperature range (unless otherwise noted)†
Input voltage, VI: µA7824C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 V
All others . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 V
Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
APPLICATION INFORMATION
+V µA78xx +VO
0.33 µF 0.1 µF
IN OUT
+ µA78xx G
VI IL
COM
– –VO
R1
IO
0.33 µF 0.1 µF
R2
VO +V )
xx ǒ )Ǔ
NOTE A: The following formula is used when Vxx is the nominal output voltage (output to common) of the fixed regulator:
V xx
R1
I Q R2
Input µA78xx
R1
0.33 µF VO(Reg)
Output
IO
IO = (VO/R1) + IO Bias Current
APPLICATION INFORMATION
1N4001
2 µF 1 µF 0.1 µF
1N4001
–20-V Input µA7915C VO = –15 V
1N4001
–VO
reverse-bias protection
Occasionally, the input voltage to the regulator can collapse faster than the output voltage. This can occur, for
example, when the input supply is crowbarred during an output overvoltage condition. If the output voltage is
greater than approximately 7 V, the emitter-base junction of the series-pass element (internal or external) could
break down and be damaged. To prevent this, a diode shunt can be used as shown in Figure 7.
VI µA78xx +VO
Thermal Tab
(See Note C)
0.360 (9,14)
0.295 (7,49)
0.350 (8,89)
NOM
0.320 (8,13)
0.420 (10,67)
0.310 (7,87)
0.410 (10,41)
1 3
0.025 (0,63)
Seating Plane
0.031 (0,79)
0.004 (0,10)
0.100 (2,54) 0.010 (0,25) M
0.005 (0,13)
0.200 (5,08)
0.001 (0,03)
0.041 (1,04)
0.010 (0,25) 0.031 (0,79)
NOM
Gage Plane
3°– 6°
0.010 (0,25)
4073375/F 12/00
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
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11/2“
(37.5mm)
WARRANTY: This SECO-LARM product is warranted against defects in material and workmanship while used in normal service SD-997A-DQ
for a period of one (1) year from the date of sale to the original consumer customer. SECO-LARM’s obligation is limited to the repair
or replacement of any defective part if the unit is returned, transportation prepaid, to SECO-LARM.
This Warranty is void if damage is caused by or attributed to acts of God, physical or electrical misuse or abuse, neglect, repair, or 63/8“ (162mm)
alteration, improper or abnormal usage, or faulty installation, or if for any other reason SECO-LARM determines that such equipment
is not operating properly as a result of causes other than defects in material and workmanship.
The sole obligation of SECO-LARM, and the purchaser’s exclusive remedy, shall be limited to replacement or repair only, at SECO-LARM’s
option. In no event shall SECO-LARM be liable for any special, collateral, incidental, or consequential personal or property damages of any
kind to the purchaser or anyone else.
NOTICE: The information and specifications printed in this manual are current at the time of publication. However, the SD-997B series
SECO-LARM policy is one of continual development and improvement. For this reason, SECO-LARM reserves the right to change
specifications without notice. SECO-LARM is also not responsible for misprints or typographical errors. Dimensions:*
Copyright © 2013 SECO-LARM U.S.A., Inc. All rights reserved. This material may not be reproduced or copied, in whole or in part, *Note: Original measurements
without the written permission of SECO-LARM. taken in millimeters. Inches are
closest 1/16” approximation.
PITSW2
SECO-LARM® U.S.A., Inc. MiSD997x-xxQ_032814.pmd
16842 Millikan Avenue, Irvine, CA 92606 Website: www.seco-larm.com
Tel: 800-662-0800 / 949-261-2999 Fax: 949-261-7326 E-mail: sales@seco-larm.com
Page 4 SECO-LARM U.S.A., Inc. Note: Products with model numbers that end with "Q" or that have a round green"Q"sticker are RoHS compliant. Page 1
Electric Deadbolt Installation Manual Electric Deadbolt Installation Manual
Fig. 2 - Parts List: SD-997A-DQ Also Includes:
door is closed but the deadbolt remains unlock. 6 . For SD-997A-DQ only (see figs. 5 and 6)
During this time the lock body may attempt multiple Because the SD-997A-DQ offers fail-secure operation, the door
Lock body x 1 Manual times to relock the door and if it fails, it will stop to locks if power to the unit is cut. For such a situation, a separate
prevent the solenoid from burning out. manual lock/unlock cylinder is provided for manual operation.
lock/unlock A. Insert the cylinder as shown in Fig. 5, and secure it to the
However if the lock body and the strike plate are too far
cylinder x 1
or apart, the lock body will not attempt to lock the door and the lock body with the provided long screw. Turning the key or
the manual knob will unlock the SD-997A-DQ manually.
SD-997BQ/ Faceplate x 1 deadbolt will not throw out.
SD-997A-DQ SD-997B-GBQ Oval cylinder IMPORTANT – The lock body and strike plate must be B. Two separate templates are included for drilling holes in the
plate x 2 properly aligned and next to each other in order for the door frame for the key and manual knob.
Mounting tabs product to function properly. C. A separate 3-pin connector for the SD-997A-DQ can be
6-Pin
Strike (large) x 2 connector x 1 Keys x 3 G. Pull the vinyl covering off the faceplate, and place the connected to an alarm panel or annunciator to alert when
Plate x 1 faceplate over the face of the lock body. Use screws to the door is locked or unlocked.
Mounting tabs
• Templates x 4 3-Pin fix the faceplate and lock body to the mounting tabs.
(small) x 2
• Mounting screws connector x 1 Fig. 4 - Door and Frame Cuts Fig. 7 - Wiring Push
Card reader button
N.C. COM or keypad
Door frame
Installation Fig. 3 - Aligning Max. 50mm N.O.
1. Determine where the deadbolt will be mounted (see fig. 1). Door
2. Tape the templates to the door frame and door (see fig. 3) SD-997A-DQ/SD-997B series
A. Align the templates so that the deadbolt of the lock body template Lock body template See fig. 8
is centered on the deadbolt hole of the strike plate template. SD-997A-DQ Orange
B. Make sure to leave enough room at the ends of the lock body only* Brown wire Power
and strike plate templates for mounting the mounting tabs. Red wire Supply
3. Door frame cut (see fig. 4)
A. Cut out the space for the lock body.
B. Test the fit. The lock body should fit snugly inside the space. Strike plate template Green wire - door monitor, COM
C. Drill two 5mm screw holes as shown on the template. Yellow wire - door monitor, N.C. (active when door closed)
Blue wire - door monitor, N.O. (active when door open)
4 . Door cut and mount. (see fig. 4) Purple wire - active if door is locked (N.C.) For
{
A. For wood doors: *See separate Gray wire - manual lock/unlock (COM) SD-997A-DQ
1) Use a chisel to knock out a 3mm (1/8-inch) deep space as template. only
Black wire - active if door is unlocked (N.O.)
shown on the template.
2) Drill the magnet hole, 12mm (1/2”) wide by 6mm (1/4”) deep. IMPORTANT – Do not cut wires before the plug as warranty
3) Use four wood screws to mount the strike plate in the Fig. 5 - Manual Lock/Unlock Cylinder will be voided.
chiseled space. The magnet should fit in the magnet hole.
4) Use a drill to drill out the deadbolt hole to a depth of 16mm (5/8”).
(SD-997A-DQ only): Fig. 8 - Setting Door Lock Delay Timer
Note: If cylinder is used,
B. For hollow metal doors:
max. depth of door SD-997A-DQ
1) Cut out the space for the strike plate.
frame is 50mm.
2) Drill two screw holes for each of the two mounting tabs.
3) Use screws to fix the mounting tabs inside the hollow metal door.
4) Use screws to fix the strike plate to the mounting tabs. Line up these marks
Screw to secure
cylinder to lock body SD-997BQ /
5. Door jamb cut and mount (see fig. 4) IMPORTANT – Push all the wires into the door frame. If SD-997B-GBQ
A. Cut out the space for the face of the lock body. space is a problem, cut away part of the dust catcher inside
B. Drill one 5mm hole for each of the two mounting tabs. the frame, or carefully chip away part of the drywall, being Fig. 6 - Installation of Manual Lock/Unlock Cylinder (SD-997A-DQ only):
C. Use screws to fix the mounting tabs inside the door jamb. careful not to damage the wall. Installation at side of door Installation at top of door
D. SD-997A-DQ only: Insert the lock/unlock cylinder (see fig. 5). F. Set the door lock delay timer (see fig. 8). This is the
E. Connect the wires, and insulate them (see fig. 7): time it takes the deadbolt to automatically lock after
1) Red – Power input (+) the door is closed.
2) Brown – Power input (-) NOTE: For SD-997A-DQ & SD-997B-GBQ only – The Drill hole
3) Orange – Control wire (ground to release bolt) for lock Drill hole
deadbolt automatically relocks 4 seconds after an Drill hole for lock Drill hole for lock
*{
for lock
4) Green – Door monitor, COM optional external push button (egress button) is
5) Yellow – Door monitor, N.C. (active when door closed) pressed, if the door was not opened.
6) Blue – Door monitor, N.O. (active when door open) The lock body has a sensor mechanism
IMPORTANT – Correct polarity of the red and brown wires is wherein it can detect if the strike plate is in
critical. Incorrect polarity will burn out the solenoid ! close proximity (such as when the door is
closed). If the door was closed but somehow
*Connect to an alarm control panel or warning device to show if the strike plate was not aligned properly, the
the door is open or closed. door monitor indicator may indicate that the
Page 2 SECO-LARM U.S.A., Inc. SECO-LARM U.S.A., Inc. Page 3
CFA0207
Vishay Draloric
Carbon Film Resistors, Standard
FEATURES
• Conformal lacquer coating
• Stable film structure
• Low performance and low cost applications
• General purpose commodity products
• Compatible with automatic insertion equipment
MODEL SIZE POWER RATING LIMITING ELEMENT TEMPERATURE TOLERANCE RESISTANCE E-SERIES
P70°C VOLTAGE MAX COEFFICIENT RANGE
W V쓖 ppm/K % Ω
CFA0207 0207 0.33 250 + 350/- 1500 5 1R0 - 10M 24
TECHNICAL SPECIFICATIONS
PARAMETER UNIT CFA0207
Rated Dissipation at 70°C W 0.33
Limiting Element Voltage 1) V쓖 ≤ 250
Insulation voltage (1 min) Veff > 500
Thermal Resistance K/W ≤ 257
Insulation Resistance Ω ≥ 109
Category Temperature Range °C - 55/+ 155
Terminal Strength, axial N > 25
-9
Failure Rate 10 /h < 10
Weight g 0.21
1)Rated voltage: PxR
PACKAGING
MODEL REEL 2) MIN. ORDER QTY BOX MIN. ORDER QTY
PIECES/REEL CODE PACKAGING UNITS PIECES/BOX CODE PACKAGING UNITS
CFA0207 5000 R5 1 5000 A5 1
2)On special request only
ORDERING INFORMATION
CFA0207 1K8 ± 5% A5
MODEL RESISTANCE VALUE TOLERANCE PACKAGING
Ω % A5-Ammopack 5000 pcs
100
100 80
60
50 40
20
0 0
0 0.2 0.4 0.6 0.8 -55 -25 0 25 50 75 100 125 155
70
TEMPERATURE RISE Power (W) DERATING Ambient Temperature (°C)
PERFORMANCE
TEST CONDITIONS OF TEST REQUIREMENTS 1)
Endurance Test at 70°C 1000 hours at 70°C, 1.5 hours “ON”, 0.5 hours “OFF” ≤ ± 3.0%
IEC 60115-1 4.25.1
Endurance at UCT 1000 hours at 155°C without load ≤ ± 3.0%
IEC 60115-1 4.25.3
Overload Test Short time overload 5s ≤ ± 0.75%
IEC 60115-1 4.13 at 2.5 x rated voltage or ≤ twice the limiting element voltage
Thermal Shock Rapid change between upper and lower category temperature ≤ ± 0.5%
IEC 60115-1 4.19, IEC 60068-2-14
Climatic Sequence Dry heat, damp heat cyclic, cold, low air pressure ≤ ± 1.5%
IEC 60115-1 4.23
Damp Heat Steady State 56 days at 40°C and 93% relative humidity ≤ ± 3.0%
IEC 60115-1 4.24, IEC 60068-2-3
Resistance to Soldering Heat 10 seconds at 260°C solder bath temperature ≤ ± 1.0%
IEC 60115-1 4.18, IEC 60068-2-20
Robustness of Terminations Tensile, bending and torsion ≤ ± 0.25%
IEC 60115-1 4.16
Vibration 0.75mm or 10g, 10Hz - 500Hz 6 hours ≤ ± 0.25%
IEC 60115-1 4.22
1)
For ohmic values between 10R and 1M
APPLICABLE SPECIFICATIONS
CECC40000/40100/EN 140000/IEC 60115-1
www.datasheetcatalog.com
1. Introduction
This document describes the functionality and electrical specifications of the contactless
reader/writer MFRC522.
Remark: The MFRC522 supports all variants of the MIFARE Mini, MIFARE 1K,
MIFARE 4K, MIFARE Ultralight, MIFARE DESFire EV1 and MIFARE Plus RF
identification protocols. To aid readability throughout this data sheet, the MIFARE Mini,
MIFARE 1K, MIFARE 4K, MIFARE Ultralight, MIFARE DESFire EV1 and MIFARE Plus
products and protocols have the generic name MIFARE.
2. General description
The MFRC522 is a highly integrated reader/writer IC for contactless communication
at 13.56 MHz. The MFRC522 reader supports ISO/IEC 14443 A/MIFARE mode.
The MFRC522 supports MF1xxS20, MF1xxS70 and MF1xxS50 products. The MFRC522
supports contactless communication and uses MIFARE higher transfer speeds up to
848 kBd in both directions.
MFRC522 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
[1] Supply voltages below 3 V reduce the performance in, for example, the achievable operating distance.
[2] VDDA, VDDD and VDD(TVDD) must always be the same voltage.
[3] VDD(PVDD) must always be the same or lower voltage than VDDD.
[4] Ipd is the total current for all supplies.
[5] IDD(PVDD) depends on the overall load at the digital pins.
[6] IDD(TVDD) depends on VDD(TVDD) and the external circuit connected to pins TX1 and TX2.
[7] During typical circuit operation, the overall current is below 100 mA.
[8] Typical value using a complementary driver configuration and an antenna matched to 40 between pins TX1 and TX2 at 13.56 MHz.
5. Ordering information
Table 2. Ordering information
Type number Package
Name Description Version
MFRC52201HN1/TRAYB[1] HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; SOT617-1
32 terminal; body 5 5 0.85 mm
MFRC52201HN1/TRAYBM[2] HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; SOT617-1
32 terminal; body 5 5 0.85 mm
MFRC52202HN1/TRAYB[1] HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; SOT617-1
32 terminal; body 5 5 0.85 mm
MFRC52202HN1/TRAYBM[2] HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; SOT617-1
32 terminal; body 5 5 0.85 mm
MFRC522 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
6. Block diagram
The analog interface handles the modulation and demodulation of the analog signals.
The contactless UART manages the protocol requirements for the communication
protocols in cooperation with the host. The FIFO buffer ensures fast and convenient data
transfer to and from the host and the contactless UART and vice versa.
REGISTER BANK
ANALOG CONTACTLESS
ANTENNA FIFO
INTERFACE UART SERIAL UART
BUFFER
SPI HOST
I2C-BUS
001aaj627
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D6/ADR_0/
D2/ADR_4 D4/ADR_2 MOSI/MX
D5/ADR_1/ D7/SCL/
SDA/NSS/RX EA I2C D1/ADR_5 D3/ADR_3 SCK/DTRQ MISO/TX PVDD PVSS
24 32 1 25 26 27 28 29 30 31 2 5
3
DVDD
VOLTAGE 4
MONITOR DVSS
SPI, UART, I2C-BUS INTERFACE CONTROL AND
15
POWER ON AVDD
DETECT 18
AVSS
FIFO CONTROL
STATE MACHINE
64-BYTE FIFO RESET
COMMAND REGISTER
BUFFER CONTROL
CRC16
MIFARE CLASSIC UNIT
GENERATION AND CHECK
BIT COUNTER
7
MFIN
8
SERIAL DATA SWITCH MFOUT
9
SVDD
21
CLOCK OSCIN
AMPLITUDE GENERATION,
OSCILLATOR
RATING FILTERING AND 22
ANALOG TO DIGITAL
DISTRIBUTION OSCOUT
CONVERTER
REFERENCE
VOLTAGE
Q-CLOCK TEMPERATURE
GENERATION SENSOR
ANALOG TEST
MULTIPLEXOR I-CHANNEL Q-CHANNEL
AND AMPLIFIER AMPLIFIER
TRANSMITTER CONTROL
DIGITAL TO
I-CHANNEL Q-CHANNEL
ANALOG
DEMODULATOR DEMODULATOR
CONVERTER
16 19 20 17 10, 14 11 13 12
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7. Pinning information
29 D5/ADR_1/SCK/DTRQ
30 D6/ADR_0/MOSI/MX
31 D7/SCL/MISO/TX
28 D4/ADR_2
27 D3/ADR_3
26 D2/ADR_4
25 D1/ADR_5
32 EA
I2C 1 24 SDA/NSS/RX
PVDD 2 23 IRQ
DVDD 3 22 OSCOUT
DVSS 4 21 OSCIN
MFRC522
PVSS 5 20 AUX2
NRSTPD 6 19 AUX1
MFIN 7 18 AVSS
MFOUT 8 17 RX
TVSS 10
TX1 11
TVDD 12
TX2 13
TVSS 14
AVDD 15
VMID 16
9
SVDD
001aaj819
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[1] Pin types: I = Input, O = Output, I/O = Input/Output, P = Power and G = Ground.
[2] The pin functionality of these pins is explained in Section 8.1 “Digital interfaces”.
[3] Connection of heatsink pad on package bottom side is not necessary. Optional connection to pin DVSS is possible.
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8. Functional description
The MFRC522 transmission module supports the Read/Write mode for
ISO/IEC 14443 A/MIFARE using various transfer speeds and modulation protocols.
BATTERY
MFRC522 ISO/IEC 14443 A CARD
MICROCONTROLLER
contactless card
reader/writer 001aak583
(1)
ISO/IEC 14443 A
READER ISO/IEC 14443 A CARD
(2)
MFRC522
001aak584
(1) Reader to card 100 % ASK, Miller encoded, transfer speed 106 kBd to 848 kBd.
(2) Card to reader subcarrier load modulation, Manchester encoded or BPSK, transfer speed 106 kBd
to 848 kBd.
Fig 5. ISO/IEC 14443 A/MIFARE Read/Write mode communication diagram
The MFRC522’s contactless UART and dedicated external host must manage the
complete ISO/IEC 14443 A/MIFARE protocol. Figure 6 shows the data coding and
framing according to ISO/IEC 14443 A/MIFARE.
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ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd even
start parity
The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A
part 3 and handles parity generation internally according to the transfer speed. Automatic
parity generation can be switched off using the MfRxReg register’s ParityDisable bit.
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An interface compatible with SPI enables high-speed serial communication between the
MFRC522 and a microcontroller. The implemented interface is in accordance with the SPI
standard.
MFRC522
SCK
SCK
MOSI
MOSI
MISO
MISO
NSS
NSS
001aak586
The MFRC522 acts as a slave during SPI communication. The SPI clock signal SCK must
be generated by the master. Data communication from the master to the slave uses the
MOSI line. The MISO line is used to send data from the MFRC522 to the master.
Data bytes on both MOSI and MISO lines are sent with the MSB first. Data on both MOSI
and MISO lines must be stable on the rising edge of the clock and can be changed on the
falling edge. Data is provided by the MFRC522 on the falling clock edge and is stable
during the rising clock edge.
The first byte sent defines both the mode and the address.
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The first send byte defines both the mode and the address byte.
The MSB of the first byte defines the mode used. To read data from the MFRC522 the
MSB is set to logic 1. To write data to the MFRC522 the MSB must be set to logic 0. Bits 6
to 1 define the address and the LSB is set to logic 0.
MFRC522
RX
RX
TX
TX
DTRQ
DTRQ
MX
MX
001aak587
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The default transfer speed is 9.6 kBd. To change the transfer speed, the host controller
must write a value for the new transfer speed to the SerialSpeedReg register. Bits
BR_T0[2:0] and BR_T1[4:0] define the factors for setting the transfer speed in the
SerialSpeedReg register.
The BR_T0[2:0] and BR_T1[4:0] settings are described in Table 9. Examples of different
transfer speeds and the relevant register settings are given in Table 10.
[1] The resulting transfer speed error is less than 1.5 % for all described transfer speeds.
The selectable transfer speeds shown in Table 10 are calculated according to the
following equations:
If BR_T0[2:0] = 0:
6
27.12 10
transfer speed = -------------------------------
- (1)
BR_T0 + 1
If BR_T0[2:0] > 0:
27.12 10 6
transfer speed = ----------------------------------- (2)
----------------------------------
BR_T1 + 33
-
2 BR_T0 – 1
Remark: The LSB for data and address bytes must be sent first. No parity bit is used
during transmission.
Read data: To read data using the UART interface, the flow shown in Table 12 must be
used. The first byte sent defines both the mode and the address.
ADDRESS
RX
SA A0 A1 A2 A3 A4 A5 (1) R/W SO
DATA
TX
SA D0 D1 D2 D3 D4 D5 D6 D7 SO
MX
DTRQ
001aak588
(1) Reserved.
Fig 9. UART read data timing diagram
Write data: To write data to the MFRC522 using the UART interface, the structure shown
in Table 13 must be used.
The first byte sent defines both the mode and the address.
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NXP Semiconductors
ADDRESS DATA
RX
SA A0 A1 A2 A3 A4 A5 (1) R/W SO SA D0 D1 D2 D3 D4 D5 D6 D7 SO
ADDRESS
TX
SA A0 A1 A2 A3 A4 A5 (1) R/W SO
All information provided in this document is subject to legal disclaimers.
Rev. 3.8 — 17 September 2014
MX
DTRQ
112138
001aak589
(1) Reserved.
Fig 10. UART write data timing diagram
Remark: The data byte can be sent directly after the address byte on pin RX.
The MSB of the first byte sets the mode used. To read data from the MFRC522, the MSB is set to logic 1. To write data to the
MFRC522 the MSB is set to logic 0. Bit 6 is reserved for future use, and bits 5 to 0 define the address; see Table 14.
© NXP Semiconductors N.V. 2014. All rights reserved.
MFRC522
15 of 95
NXP Semiconductors MFRC522
Standard 3V MIFARE reader solution
SDA
SCL
MICROCONTROLLER
I2C
CONFIGURATION
EA
WIRING
ADR_[5:0]
001aak590
The MFRC522 can act either as a slave receiver or slave transmitter in Standard mode,
Fast mode and High-speed mode.
SDA is a bidirectional line connected to a positive supply voltage using a current source or
a pull-up resistor. Both SDA and SCL lines are set HIGH when data is not transmitted. The
MFRC522 has a 3-state output stage to perform the wired-AND function. Data on the
I2C-bus can be transferred at data rates of up to 100 kBd in Standard mode, up to
400 kBd in Fast mode or up to 3.4 Mbit/s in High-speed mode.
If the I2C-bus interface is selected, spike suppression is activated on lines SCL and SDA
as defined in the I2C-bus interface specification.
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SDA
SCL
• A START condition is defined with a HIGH-to-LOW transition on the SDA line while
SCL is HIGH.
• A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while
SCL is HIGH.
The I2C-bus master always generates the START and STOP conditions. The bus is busy
after the START condition. The bus is free again a certain time after the STOP condition.
The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition.
The START (S) and repeated START (Sr) conditions are functionally identical. Therefore,
S is used as a generic term to represent both the START (S) and repeated START (Sr)
conditions.
SDA SDA
SCL SCL
S P
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8.1.4.4 Acknowledge
An acknowledge must be sent at the end of one data byte. The acknowledge-related clock
pulse is generated by the master. The transmitter of data, either master or slave, releases
the SDA line (HIGH) during the acknowledge clock pulse. The receiver pulls down the
SDA line during the acknowledge clock pulse so that it remains stable LOW during the
HIGH period of this clock pulse.
The master can then generate either a STOP (P) condition to stop the transfer or a
repeated START (Sr) condition to start a new transfer.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from
1 2 8 9
master
S
clock pulse for
START
acknowledgement
condition
mbc602
P
SDA
byte complete,
interrupt within slave
SCL S Sr
or 1 2 7 8 9 1 2 3-8 9 or
Sr P
ACK ACK
START or STOP or
repeated START repeated START
condition condition
msc608
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Several address numbers are reserved. During device configuration, the designer must
ensure that collisions with these reserved addresses cannot occur. Check the I2C-bus
specification for a complete list of reserved addresses.
The I2C-bus address specification is dependent on the definition of pin EA. Immediately
after releasing pin NRSTPD or after a power-on reset, the device defines the I2C-bus
address according to pin EA.
If pin EA is set LOW, the upper 4 bits of the device bus address are reserved by
NXP Semiconductors and set to 0101b for all MFRC522 devices. The remaining 3 bits
(ADR_0, ADR_1, ADR_2) of the slave address can be freely configured by the customer
to prevent collisions with other I2C-bus devices.
If pin EA is set HIGH, ADR_0 to ADR_5 can be completely specified at the external pins
according to Table 5 on page 9. ADR_6 is always set to logic 0.
In both modes, the external address coding is latched immediately after releasing the
reset condition. Further changes at the used pins are not taken into consideration.
Depending on the external wiring, the I2C-bus address pins can be used for test signal
outputs.
MSB LSB
• The first byte of a frame indicates the device address according to the I2C-bus rules.
• The second byte indicates the register address followed by up to n-data bytes.
In one frame all data bytes are written to the same register address. This enables fast
FIFO buffer access. The Read/Write (R/W) bit is set to logic 0.
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• Firstly, a write access to the specific register address must be performed as indicated
in the frame that follows
• The first byte of a frame indicates the device address according to the I2C-bus rules
• The second byte indicates the register address. No data bytes are added
• The Read/Write bit is 0
After the write access, read access can start. The host sends the device address of the
MFRC522. In response, the MFRC522 sends the content of the read access register. In
one frame all data bytes can be read from the same register address. This enables fast
FIFO buffer access or register polling.
write cycle
I2C-BUS 0
S SLAVE ADDRESS A 0 0 JOINER REGISTER A [0:n] DATA A
(W) ADDRESS [A5:A0] [7:0]
[A7:A0]
read cycle
I2C-BUS 0
S SLAVE ADDRESS A 0 0 JOINER REGISTER A P
(W) ADDRESS [A5:A0]
[A7:A0]
[0:n]
I2C-BUS
1 DATA
S SLAVE ADDRESS A [0:n] A
(R) [7:0]
[A7:A0]
DATA A P
[7:0]
sent by master
001aak592
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• The inputs of the device in HS mode incorporate spike suppression, a Schmitt trigger
on the SDA and SCL inputs and different timing constants when compared to
F/S mode
• The output buffers of the device in HS mode incorporate slope control of the falling
edges of the SDA and SCL signals with different fall times compared to F/S mode
When HS mode starts, the active master sends a repeated START condition (Sr) followed
by a 7-bit slave address with a R/W bit address and receives an acknowledge bit (A) from
the selected MFRC522.
Data transfer continues in HS mode after the next repeated START (Sr), only switching
back to F/S mode after a STOP condition (P). To reduce the overhead of the master code,
a master links a number of HS mode transfers, separated by repeated START conditions
(Sr).
F/S mode HS mode (current-source for SCL HIGH enabled) F/S mode
(n-bytes + A)
HS mode continues
Sr SLAVE ADDRESS
001aak749
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A t1
8-bit master code 0000 1xxx
S tH
SDA high
SCL high 1 2 to 5 6 7 8 9
F/S mode
SDA high
SCL high 1 2 to 5 6 7 8 9 1 2 to 5 6 7 8 9
If P then
HS mode F/S mode
If Sr (dotted lines)
then HS mode
tH
tFS
= Master current source pull-up
msc618
= Resistor pull-up
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1. Adapt the SDA and SCL input filters according to the spike suppression requirement
in HS mode.
2. Adapt the slope control of the SDA output stages.
It is possible for system configurations that do not have other I2C-bus devices involved in
the communication to switch to HS mode permanently. This is implemented by setting
Status2Reg register’s I2CForceHS bit to logic 1. In permanent HS mode, the master code
is not required to be sent. This is not defined in the specification and must only be used
when no other devices are connected on the bus. In addition, spikes on the I2C-bus lines
must be avoided because of the reduced spike suppression.
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8.2.1 General
The integrated contactless UART supports the external host online with framing and error
checking of the protocol requirements up to 848 kBd. An external circuit can be connected
to the communication interface pins MFIN and MFOUT to modulate and demodulate the
data.
The contactless UART handles the protocol requirements for the communication
protocols in cooperation with the host. Protocol handling generates bit and byte-oriented
framing. In addition, it handles error detection such as parity and CRC, based on the
various supported contactless communication protocols.
Remark: The size and tuning of the antenna and the power supply voltage have an
important impact on the achievable operating distance.
8.2.2 TX p-driver
The signal on pins TX1 and TX2 is the 13.56 MHz energy carrier modulated by an
envelope signal. It can be used to drive an antenna directly using a few passive
components for matching and filtering; see Section 15 on page 81. The signal on pins TX1
and TX2 can be configured using the TxControlReg register; see Section 9.3.2.5 on
page 50.
The modulation index can be set by adjusting the impedance of the drivers. The
impedance of the p-driver can be configured using registers CWGsPReg and
ModGsPReg. The impedance of the n-driver can be configured using the GsNReg
register. The modulation index also depends on the antenna design and tuning.
The TxModeReg and TxSelReg registers control the data rate and framing during
transmission and the antenna driver setting to support the different requirements at the
different modes and transfer speeds.
Table 15. Register and bit settings controlling the signal on pin TX1
Bit Bit Bit Bit Envelope Pin GSPMos GSNMos Remarks
Tx1RFEn Force InvTx1RFOn InvTx1RFOff TX1
100ASK
0 X[1] X[1] X[1] X[1] X[1] X[1] X[1] not specified if RF is
switched off
1 0 0 X[1] 0 RF pMod nMod 100 % ASK: pin TX1
1 RF pCW nCW pulled to logic 0,
independent of the
0 1 X[1] 0 RF pMod nMod InvTx1RFOff bit
1 RF pCW nCW
1 1 X[1] 0 0 pMod nMod
1 RF_n pCW nCW
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Table 16. Register and bit settings controlling the signal on pin TX2
Bit Bit Bit Bit Bit Envelope Pin GSPMos GSNMos Remarks
Tx1RFEn Force Tx2CW InvTx2RFOn InvTx2RFOff TX2
100ASK
0 X[1] X[1] X[1] X[1] X[1] X[1] X[1] X[1] not specified if
RF is switched
off
1 0 0 0 X[1] 0 RF pMod nMod -
1 RF pCW nCW
1 X[1] 0 RF_n pMod nMod
1 RF_n pCW nCW
1 0 X[1] X[1] RF pCW nCW conductance
1 X[1] X[1] RF_n pCW nCW always CW for
the Tx2CW bit
1 0 0 X[1] 0 0 pMod nMod 100 % ASK: pin
1 RF pCW nCW TX2 pulled
to logic 0
1 X[1] 0 0 pMod nMod (independent of
1 RF_n pCW nCW the
InvTx2RFOn/Inv
1 0 X[1] X[1] RF pCW nCW
Tx2RFOff bits)
1 X[1] X[1] RF_n pCW nCW
The following abbreviations have been used in Table 15 and Table 16:
• RF: 13.56 MHz clock derived from 27.12 MHz quartz crystal oscillator divided by 2
• RF_n: inverted 13.56 MHz clock
• GSPMos: conductance, configuration of the PMOS array
• GSNMos: conductance, configuration of the NMOS array
• pCW: PMOS conductance value for continuous wave defined by the CWGsPReg
register
• pMod: PMOS conductance value for modulation defined by the ModGsPReg register
• nCW: NMOS conductance value for continuous wave defined by the GsNReg
register’s CWGsN[3:0] bits
• nMod: NMOS conductance value for modulation defined by the GsNReg register’s
ModGsN[3:0] bits
• X = do not care.
Remark: If only one driver is switched on, the values for CWGsPReg, ModGsPReg and
GsNReg registers are used for both drivers.
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This topology allows the analog block of the MFRC522 to be connected to the digital block
of another device.
The serial signal switch is controlled by the TxSelReg and RxSelReg registers.
Figure 20 shows the serial data switch for p-driver TX1 and TX2.
DriverSel[1:0]
3-state 00
INTERNAL INVERT IF envelope
01
CODER InvMod = 1
10 to driver TX1 and TX2
0 = impedance = modulated
1 11
1 = impedance = CW
INVERT IF
MFIN
PolMFin = 0
001aak593
Fig 20. Serial data switch for p-driver TX1 and TX2
This topology allows some parts of the analog block to be connected to the digital block of
another device.
Switch MFOutSel in the TxSelReg register can be used to measure MIFARE and
ISO/IEC14443 A related signals. This is especially important during the design-in phase
or for test purposes as it enables checking of the transmitted and received data.
The most important use of pins MFIN and MFOUT is found in the active antenna concept.
An external active antenna circuit can be connected to the MFRC522’s digital block.
Switch MFOutSel must be configured so that the internal Miller encoded signal is sent to
pin MFOUT (MFOutSel = 100b). UARTSel[1:0] must be configured to receive a
Manchester signal with subcarrier from pin MFIN (UARTSel[1:0] = 01).
It is possible to connect a passive antenna to pins TX1, TX2 and RX (using the
appropriate filter and matching circuit) and an active antenna to pins MFOUT and MFIN at
the same time. In this configuration, two RF circuits can be driven (one after another) by a
single host processor.
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Remark: Pins MFIN and MFOUT have a dedicated supply on pin SVDD with the ground
on pin PVSS. If pin MFIN is not used it must be connected to either pin SVDD or pin
PVSS. If pin SVDD is not used it must be connected to either pin DVDD, pin PVDD or any
other voltage supply pin.
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NXP Semiconductors
MFOUT
DRIVER
test bus 3 HIGH 3
Sel[1:0]
internal envelope 4
Rev. 3.8 — 17 September 2014
SUBCARRIER
0 LOW DEMODULATOR
1 Manchester with subcarrier
RX bit stream MANCHESTER
2 internal modulated
DECODER DEMODULATOR RX
UART 3 NRZ coding without subcarrier (> 106 kBd)
Sel[1:0]
MFRC522
Fig 21. Overview of MFIN and MFOUT signal routing
28 of 95
NXP Semiconductors MFRC522
Standard 3V MIFARE reader solution
• The CRC preset value can be either 0000h, 6363h, A671h or FFFFh depending on
the ModeReg register’s CRCPreset[1:0] bits setting
• The CRC polynomial for the 16-bit CRC is fixed to x16 + x12 + x5 + 1
• The CRCResultReg register indicates the result of the CRC calculation. This register
is split into two 8-bit registers representing the higher and lower bytes.
• The ModeReg register’s MSBFirst bit indicates that data will be loaded with the MSB
first.
When the microcontroller starts a command, the MFRC522 can, while the command is in
progress, access the FIFO buffer according to that command. Only one FIFO buffer has
been implemented which can be used for input and output. The microcontroller must
ensure that there are not any unintentional FIFO buffer accesses.
• ComIEnReg register’s LoAlertIEn bit is set to logic 1. It activates pin IRQ when
Status1Reg register’s LoAlert bit changes to logic 1.
• ComIEnReg register’s HiAlertIEn bit is set to logic 1. It activates pin IRQ when
Status1Reg register’s HiAlert bit changes to logic 1.
If the maximum number of WaterLevel bytes (as set in the WaterLevelReg register) or less
are stored in the FIFO buffer, the HiAlert bit is set to logic 1. It is generated according to
Equation 3:
If the number of WaterLevel bytes (as set in the WaterLevelReg register) or less are
stored in the FIFO buffer, the LoAlert bit is set to logic 1. It is generated according to
Equation 4:
The ComIrqReg register’s TxIRq bit indicates that the transmitter has finished. If the state
changes from sending data to transmitting the end of the frame pattern, the transmitter
unit automatically sets the interrupt bit. The CRC coprocessor sets the DivIrqReg
register’s CRCIRq bit after processing all the FIFO buffer data which is indicated by
CRCReady bit = 1.
The ComIrqReg register’s RxIRq bit indicates an interrupt when the end of the received
data is detected. The ComIrqReg register’s IdleIRq bit is set if a command finishes and
the Command[3:0] value in the CommandReg register changes to idle (see Table 149 on
page 70).
The ComIrqReg register’s HiAlertIRq bit is set to logic 1 when the Status1Reg register’s
HiAlert bit is set to logic 1 which means that the FIFO buffer has reached the level
indicated by the WaterLevel[5:0] bits.
The ComIrqReg register’s LoAlertIRq bit is set to logic 1 when the Status1Reg register’s
LoAlert bit is set to logic 1 which means that the FIFO buffer has reached the level
indicated by the WaterLevel[5:0] bits.
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The ComIrqReg register’s ErrIRq bit indicates an error detected by the contactless UART
during send or receive. This is indicated when any bit is set to logic 1 in register ErrorReg.
• Timeout counter
• Watchdog counter
• Stop watch
• Programmable one shot
• Periodical trigger
The timer unit can be used to measure the time interval between two events or to indicate
that a specific event occurred after a specific time. The timer can be triggered by events
explained in the paragraphs below. The timer does not influence any internal events, for
example, a time-out during data reception does not automatically influence the reception
process. Furthermore, several timer-related bits can be used to generate an interrupt.
The timer has an input clock of 13.56 MHz derived from the 27.12 MHz quartz crystal
oscillator. The timer consists of two stages: prescaler and counter.
The prescaler (TPrescaler) is a 12-bit counter. The reload values (TReloadVal_Hi[7:0] and
TReloadVal_Lo[7:0]) for TPrescaler can be set between 0 and 4095 in the TModeReg
register’s TPrescaler_Hi[3:0] bits and TPrescalerReg register’s TPrescaler_Lo[7:0] bits.
The reload value for the counter is defined by 16 bits between 0 and 65535 in the
TReloadReg register.
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The timer can be started manually using the ControlReg register’s TStartNow bit and
stopped using the ControlReg register’s TStopNow bit.
The timer can also be activated automatically to meet any dedicated protocol
requirements by setting the TModeReg register’s TAuto bit to logic 1.
The delay time of a timer stage is set by the reload value + 1. The total delay time (td1) is
calculated using Equation 5:
TPrescaler 2 + 1 TReloadVal + 1
t d1 = --------------------------------------------------------------------------------------------------------- (5)
13.56 MHz
An example of calculating total delay time (td) is shown in Equation 6, where the
TPrescaler value = 4095 and TReloadVal = 65535:
4095 2 + 1 65535 + 1
39.59 s = ----------------------------------------------------------------------- (6)
13.56 MHz
Example: To give a delay time of 25 s requires 339 clock cycles to be counted and a
TPrescaler value of 169. This configures the timer to count up to 65535 time-slots for
every 25 s period.
The MFRC522 version 2.0 offers in addition a second prescaler timer. Due to the fact that
the prescaler counts down to 0 the prescaler period always count an odd number of
clocks (1, 3, 5, ..). This may lead to inaccuracy. The second available prescaler timer
implements the possibility to change the prescaler reload value to odd numbers, which
results in an even prescaler period. This new prescaler can be enabled only in version 2.0
using the register bit DemodeReg, see Table 72. Within this option, the total delay time
(td2) is calculated using Equation 5:
TPrescaler 2 + 2 TReloadVal + 1
t d2 = --------------------------------------------------------------------------------------------------------- (7)
13.56 MHz
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During soft power-down, all register values, the FIFO buffer content and the configuration
keep their current contents.
After setting the PowerDown bit to logic 0, it takes 1024 clocks until the Soft power-down
mode is exited indicated by the PowerDown bit. Setting it to logic 0 does not immediately
clear it. It is cleared automatically by the MFRC522 when Soft power-down mode is
exited.
Remark: If the internal oscillator is used, you must take into account that it is supplied by
pin AVDD and it will take a certain time (tosc) until the oscillator is stable and the clock
cycles can be detected by the internal logic. It is recommended for the serial UART, to first
send the value 55h to the MFRC522. The oscillator must be stable for further access to
the registers. To ensure this, perform a read access to address 0 until the MFRC522
answers to the last read command with the register content of address 0. This indicates
that the MFRC522 is ready.
MFRC522
OSCOUT OSCIN
27.12 MHz
001aak595
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The clock applied to the MFRC522 provides a time basis for the synchronous system’s
encoder and decoder. The stability of the clock frequency, therefore, is an important factor
for correct operation. To obtain optimum performance, clock jitter must be reduced as
much as possible. This is best achieved using the internal oscillator buffer with the
recommended circuitry.
If an external clock source is used, the clock signal must be applied to pin OSCIN. In this
case, special care must be taken with the clock duty cycle and clock jitter and the clock
quality must be verified.
The time (tstartup) is the start-up time of the crystal oscillator circuit. The crystal oscillator
start-up time is defined by the crystal.
The time (td) is the internal delay time of the MFRC522 when the clock signal is stable
before the MFRC522 can be addressed.
1024 = 37.74 s
t d = -------------
- (8)
27 s
device activation
oscillator
clock stable
clock ready
tstartup
td
tosc
t
001aak596
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9. MFRC522 registers
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Table 21. Reserved register (address 00h); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved
Access -
Table 23. CommandReg register (address 01h); reset value: 20h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol: reserved RcvOff PowerDown Command[3:0]
Access: - R/W D D
Table 25. ComIEnReg register (address 02h); reset value: 80h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol IRqInv TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn ErrIEn TimerIEn
Access R/W R/W R/W R/W R/W R/W R/W R/W
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Table 27. DivIEnReg register (address 03h); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol IRQPushPull reserved MfinActIEn reserved CRCIEn reserved
Access R/W - R/W - R/W -
Table 29. ComIrqReg register (address 04h); reset value: 14h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq
Access W D D D D D D D
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Table 31. DivIrqReg register (address 05h); reset value: x0h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol Set2 reserved MfinActIRq reserved CRCIRq reserved
Access W - D - D -
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Table 33. ErrorReg register (address 06h); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol WrErr TempErr reserved BufferOvfl CollErr CRCErr ParityErr ProtocolErr
Access R R - R R R R R
[1] Command execution clears all error bits except the TempErr bit. Cannot be set by software.
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Table 35. Status1Reg register (address 07h); reset value: 21h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved CRCOk CRCReady IRq TRunning reserved HiAlert LoAlert
Access - R R R R - R R
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Table 37. Status2Reg register (address 08h); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol TempSensClear I2CForceHS reserved MFCrypto1On ModemState[2:0]
Access R/W R/W - D R
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Table 39. FIFODataReg register (address 09h); reset value: xxh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol FIFOData[7:0]
Access D
Table 41. FIFOLevelReg register (address 0Ah); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol FlushBuffer FIFOLevel[6:0]
Access W R
Table 43. WaterLevelReg register (address 0Bh); reset value: 08h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved WaterLevel[5:0]
Access - R/W
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Table 45. ControlReg register (address 0Ch); reset value: 10h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol TStopNow TStartNow reserved RxLastBits[2:0]
Access W W - R
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Table 47. BitFramingReg register (address 0Dh); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol StartSend RxAlign[2:0] reserved TxLastBits[2:0]
Access W R/W - R/W
Table 49. CollReg register (address 0Eh); reset value: xxh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol ValuesAfterColl reserved CollPosNotValid CollPos[4:0]
Access R/W - R R
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Table 51. Reserved register (address 0Fh); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved
Access -
Table 53. Reserved register (address 10h); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved
Access -
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Table 55. ModeReg register (address 11h); reset value: 3Fh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol MSBFirst reserved TxWaitRF reserved PolMFin reserved CRCPreset[1:0]
Access R/W - R/W - R/W - R/W
Table 57. TxModeReg register (address 12h); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol TxCRCEn TxSpeed[2:0] InvMod reserved
Access R/W D R/W -
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Table 59. RxModeReg register (address 13h); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol RxCRCEn RxSpeed[2:0] RxNoErr RxMultiple reserved
Access R/W D R/W R/W -
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Table 61. TxControlReg register (address 14h); reset value: 80h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol InvTx2RF InvTx1RF InvTx2RF InvTx1RF Tx2CW reserved Tx2RFEn Tx1RFEn
On On Off Off
Access R/W R/W R/W R/W R/W - R/W R/W
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Table 63. TxASKReg register (address 15h); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved Force100ASK reserved
Access - R/W -
Table 65. TxSelReg register (address 16h); reset value: 10h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol: reserved DriverSel[1:0] MFOutSel[3:0]
Access: - R/W R/W
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Table 67. RxSelReg register (address 17h); reset value: 84h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol UARTSel[1:0] RxWait[5:0]
Access R/W R/W
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Table 69. RxThresholdReg register (address 18h); reset value: 84h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol MinLevel[3:0] reserved CollLevel[2:0]
Access R/W - R/W
Table 71. DemodReg register (address 19h); reset value: 4Dh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol AddIQ[1:0] FixIQ TPrescal TauRcv[1:0] TauSync[1:0]
Even
Access R/W R/W R/W R/W R/W
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Table 73. Reserved register (address 1Ah); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved
Access -
Table 75. Reserved register (address 1Bh); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved
Access -
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Table 77. MfTxReg register (address 1Ch); reset value: 62h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved TxWait[1:0]
Access - R/W
Table 79. MfRxReg register (address 1Dh); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved ParityDisable reserved
Access - R/W -
Table 81. Reserved register (address 1Eh); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved
Access -
Table 83. SerialSpeedReg register (address 1Fh); reset value: EBh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol BR_T0[2:0] BR_T1[4:0]
Access R/W R/W
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Table 85. Reserved register (address 20h); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol -
Access reserved
Table 87. CRCResultReg (higher bits) register (address 21h); reset value: FFh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol CRCResultMSB[7:0]
Access R
Table 89. CRCResultReg (lower bits) register (address 22h); reset value: FFh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol CRCResultLSB[7:0]
Access R
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Table 91. Reserved register (address 23h); reset value: 88h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved
Access -
Table 93. ModWidthReg register (address 24h); reset value: 26h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol ModWidth[7:0]
Access R/W
Table 95. Reserved register (address 25h); reset value: 87h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved
Access -
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Table 97. RFCfgReg register (address 26h); reset value: 48h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved RxGain[2:0] reserved
Access - R/W -
Table 99. GsNReg register (address 27h); reset value: 88h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol CWGsN[3:0] ModGsN[3:0]
Access R/W R/W
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Table 101. CWGsPReg register (address 28h); reset value: 20h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved CWGsP[5:0]
Access - R/W
Table 103. ModGsPReg register (address 29h); reset value: 20h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved ModGsP[5:0]
Access - R/W
Remark: The TPrescaler setting higher 4 bits are in the TModeReg register and the lower
8 bits are in the TPrescalerReg register.
Table 105. TModeReg register (address 2Ah); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol TAuto TGated[1:0] TAutoRestart TPrescaler_Hi[3:0]
Access R/W R/W R/W R/W
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Table 107. TPrescalerReg register (address 2Bh); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol TPrescaler_Lo[7:0]
Access R/W
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Remark: The reload value bits are contained in two 8-bit registers.
Table 109. TReloadReg (higher bits) register (address 2Ch); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol TReloadVal_Hi[7:0]
Access R/W
Table 111. TReloadReg (lower bits) register (address 2Dh); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol TReloadVal_Lo[7:0]
Access R/W
Remark: The timer value bits are contained in two 8-bit registers.
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Table 113. TCounterValReg (higher bits) register (address 2Eh); reset value: xxh bit
allocation
Bit 7 6 5 4 3 2 1 0
Symbol TCounterVal_Hi[7:0]
Access R
Table 115. TCounterValReg (lower bits) register (address 2Fh); reset value: xxh bit
allocation
Bit 7 6 5 4 3 2 1 0
Symbol TCounterVal_Lo[7:0]
Access R
Table 117. Reserved register (address 30h); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved
Access -
Table 119. TestSel1Reg register (address 31h); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved TstBusBitSel[2:0]
Access - R/W
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Table 121. TestSel2Reg register (address 32h); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol TstBusFlip PRBS9 PRBS15 TestBusSel[4:0]
Access R/W R/W R/W R/W
Table 123. TestPinEnReg register (address 33h); reset value: 80h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol RS232LineEn TestPinEn[5:0] reserved
Access R/W R/W -
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Table 125. TestPinValueReg register (address 34h); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol UseIO TestPinValue[5:0] reserved
Access R/W R/W -
Table 127. TestBusReg register (address 35h); reset value: xxh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol TestBus[7:0]
Access R
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Table 129. AutoTestReg register (address 36h); reset value: 40h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved AmpRcv RFT SelfTest[3:0]
Access - R/W - R/W
Table 131. VersionReg register (address 37h); reset value: xxh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol Version[7:0]
Access R
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Table 133. AnalogTestReg register (address 38h); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol AnalogSelAux1[3:0] AnalogSelAux2[3:0]
Access R/W R/W
[1] Remark: Current source output; the use of 1 k pull-down resistor on AUXn is recommended.
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Table 135. TestDAC1Reg register (address 39h); reset value: xxh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved TestDAC1[5:0]
Access - R/W
Table 137. TestDAC2Reg register (address 3Ah); reset value: xxh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved TestDAC2[5:0]
Access - R/W
Table 139. TestADCReg register (address 3Bh); reset value: xxh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol ADC_I[3:0] ADC_Q[3:0]
Access R R
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Table 141. Reserved register (address 3Ch); reset value: FFh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol RFT
Access -
Table 143. Reserved register (address 3Dh); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol RFT
Access -
Table 145. Reserved register (address 3Eh); reset value: 03h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol RFT
Access -
Table 147. Reserved register (address 3Fh); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved
Access -
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Arguments and/or data necessary to process a command are exchanged via the FIFO
buffer.
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10.3.1.1 Idle
Places the MFRC522 in Idle mode. The Idle command also terminates itself.
10.3.1.2 Mem
Transfers 25 bytes from the FIFO buffer to the internal buffer.
To read out the 25 bytes from the internal buffer the Mem command must be started with
an empty FIFO buffer. In this case, the 25 bytes are transferred from the internal buffer to
the FIFO.
During a hard power-down (using pin NRSTPD), the 25 bytes in the internal buffer remain
unchanged and are only lost if the power supply is removed from the MFRC522.
This command automatically terminates when finished and the Idle command becomes
active.
10.3.1.4 CalcCRC
The FIFO buffer content is transferred to the CRC coprocessor and the CRC calculation is
started. The calculation result is stored in the CRCResultReg register. The CRC
calculation is not limited to a dedicated number of bytes. The calculation is not stopped
when the FIFO buffer is empty during the data stream. The next byte written to the FIFO
buffer is added to the calculation.
The CRC preset value is controlled by the ModeReg register’s CRCPreset[1:0] bits. The
value is loaded in to the CRC coprocessor when the command starts.
If the AutoTestReg register’s SelfTest[3:0] bits are set correctly, the MFRC522 enters Self
Test mode. Starting the CalcCRC command initiates a digital self test. The result of the
self test is written to the FIFO buffer.
10.3.1.5 Transmit
The FIFO buffer content is immediately transmitted after starting this command. Before
transmitting the FIFO buffer content, all relevant registers must be set for data
transmission.
This command automatically terminates when the FIFO buffer is empty. It can be
terminated by another command written to the CommandReg register.
10.3.1.6 NoCmdChange
This command does not influence any running command in the CommandReg register. It
can be used to manipulate any bit except the CommandReg register Command[3:0] bits,
for example, the RcvOff bit or the PowerDown bit.
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10.3.1.7 Receive
The MFRC522 activates the receiver path and waits for a data stream to be received. The
correct settings must be chosen before starting this command.
This command automatically terminates when the data stream ends. This is indicated
either by the end of frame pattern or by the length byte depending on the selected frame
type and speed.
Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Receive
command will not automatically terminate. It must be terminated by starting another
command in the CommandReg register.
10.3.1.8 Transceive
This command continuously repeats the transmission of data from the FIFO buffer and the
reception of data from the RF field. The first action is transmit and after transmission the
command is changed to receive a data stream.
Each transmit process must be started by setting the BitFramingReg register’s StartSend
bit to logic 1. This command must be cleared by writing any command to the
CommandReg register.
Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Transceive
command never leaves the receive state because this state cannot be cancelled
automatically.
10.3.1.9 MFAuthent
This command manages MIFARE authentication to enable a secure communication to
any MIFARE Mini, MIFARE 1K and MIFARE 4K card. The following data is written to the
FIFO buffer before the command can be activated:
Remark: When the MFAuthent command is active all access to the FIFO buffer is
blocked. However, if there is access to the FIFO buffer, the ErrorReg register’s WrErr bit is
set.
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This command automatically terminates when the MIFARE card is authenticated and the
Status2Reg register’s MFCrypto1On bit is set to logic 1.
This command does not terminate automatically if the card does not answer, so the timer
must be initialized to automatic mode. In this case, in addition to the IdleIRq bit, the
TimerIRq bit can be used as the termination criteria. During authentication processing, the
RxIRq bit and TxIRq bit are blocked. The Crypto1On bit is only valid after termination of
the MFAuthent command, either after processing the protocol or writing Idle to the
CommandReg register.
If an error occurs during authentication, the ErrorReg register’s ProtocolErr bit is set to
logic 1 and the Status2Reg register’s Crypto1On bit is set to logic 0.
10.3.1.10 SoftReset
This command performs a reset of the device. The configuration data of the internal buffer
remains unchanged. All registers are set to the reset values. This command automatically
terminates when finished.
Remark: The SerialSpeedReg register is reset and therefore the serial data rate is set to
9.6 kBd.
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[1] Supply voltages below 3 V reduce the performance (the achievable operating distance).
[2] VDDA, VDDD and VDD(TVDD) must always be the same voltage.
[3] VDD(PVDD) must always be the same or lower voltage than VDDD.
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14. Characteristics
Table 153. Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Input characteristics
Pins EA, I2C and NRSTPD
ILI input leakage current 1 - +1 A
VIH HIGH-level input voltage 0.7VDD(PVDD) - - V
VIL LOW-level input voltage - - 0.3VDD(PVDD) V
Pin MFIN
ILI input leakage current 1 - +1 A
VIH HIGH-level input voltage 0.7VDD(SVDD) - - V
VIL LOW-level input voltage - - 0.3VDD(SVDD) V
Pin SDA
ILI input leakage current 1 - +1 A
VIH HIGH-level input voltage 0.7VDD(PVDD) - - V
VIL LOW-level input voltage - - 0.3VDD(PVDD) V
Pin RX[1]
Vi input voltage 1 - VDDA +1 V
Ci input capacitance VDDA = 3 V; receiver active; - 10 - pF
VRX(p-p) = 1 V; 1.5 V (DC)
offset
Ri input resistance VDDA = 3 V; receiver active; - 350 -
VRX(p-p) = 1 V; 1.5 V (DC)
offset
Input voltage range; see Figure 24
Vi(p-p)(min) minimum peak-to-peak input Manchester encoded; - 100 - mV
voltage VDDA = 3 V
Vi(p-p)(max) maximum peak-to-peak input Manchester encoded; - 4 - V
voltage VDDA = 3 V
Input sensitivity; see Figure 24
Vmod modulation voltage minimum Manchester - 5 - mV
encoded; VDDA = 3 V;
RxGain[2:0] = 111b (48 dB)
Pin OSCIN
ILI input leakage current 1 - +1 A
VIH HIGH-level input voltage 0.7VDDA - - V
VIL LOW-level input voltage - - 0.3VDDA V
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[1] The voltage on pin RX is clamped by internal diodes to pins AVSS and AVDD.
[2] Ipd is the total current for all supplies.
[3] IDD(PVDD) depends on the overall load at the digital pins.
[4] IDD(TVDD) depends on VDD(TVDD) and the external circuit connected to pins TX1 and TX2.
[5] During typical circuit operation, the overall current is below 100 mA.
[6] Typical value using a complementary driver configuration and an antenna matched to 40 between pins TX1 and TX2 at 13.56 MHz.
[7] IDD(SVDD) depends on the load at pin MFOUT.
Vmod
Vi(p-p)(max) Vi(p-p)(min)
VMID
13.56 MHz
carrier
0V
001aak012
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MFRC522 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
SCK
tSLDX
tSLNH
NSS
001aaj634
Remark: The signal NSS must be LOW to be able to send several bytes in one data stream.
To send more than one data stream NSS must be set HIGH between the data streams.
Fig 25. Timing diagram for SPI
SDA
tf tSU;DAT tSP tr
tLOW tf tHD;STA tBUF
SCL
tr tHIGH tSU;STO
tHD;STA tSU;STA
S tHD;DAT Sr P S
001aaj635
Fig 26. Timing for Fast and Standard mode devices on the I2C-bus
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The antenna tuning and RF part matching is described in the application note Ref. 1 and
Ref. 2.
supply
L0 C1 Ra
NRSTPD TX1
6 11 antenna
host
interface MFRC522 C0 C2
MICRO- TVSS
10, 14 Lant
PROCESSOR
C0 C2
L0 C1 Ra
IRQ TX2
23 13
AVSS DVSS
18 4
21 22
OSCIN OSCOUT
27.12 MHz
001aaj636
MFRC522 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
MFRC522 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Table 158 shows the signals that can be switched to pin AUX1 or AUX2 by setting
AnalogSelAux1[3:0] or AnalogSelAux2[3:0] in the AnalogTestReg register.
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Figure 28 shows test signal TestDAC1 on pin AUX1 and TestDAC2 on pin AUX2 when the
TestDAC1Reg register is programmed with a slope defined by values 00h to 3Fh and the
TestDAC2Reg register is programmed with a rectangular signal defined by values 00h
and 3Fh.
001aak597
(1)
(2)
100 ms/div
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001aak598
(1)
(2)
(3)
10 μs/div
16.1.3.3 Example: Output test signals ADC channel I and ADC channel Q
Figure 30 shows the channel behavior test signals ADC_I and ADC_Q on pins AUX1 and
AUX2, respectively. The AnalogTestReg register is set to 56h.
001aak599
(1)
(2)
(3)
5 μs/div
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• At 106 kBd, RxActive is HIGH during data bits, parity and CRC reception. Start bits
are not included
• At 106 kBd, TxActive is HIGH during start bits, data bits, parity and CRC transmission
• At 212 kBd, 424 kBd and 848 kBd, RxActive is HIGH during data bits and CRC
reception. Start bits are not included
• At 212 kBd, 424 kBd and 848 kBd, TxActive is HIGH during data bits and CRC
transmission
001aak600
(1)
(2)
(3)
10 μs/div
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001aak601
(1)
(2)
20 μs/div
16.1.3.6 PRBS
The pseudo-random binary sequences PRBS9 and PRBS15 are based on ITU-TO150
and are defined with the TestSel2Reg register. Transmission of either data stream is
started by the Transmit command. The preamble/sync byte/start bit/parity bit are
automatically generated depending on the mode selected.
Remark: All relevant registers for transmitting data must be configured in accordance with
ITU-TO150 before selecting PRBS transmission.
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HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm SOT617-1
D B A
terminal 1
index area A
A1
E c
detail X
e1 C
e 1/2 e b v M C A B y1 C y
9 16 w M C
L
17
8
e
Eh e2
1/2 e
1
24
terminal 1
index area 32 25
Dh X
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
A(1)
UNIT A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1
max.
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
01-08-08
SOT617-1 --- MO-220 ---
02-10-18
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chamfer
barcode label (permanent)
PIN 1
barcode label (peel-off)
chamfer
QA seal
PIN 1
Hyatt patent preprinted
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20. Abbreviations
Table 159. Abbreviations
Acronym Description
ADC Analog-to-Digital Converter
BPSK Binary Phase Shift Keying
CRC Cyclic Redundancy Check
CW Continuous Wave
DAC Digital-to-Analog Converter
HBM Human Body Model
I2C Inter-integrated Circuit
LSB Least Significant Bit
MISO Master In Slave Out
MM Machine Model
MOSI Master Out Slave In
MSB Most Significant Bit
NRZ Not Return to Zero
NSS Not Slave Select
PLL Phase-Locked Loop
PRBS Pseudo-Random Bit Sequence
RX Receiver
SOF Start Of Frame
SPI Serial Peripheral Interface
TX Transmitter
UART Universal Asynchronous Receiver Transmitter
21. References
[1] Application note — MFRC52x Reader IC Family Directly Matched Antenna
Design
[2] Application note — MIFARE (ISO/IEC 14443 A) 13.56 MHz RFID Proximity
Antennas
MFRC522 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
MFRC522 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
23.2 Definitions Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Draft — The document is a draft version only. The content is still under
malfunction of an NXP Semiconductors product can reasonably be expected
internal review and subject to formal approval, which may result in
to result in personal injury, death or severe property or environmental
modifications or additions. NXP Semiconductors does not give any
damage. NXP Semiconductors and its suppliers accept no liability for
representations or warranties as to the accuracy or completeness of
inclusion and/or use of NXP Semiconductors products in such equipment or
information included herein and shall have no liability for the consequences of
applications and therefore such inclusion and/or use is at the customer’s own
use of such information.
risk.
Short data sheet — A short data sheet is an extract from a full data sheet
Applications — Applications that are described herein for any of these
with the same product type number(s) and title. A short data sheet is intended
products are for illustrative purposes only. NXP Semiconductors makes no
for quick reference only and should not be relied upon to contain detailed and
representation or warranty that such applications will be suitable for the
full information. For detailed and full information see the relevant full data
specified use without further testing or modification.
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the Customers are responsible for the design and operation of their applications
full data sheet shall prevail. and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
Product specification — The information and data provided in a Product design. It is customer’s sole responsibility to determine whether the NXP
data sheet shall define the specification of the product as agreed between Semiconductors product is suitable and fit for the customer’s applications and
NXP Semiconductors and its customer, unless NXP Semiconductors and products planned, as well as for the planned application and use of
customer have explicitly agreed otherwise in writing. In no event however, customer’s third party customer(s). Customers should provide appropriate
shall an agreement be valid in which the NXP Semiconductors product is design and operating safeguards to minimize the risks associated with their
deemed to offer functions and qualities beyond those described in the applications and products.
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
23.3 Disclaimers customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Limited warranty and liability — Information in this document is believed to
Semiconductors products in order to avoid a default of the applications and
be accurate and reliable. However, NXP Semiconductors does not give any
the products or of the application or use by customer’s third party
representations or warranties, expressed or implied, as to the accuracy or
customer(s). NXP does not accept any liability in this respect.
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no Limiting values — Stress above one or more limiting values (as defined in
responsibility for the content in this document if provided by an information the Absolute Maximum Ratings System of IEC 60134) will cause permanent
source outside of NXP Semiconductors. damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
In no event shall NXP Semiconductors be liable for any indirect, incidental,
the Recommended operating conditions section (if present) or the
punitive, special or consequential damages (including - without limitation - lost
Characteristics sections of this document is not warranted. Constant or
profits, lost savings, business interruption, costs related to the removal or
repeated exposure to limiting values will permanently and irreversibly affect
replacement of any products or rework charges) whether or not such
the quality and reliability of the device.
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory. Terms and conditions of commercial sale — NXP Semiconductors
Notwithstanding any damages that customer might incur for any reason products are sold subject to the general terms and conditions of commercial
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards sale, as published at http://www.nxp.com/profile/terms, unless otherwise
customer for the products described herein shall be limited in accordance agreed in a valid written individual agreement. In case an individual
with the Terms and conditions of commercial sale of NXP Semiconductors. agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
Right to make changes — NXP Semiconductors reserves the right to make applying the customer’s general terms and conditions with regard to the
changes to information published in this document, including without purchase of NXP Semiconductors products by customer.
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior No offer to sell or license — Nothing in this document may be interpreted or
to the publication hereof. construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
MFRC522 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Export control — This document as well as the item(s) described herein NXP Semiconductors’ specifications such use shall be solely at customer’s
may be subject to export control regulations. Export might require a prior own risk, and (c) customer fully indemnifies NXP Semiconductors for any
authorization from competent authorities. liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
Quick reference data — The Quick reference data is an extract of the
standard warranty and NXP Semiconductors’ product specifications.
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding. Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
Non-automotive qualified products — Unless this data sheet expressly
between the translated and English versions.
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
23.4 Trademarks
non-automotive qualified products in automotive equipment or applications. Notice: All referenced brands, product names, service names and trademarks
In the event that customer uses the product for design-in and use in are the property of their respective owners.
automotive applications to automotive specifications and standards, customer I2C-bus — logo is a trademark of NXP Semiconductors N.V.
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b) MIFARE — is a trademark of NXP Semiconductors N.V.
whenever customer uses the product for automotive applications beyond
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25. Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8.6 Power reduction modes . . . . . . . . . . . . . . . . . 33
2 General description . . . . . . . . . . . . . . . . . . . . . . 1 8.6.1 Hard power-down. . . . . . . . . . . . . . . . . . . . . . 33
2.1 Differences between version 1.0 and 2.0 . . . . . 1 8.6.2 Soft power-down mode . . . . . . . . . . . . . . . . . 33
8.6.3 Transmitter power-down mode . . . . . . . . . . . 33
3 Features and benefits . . . . . . . . . . . . . . . . . . . . 2
8.7 Oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . 33
4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 8.8 Reset and oscillator start-up time . . . . . . . . . 34
5 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 8.8.1 Reset timing requirements . . . . . . . . . . . . . . . 34
6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8.8.2 Oscillator start-up time . . . . . . . . . . . . . . . . . . 34
7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 9 MFRC522 registers . . . . . . . . . . . . . . . . . . . . . 35
7.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 9.1 Register bit behavior . . . . . . . . . . . . . . . . . . . 35
8 Functional description . . . . . . . . . . . . . . . . . . . 8 9.2 Register overview . . . . . . . . . . . . . . . . . . . . . 36
8.1 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . 9 9.3 Register descriptions . . . . . . . . . . . . . . . . . . . 38
8.1.1 Automatic microcontroller interface detection. . 9 9.3.1 Page 0: Command and status . . . . . . . . . . . . 38
8.1.2 Serial Peripheral Interface . . . . . . . . . . . . . . . 10 9.3.1.1 Reserved register 00h . . . . . . . . . . . . . . . . . . 38
8.1.2.1 SPI read data . . . . . . . . . . . . . . . . . . . . . . . . . 10 9.3.1.2 CommandReg register. . . . . . . . . . . . . . . . . . 38
8.1.2.2 SPI write data . . . . . . . . . . . . . . . . . . . . . . . . . 11 9.3.1.3 ComIEnReg register . . . . . . . . . . . . . . . . . . . 38
8.1.2.3 SPI address byte . . . . . . . . . . . . . . . . . . . . . . 11 9.3.1.4 DivIEnReg register. . . . . . . . . . . . . . . . . . . . . 39
8.1.3 UART interface . . . . . . . . . . . . . . . . . . . . . . . . 11 9.3.1.5 ComIrqReg register . . . . . . . . . . . . . . . . . . . . 39
8.1.3.1 Connection to a host. . . . . . . . . . . . . . . . . . . . 11 9.3.1.6 DivIrqReg register . . . . . . . . . . . . . . . . . . . . . 40
8.1.3.2 Selectable UART transfer speeds . . . . . . . . . 12 9.3.1.7 ErrorReg register . . . . . . . . . . . . . . . . . . . . . . 41
8.1.3.3 UART framing . . . . . . . . . . . . . . . . . . . . . . . . . 13 9.3.1.8 Status1Reg register . . . . . . . . . . . . . . . . . . . . 42
8.1.4 I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 16 9.3.1.9 Status2Reg register . . . . . . . . . . . . . . . . . . . . 43
8.1.4.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.3.1.10 FIFODataReg register . . . . . . . . . . . . . . . . . . 44
8.1.4.2 START and STOP conditions . . . . . . . . . . . . . 17 9.3.1.11 FIFOLevelReg register. . . . . . . . . . . . . . . . . . 44
8.1.4.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.3.1.12 WaterLevelReg register . . . . . . . . . . . . . . . . . 44
8.1.4.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.3.1.13 ControlReg register . . . . . . . . . . . . . . . . . . . . 45
8.1.4.5 7-Bit addressing . . . . . . . . . . . . . . . . . . . . . . . 19 9.3.1.14 BitFramingReg register . . . . . . . . . . . . . . . . . 46
8.1.4.6 Register write access . . . . . . . . . . . . . . . . . . . 19 9.3.1.15 CollReg register . . . . . . . . . . . . . . . . . . . . . . . 46
8.1.4.7 Register read access . . . . . . . . . . . . . . . . . . . 20 9.3.1.16 Reserved register 0Fh . . . . . . . . . . . . . . . . . . 47
8.1.4.8 High-speed mode . . . . . . . . . . . . . . . . . . . . . . 21 9.3.2 Page 1: Communication. . . . . . . . . . . . . . . . . 47
8.1.4.9 High-speed transfer . . . . . . . . . . . . . . . . . . . . 21 9.3.2.1 Reserved register 10h . . . . . . . . . . . . . . . . . . 47
8.1.4.10 Serial data transfer format in HS mode . . . . . 21 9.3.2.2 ModeReg register . . . . . . . . . . . . . . . . . . . . . 48
8.1.4.11 Switching between F/S mode and HS mode . 23 9.3.2.3 TxModeReg register . . . . . . . . . . . . . . . . . . . 48
8.1.4.12 MFRC522 at lower speed modes . . . . . . . . . . 23 9.3.2.4 RxModeReg register . . . . . . . . . . . . . . . . . . . 49
8.2 Analog interface and contactless UART . . . . . 24 9.3.2.5 TxControlReg register . . . . . . . . . . . . . . . . . . 50
8.2.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.3.2.6 TxASKReg register . . . . . . . . . . . . . . . . . . . . 51
8.2.2 TX p-driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.3.2.7 TxSelReg register . . . . . . . . . . . . . . . . . . . . . 51
8.2.3 Serial data switch . . . . . . . . . . . . . . . . . . . . . . 26 9.3.2.8 RxSelReg register . . . . . . . . . . . . . . . . . . . . . 52
8.2.4 MFIN and MFOUT interface support . . . . . . . 26 9.3.2.9 RxThresholdReg register . . . . . . . . . . . . . . . . 53
8.2.5 CRC coprocessor . . . . . . . . . . . . . . . . . . . . . . 29 9.3.2.10 DemodReg register . . . . . . . . . . . . . . . . . . . . 53
8.3 FIFO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.3.2.11 Reserved register 1Ah . . . . . . . . . . . . . . . . . . 54
8.3.1 Accessing the FIFO buffer . . . . . . . . . . . . . . . 29 9.3.2.12 Reserved register 1Bh . . . . . . . . . . . . . . . . . . 54
8.3.2 Controlling the FIFO buffer . . . . . . . . . . . . . . . 29 9.3.2.13 MfTxReg register . . . . . . . . . . . . . . . . . . . . . . 54
8.3.3 FIFO buffer status information . . . . . . . . . . . . 29 9.3.2.14 MfRxReg register . . . . . . . . . . . . . . . . . . . . . . 55
8.4 Interrupt request system . . . . . . . . . . . . . . . . . 30 9.3.2.15 Reserved register 1Eh . . . . . . . . . . . . . . . . . . 55
8.4.1 Interrupt sources overview . . . . . . . . . . . . . . . 30 9.3.2.16 SerialSpeedReg register . . . . . . . . . . . . . . . . 55
8.5 Timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.3.3 Page 2: Configuration . . . . . . . . . . . . . . . . . . 57
9.3.3.1 Reserved register 20h . . . . . . . . . . . . . . . . . . 57
continued >>
MFRC522 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
AVX
Tantalum Leaded
Capacitors
AVX Tantalum
Ask The World Of Us
As one of the world’s broadest line leaded
tantalum suppliers, and the major radial
tantalum manufacturer, it is our mission to
provide First In Class Technology,
Quality and Service, by establishing
progressive design, manufacturing and
continuous improvement programs
driving toward a single goal:
TOTAL CUSTOMER SATISFACTION
AVX offers a broad line of solid tantalum capacitors in a wide powered applications, such as hearing aids, in mind. The
range of sizes, styles, and ratings to meet any design “X” case size in the TMH line is the smallest leaded tantalum
needs. This catalog combines into one source AVX’s leaded capacitor available in the world.
tantalum capacitor information from its worldwide tantalum AVX has a complete tantalum applications service available
operations. for use by all our customers. With the capability to prototype
The TAP is rated for use from -55°C to +85°C at rated and mass produce solid tantalum capacitors in special
voltage and up to +125°C with voltage derating. There configurations, almost any design need can be fulfilled.
are three preferred wire forms to choose from which are And if the customer requirements are outside our standard
available on tape and reel, and in bulk for hand insertion. testing, AVX will work with you to define and implement a
Four sizes of molded axials, the TAR series, are also test or screening plan.
available. The TAR is fully marked and available on tape and AVX is determined to become the world leader in tantalum
reel for high speed insertion. The TAA is a hermetically capacitor technology and has made, and is continuing to
sealed series also with four case sizes available. make, significant investments in equipment and research to
The TMH series (MINITAN ® ) leaded capacitors are reach that end. We believe that the investment has paid off
available in both axial and radial configurations. with the devices shown on the following pages.
The TMH series is designed with small battery-
Contents
Page
Introduction Foreword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1
Dipped Radial Capacitors
Introduction
Tantalum Graphite
Resin encapsulation
Tantalum Wire
Terminal Wire
Silver
Solder
Manganese
dioxide
Tantalum
pentoxide
2
Dipped Radial Capacitors
Wire Form Outline
SOLID TANTALUM RESIN DIPPED TAP
Preferred Wire Forms
D D D
Figure 1 Figure 2 Figure 3
2.0(0.08)
H H1 + 4 (0.16) max H1
+ max
+
L L
S L S
S
d d
2 (0.079) 2 (0.079)
d
min min
Wire Form C Wire Form B Wire Form S
Non-Preferred Wire Forms (Not recommended for new designs)
Figure 4 D Figure 5 Figure 6 D
D
L 0.079 (2)
min L
1.10 +0.25
-0.10 L
(0.4 +0.010
S S
-0.004 )
S d d
Wire Form F Wire Form D Wire Form G
3
Dipped Radial Capacitors
TAP Series
HOW TO ORDER
TAP 475 M 035 SCS
Type Capacitance Code Capacitance Tolerance Rated DC Voltage Suffix indicating wire form
pF code: 1st two digits K = ±10% and packaging
represent significant figures, M = ±20% (see page 3)
3rd digit represents multiplier (For J = ±5% tolerance,
(number of zeros to follow) please consult factory)
4
Dipped Radial Capacitors
TAP Series
TECHNICAL SPECIFICATIONS
Technical Data: All technical data relate to an ambient temperature of +25°C
Capacitance Range: 0.1µF to 330µF
Capacitance Tolerance: ±20%; ±10% (±5% consult your AVX representative for details)
Rated Voltage DC (VR ) %+85°C: 6.3 10 16 20 25 35 50
Category Voltage (VC ) %+125°C: 4 6.3 10 13 16 23 33
Surge Voltage (VS ) %+85°C: 8 13 20 26 33 46 65
%+125°C: 5 9 12 16 21 28 40
Temperature Range: -55°C to +125°C
Environmental Classification: 55/125/56 (IEC 68-2)
Dissipation Factor: %0.04 for CR 0.1-1.5µF
%0.06 for CR 2.2-6.8µF
%0.08 for CR 10-68µF
%0.10 for CR 100-330µF
Reliability: 1% per 1000 hrs. at 85°C with 0.1Ω/V series impedance, 60% confidence level.
MARKING
Polarity, capacitance, rated DC voltage, and an "A" (AVX
logo) are laser marked on the capacitor body which is made
of flame retardant gold epoxy resin with a limiting oxygen
index in excess of 30 (ASTM-D-2863).
5
Dipped Radial Capacitors
TAP Series
RATINGS AND PART NUMBER REFERENCE
AVX Case Capacitance DCL DF ESR AVX Case Capacitance DCL DF ESR
Part No. Size µF (µA) % max. (Ω) Part No. Size µF (µA) % max. (Ω)
Max. Max. @ 100 kHz Max. Max. @ 100 kHz
6.3 volt @ 85°C (4 volt @ 125°C) 20 volt @ 85°C (13 volt @ 125°C) continued
TAP 335(*)006 A 3.3 0.5 6 13.0 TAP 336(*)020 J 33 5.2 8 1.4
TAP 475(*)006 A 4.7 0.5 6 10.0 TAP 476(*)020 K 47 7.5 8 1.2
TAP 685(*)006 A 6.8 0.5 6 8.0 TAP 686(*)020 N 68 10.8 8 0.9
TAP 106(*)006 B 10 0.5 8 6.0 TAP 107(*)020 N 100 16.0 10 0.6
TAP 156(*)006 C 15 0.8 8 5.0
TAP 226(*)006 D 22 1.1 8 3.7 25 volt @ 85°C (16 volt @ 125°C)
TAP 336(*)006 E 33 1.7 8 3.0 TAP 105(*)025 A 1.0 0.5 4 10.0
TAP 476(*)006 F 47 2.4 8 2.0 TAP 155(*)025 A 1.5 0.5 4 8.0
TAP 686(*)006 G 68 3.4 8 1.8 TAP 225(*)025 A 2.2 0.5 6 6.0
TAP 107(*)006 H 100 5.0 10 1.6 TAP 335(*)025 B 3.3 0.6 6 5.0
TAP 157(*)006 K 150 7.6 10 0.9 TAP 475(*)025 C 4.7 0.9 6 4.0
TAP 227(*)006 M 220 11.0 10 0.9 TAP 685(*)025 D 6.8 1.3 6 3.1
TAP 337(*)006 P 330 16.6 10 0.7 TAP 106(*)025 E 10 2.0 8 2.5
TAP 156(*)025 F 15 3.0 8 2.0
10 volt @ 85°C (6.3 volt @ 125°C) TAP 226(*)025 H 22 4.4 8 1.5
TAP 225(*)010 A 2.2 0.5 6 13.0 TAP 336(*)025 J 33 6.6 8 1.2
TAP 335(*)010 A 3.3 0.5 6 10.0 TAP 476(*)025 M 47 9.4 8 1.0
TAP 475(*)010 A 4.7 0.5 6 8.0 TAP 686(*)025 N 68 13.6 8 0.8
TAP 685(*)010 B 6.8 0.5 6 6.0
TAP 106(*)010 C 10 0.8 8 5.0 35 volt @ 85°C (23 volt @ 125°C)
TAP 156(*)010 D 15 1.2 8 3.7 TAP 104(*)035 A 0.1 0.5 4 26.0
TAP 226(*)010 E 22 1.7 8 2.7 TAP 154(*)035 A 0.15 0.5 4 21.0
TAP 336(*)010 F 33 2.6 8 2.1 TAP 224(*)035 A 0.22 0.5 4 17.0
TAP 476(*)010 G 47 3.7 8 1.7 TAP 334(*)035 A 0.33 0.5 4 15.0
TAP 686(*)010 H 68 5.4 8 1.3 TAP 474(*)035 A 0.47 0.5 4 13.0
TAP 107(*)010 K 100 8.0 10 1.0 TAP 684(*)035 A 0.68 0.5 4 10.0
TAP 157(*)010 N 150 12.0 10 0.8 TAP 105(*)035 A 1.0 0.5 4 8.0
TAP 227(*)010 P 220 17.6 10 0.6 TAP 155(*)035 A 1.5 0.5 4 6.0
TAP 337(*)010 R 330 20.0 10 0.5 TAP 225(*)035 B 2.2 0.6 6 5.0
TAP 335(*)035 C 3.3 0.9 6 4.0
16 volt @ 85°C (10 volt @ 125°C) TAP 475(*)035 E 4.7 1.3 6 3.0
TAP 155(*)016 A 1.5 0.5 4 10.0 TAP 685(*)035 F 6.8 1.9 6 2.5
TAP 225(*)016 A 2.2 0.5 6 8.0 TAP 106(*)035 F 10 2.8 8 2.0
TAP 335(*)016 A 3.3 0.5 6 6.0 TAP 156(*)035 H 15 4.2 8 1.6
TAP 475(*)016 B 4.7 0.6 6 5.0 TAP 226(*)035 K 22 6.1 8 1.3
TAP 685(*)016 C 6.8 0.8 6 4.0 TAP 336(*)035 M 33 9.2 8 1.0
TAP 106(*)016 D 10 1.2 8 3.2 TAP 476(*)035 N 47 10.0 8 0.8
TAP 156(*)016 E 15 1.9 8 2.5
TAP 226(*)016 F 22 2.8 8 2.0 50 volt @ 85°C (33 volt @ 125°C)
TAP 336(*)016 F 33 4.2 8 1.6 TAP 104(*)050 A 0.1 0.5 4 26.0
TAP 476(*)016 J 47 6.0 8 1.3 TAP 154(*)050 A 0.15 0.5 4 21.0
TAP 686(*)016 L 68 8.7 8 1.0 TAP 224(*)050 A 0.22 0.5 4 17.0
TAP 107(*)016 N 100 12.8 10 0.8 TAP 334(*)050 A 0.33 0.5 4 15.0
TAP 157(*)016 N 150 19.2 10 0.6 TAP 474(*)050 A 0.47 0.5 4 13.0
TAP 227(*)016 R 220 20.0 10 0.5 TAP 684(*)050 B 0.68 0.5 4 10.0
TAP 105(*)050 C 1.0 0.5 4 8.0
20 volt @ 85°C (13 volt @ 125°C) TAP 155(*)050 D 1.5 0.6 4 6.0
TAP 105(*)020 A 1.0 0.5 4 10.0 TAP 225(*)050 E 2.2 0.8 6 3.5
TAP 155(*)020 A 1.5 0.5 4 9.0 TAP 335(*)050 F 3.3 1.3 6 3.0
TAP 225(*)020 A 2.2 0.5 6 7.0 TAP 475(*)050 G 4.7 1.8 6 2.5
TAP 335(*)020 B 3.3 0.5 6 5.5 TAP 685(*)050 H 6.8 2.7 6 2.0
TAP 475(*)020 C 4.7 0.7 6 4.5 TAP 106(*)050 J 10 4.0 8 1.6
TAP 685(*)020 D 6.8 1.0 6 3.6 TAP 156(*)050 K 15 6.0 8 1.2
TAP 106(*)020 E 10 1.6 8 2.9 TAP 226(*)050 L 22 8.8 8 1.0
TAP 156(*)020 F 15 2.4 8 2.3
(*) Insert capacitance tolerance code; M for ±20%, K for ±10% and J for ±5%
TAP 226(*)020 H 22 3.5 8 1.8
NOTE: Voltage ratings are minimum values. AVX reserves the right to supply higher
voltage ratings in the same case size.
6
Dipped Radial Capacitors
Tape and Reel Packaging
SOLID TANTALUM RESIN DIPPED TAP
P2 DP
Dh
P2 DP
Dh
P2 DP
Dh
7
Dipped Radial Capacitors
Tape and Reel Packaging
SOLID TANTALUM RESIN DIPPED TAP
Feed hole diameter D 4.0 ± 0.2 (0.15 ± 0.008) Manufactured from cardboard with plastic hub.
Tape width W 18.0 + 1.0 (0.7 + 0.04) Ma u actured rom
- 0.5 - 0.02) cardboard with plastic hub.
Hold down tape width W1 6.0 (0.24) min.
Hold down tape position W2 1.0 (0.04) max.
Lead wire clench height H 16 ± 0.5 (0.63 ± 0.02)
19 ± 1.0 (0.75 ± 0.04)
on request
Hole position H1 9.0 ± 0.5 (0.35 ± 0.02)
Base of component height H2 18 (0.7) min. (S wire only)
Component height H3 32.25 (1.3) max.
Length of snipped lead L 11.0 (0.43) max. H ldi id
Total tape thickness T 0.7 ± 0.2 (0.03 ± 0.001) Holding tape outside. Positive terminal leading
(negative terminal by special request).
Carrying card
0.5 ± 0.1 (0.02 ± 0.005)
PACKAGING QUANTITIES
For Reels For ‘Ammo’ pack For bulk products
Style Case code No. of pieces Style Case code No. of pieces Style Case code No. of pieces
A 1500 A, B, C, D 3000 A to H 1000
B, C, D 1250 TAP E, F, G 2500 TAP J to L 500
TAP E, F 1000 H, J 2000 M to R 100
G, H, J 750 K, L, M, N, P, R 1000
K, L, M, N, P, R 500
8
Molded Axial Capacitors
TAR Series
HOW TO ORDER
TAR R 335 M 015
9
Molded Axial Capacitors
TAR Series
TECHNICAL SPECIFICATIONS
Technical Data: All technical data relate to an ambient temperature of +25°C
Capacitance Range: 0.1µF to 68µF
Capacitance Tolerance: ±20%; ±10%; ±5%
Rated Voltage DC (VR ) %+85°C: 4 6.3 10 15 20 25 35 50
Category Voltage (VC ) %+125°C: 2.7 4 6.3 10 13 17 23 33
Surge Voltage (VS ) %+85°C: 5.2 8 13 20 26 33 46 65
%+125°C: 3.5 5 9 12 16 21 28 40
Temperature Range: -55°C to +125°C
Environmental Classification: 55/125/56 (IEC 68-2)
Dissipation Factor: See part number table
MARKING
• Polarity • Capacitance • Date code
• Tolerance • Voltage
10
Molded Axial Capacitors
TAR Series
RATINGS AND PART NUMBER REFERENCE
AVX Case Capacitance DCL DF ESR AVX Case Capacitance DCL DF ESR
Part No. Size µF (µA) % max. (Ω) Part No. Size µF (µA) % max. (Ω)
Max. Max. @ 100 kHz Max. Max. @ 100 kHz
4 volt @ 85°C (2.7 volt @ 125°C) 25 volt @ 85°C (17 volt @ 125°C)
TARQ475(*)004 Q 4.7 0.5 8 12 TARQ474(*)025 Q 0.47 0.5 3 20
TARQ685(*)004 Q 6.8 0.5 8 10 TARQ684(*)025 Q 0.68 0.5 3 16
TARR106(*)004 R 10 0.5 8 10 TARQ105(*)025 Q 1.0 0.5 3 12
TARR156(*)004 R 15 0.5 8 8.0 TARR155(*)025 R 1.5 0.5 3 8.0
TARR226(*)004 R 22 0.7 8 6.0 TARR225(*)025 R 2.2 0.5 3 6.0
TARS336(*)004 S 33 1.1 8 5.0 TARR335(*)025 R 3.3 0.7 3 5.0
TARS476(*)004 S 47 1.5 8 3.5 TARS475(*)025 S 4.7 0.9 4 4.0
TARW686(*)004 W 68 2.2 8 2.5 TARS685(*)025 S 6.8 1.4 4 3.1
TARS106(*)025 S 10 1.5 4 2.5
6.3 volt @ 85°C (4 volt @ 125°C) TARW156(*)025 W 15 3.0 4 2.0
TARQ335(*)006 Q 3.3 0.5 4 14
TARQ475(*)006 Q 4.7 0.5 4 10 35 volt @ 85°C (23 volt @ 125°C)
TARR685(*)006 R 6.8 0.5 6 8.0 TARQ104(*)035 Q 0.1 0.5 3 26
TARR106(*)006 R 10 0.5 6 6.0 TARQ154(*)035 Q 0.15 0.5 3 21
TARR156(*)006 R 15 0.7 6 5.0 TARQ224(*)035 Q 0.22 0.5 3 17
TARS226(*)006 S 22 1.1 6 3.7 TARQ334(*)035 Q 0.33 0.5 3 15
TARS336(*)006 S 33 1.5 6 3.0 TARQ474(*)035 Q 0.47 0.5 3 13
TARW476(*)006 W 47 2.3 6 2.0 TARR684(*)035 R 0.68 0.5 3 10
TARW686(*)006 W 68 3.3 6 1.8 TARR105(*)035 R 1.0 0.5 3 8.0
TARR155(*)035 R 1.5 0.5 3 6.0
10 volt @ 85°C (7 volt @ 125°C) TARS225(*)035 S 2.2 0.6 3 5.0
TARQ225(*)010 Q 2.2 0.5 4 14 TARS335(*)035 S 3.3 0.9 4 4.0
TARQ335(*)010 Q 3.3 0.5 4 10 TARS475(*)035 S 4.7 1.3 4 3.0
TARR475(*)010 R 4.7 0.5 4 8.0 TARW685(*)035 W 6.8 1.9 4 2.5
TARR685(*)010 R 6.8 0.5 6 6.0 TARW106(*)035 W 10 2.8 4 2.0
TARR106(*)010 R 10 0.8 6 5.0
TARS156(*)010 S 15 1.2 6 3.7 50 volt @ 85°C (33 volt @ 125°C)
TARS226(*)010 S 22 1.5 6 2.7 TARQ104(*)050 Q 0.1 0.5 3 26
TARW336(*)010 W 33 2.6 6 2.1 TARQ154(*)050 Q 0.15 0.5 3 21
TARW476(*)010 W 47 3.8 6 1.7 TARQ224(*)050 Q 0.22 0.5 3 17
TARR334(*)050 R 0.33 0.5 3 15
15 volt @ 85°C (10 volt @ 125°C) TARR474(*)050 R 0.47 0.5 3 13
TARQ155(*)015 Q 1.5 0.5 4 14 TARR684(*)050 R 0.68 0.5 3 10
TARQ225(*)015 Q 2.2 0.5 4 8.0 TARR105(*)050 R 1.0 0.5 3 8.0
TARR335(*)015 R 3.3 0.5 4 6.0 TARS155(*)050 S 1.5 0.6 4 5.0
TARR475(*)015 R 4.7 0.6 4 5.0 TARS225(*)050 S 2.2 0.9 4 3.5
TARR685(*)015 R 6.8 0.8 6 4.0 TARW335(*)050 W 3.3 1.3 4 3.0
TARS106(*)015 S 10 1.2 6 3.2 TARW475(*)050 W 4.7 1.9 4 2.5
TARS156(*)015 S 15 1.5 6 2.5
(*) Insert capacitance tolerance code; M for ±20%, K for ±10% and J for ±5%
TARW226(*)015 W 22 2.6 6 2.0
TARW336(*)015 W 33 4.0 6 1.6 NOTE: Voltage ratings are minimum values. AVX reserves the right to supply higher
voltage ratings in the same case size.
20 volt @ 85°C (13 volt @ 125°C)
TARQ105(*)020 Q 1.0 0.5 4 18
TARQ155(*)020 Q 1.5 0.5 4 12
TARR225(*)020 R 2.2 0.5 4 7.0
TARR335(*)020 R 3.3 0.5 4 5.5
TARR475(*)020 R 4.7 0.8 4 4.5
TARS685(*)020 S 6.8 1.1 6 3.7
TARS106(*)020 S 10 1.6 6 2.8
TARW156(*)020 W 15 2.4 6 2.3
TARW226(*)020 W 22 3.5 6 1.9
11
Hermetic Axial Capacitors
TAA Series
HOW TO ORDER
TAA A 105 M 035 G
Type Case Code Capacitance Code Capacitance Rated DC Voltage TAA Packaging
pF code: Tolerance Suffixes
1st two digits represent K = ±10% (see page 15)
significant figures, M = ±20%
3rd digit represents (For J = ±5%
multiplier (number of tolerance, please
zeros to follow) consult factory)
12
Hermetic Axial Capacitors
TAA Series
TECHNICAL SPECIFICATIONS
Construction: Hermetically sealed; Temperature Range: -55°C to +125°C
axial terminations Environmental
Capacitance Range: 0.1µF to 330µF Classification: 55/125/56 (IEC 68-2)
Dissipation Factor: (tan d) %0.04 for C=0.1 to 4.7µF
Capacitance Tolerance: ±20%; ±10%; ±5%
%0.06 for C= 6.8 to 100µF
Measuring Conditions: 120 Hz, 20°C
%0.08 for C= 150 to 330µF
Rated Voltage VDC %+85°C: 6.3 10 16 20 25 35 50
Approvals: BS CECC 30 201-001
Category Voltage VDC %+125°C: 4 6.3 10 13 17 23 33 IECQ QC 300 201 GB0002
Surge Voltage VDC %+85°C: 8 13 20 26 33 46 65 CECC 30 201-005 CTS 13
%+125°C: 5 9 12 16 21 28 40 CECC 30 201-019 CTS 32
13
Hermetic Axial Capacitors
TAA Series
14
Axial Capacitors
Tape and Reel Packaging
SOLID TANTALUM AXIAL TAR AND TAA
G 30 max.
400 max.
P
n
Shape: Circular or Octagonal
K E
7.00 max. L
15
MINITAN® Capacitors
TMH Series
Figure 1
C B
E d
Radial Axial
Case Sizes
X, W, U
Leads – Leads are solder coated pure nickel wire suitable for soldering or welding.
Tested in accordance with MIL-STD-202, Method 211, .010 diameter leads
withstand a 1-lb. pull and .007 diameter leads an 8 oz. pull. All lead diameters
withstand 5 rotations twist.
16
MINITAN® Capacitors
TMH Series
TECHNICAL SPECIFICATIONS
Technical Data: All technical data relate to an ambient temperature of +25°C
Capacitance Range: 0.001µF to 10µF
Capacitance Tolerance: ±20%; ±10%; ±5%
Rated Voltage DC (VR) %+85°C: 2 3 4 6 10 15 20
Category Voltage (VC) %+125°C: 1.3 2 2.6 4 6.7 10 13
Surge Voltage (VS) %+85°C: 2.6 4 5.2 8 13 19 26
%+125°C: 1.7 2.6 3.4 5.2 8.7 13 16
Temperature Range: -55°C to +125°C
Dissipation Factor: see part number table
Life Test: After 2000 hrs. at 85°C with VR applied.
∆CAP = ±15% max.
∆DF, DCL = initial limit.
HOW TO ORDER
TMH W 472 M 020 R B SZ0000
Type Case Code Capacitance Code Tolerance Rated DC Voltage Lead Packaging Other Product
(See table pF code: 1st two digits J = ±5% Configuration B = Bulk Information
on page 16) represent significant K = ±10% R = Radial (100 pcs per bag) SZ = Standard
figures, 3rd digit M = ±20% A = Axial Product
represents multiplier 0000 = Standard
(number of zeros Product
to follow)
MARKING
Capacitance value shall be typographically marked on all
case sizes.
• Capacitance • Tolerance code:
• Polarity ±20% = Standard (no marking)
• Radial = Red dot on top of unit ±10% = Silver dot
• Axial = Red end ±5% = Gold dot
Tolerance
Color Code Dot
Tolerance
Polarity Color Code Dot
Polarity
106
106
17
MINITAN® Capacitors
TMH Series
18
Technical Summary and
Application Guidelines
CONTENTS
Section 1: Electrical Characteristics and Explanation of Terms. The following example uses a 22µF 25V capacitor to
Section 2: A.C. Operation and Ripple Voltage. illustrate the point.
Section 3: Reliability and Calculation of Failure Rate. «o«r A
C=
Section 4: Application Guidelines for Tantalum Capacitors. d
Section 5: Mechanical and Thermal Properties of where «o is the dielectric constant of free space
Leaded Capacitors. (8.855 x 10-12 Farads/m)
Section 6: Qualification approval status. «r is the relative dielectric constant for Tantalum
Pentoxide (27)
d is the dielectric thickness in meters
INTRODUCTION (for a typical 25V part)
Tantalum capacitors are manufactured from a powder of pure C is the capacitance in Farads
tantalum metal. The typical particle size is between 2 and 10 µm.
and A is the surface area in meters
Rearranging this equation gives
Cd
A= «o«r
thus for a 22µF/25V capacitor the surface area is 150 square
centimeters, or nearly 1⁄2 the size of this page.
19
Technical Summary and
Application Guidelines
The pentoxide (Ta 2 O 5 ) dielectric grows at a rate of
Tantalum
1.7 x 10-9 m/V
Dielectric thickness (d) = 100 x 1.7 x 10-9
= 0.17 µm
Dielectric
Electric Field strength = Working Voltage / d Oxide Film
= 147 KV/mm
Manganese
Dioxide
Tantalum
20
Technical Summary and
Application Guidelines
SECTION 1:
ELECTRICAL CHARACTERISTICS AND EXPLANATION OF TERMS
1.1 CAPACITANCE
1.1.1 Rated capacitance (CR) 1.1.3 Capacitance tolerance
This is the nominal rated capacitance. For tantalum capaci- This is the permissible variation of the actual value of the
tors it is measured as the capacitance of the equivalent capacitance from the rated value.
series circuit at 20°C in a measuring bridge supplied by a 1.1.4 Frequency dependence of the capacitance
120 Hz source free of harmonics with 2.2V DC bias max.
The effective capacitance decreases as frequency increases.
1.1.2 Temperature dependence on the capacitance Beyond 100 kHz the capacitance continues to drop until res-
The capacitance of a tantalum capacitor varies with temper- onance is reached (typically between 0.5-5 MHz depending
ature. This variation itself is dependent to a small extent on on the rating). Beyond this the device becomes inductive.
the rated voltage and capacitor size. See graph below for
typical capacitance changes with temperature.
1.4
TYPICAL CAPACITANCE vs. TEMPERATURE
1.2
15 1.0
CAP (mF)
1.0mF 35V
10 0.8
% Capacitance
5 0.6
0 0.4
100Hz 1kHz 10kHz 100kHz
-5 FREQUENCY
-10
-15
90
1.2.2 Category voltage (VC)
This is the maximum voltage that may be applied continu-
ously to a capacitor. It is equal to the rated voltage up to 80
+85°C, beyond which it is subject to a linear derating, to 2/3
VR at 125°C.
70
1.2.3 Surge voltage (VS)
This is the highest voltage that may be applied to a capaci-
60
tor for short periods of time. The surge voltage may be
applied up to 10 times in an hour for periods of up to
30 seconds at a time. The surge voltage must not be used 50
as a parameter in the design of circuits in which, in the 75 85 95 105 115 125
normal course of operation, the capacitor is periodically Temperature °C
charged and discharged.
21
Technical Summary and
Application Guidelines
1.2.5 Reverse voltage and non-polar operation
85°C 125°C
The reverse voltage ratings are designed to cover excep-
Rated Surge Category Surge tional conditions of small level excursions into incorrect
Voltage Voltage Voltage Voltage
(V DC) (V DC) (V DC) (V DC) polarity. The values quoted are not intended to cover contin-
2 2.6 1.3 1.7 uous reverse operation.
3 4 2 2.6 The peak reverse voltage applied to the capacitor must not
4 5.2 2.6 3.4
6.3 8 4 5 exceed:
10 13 6.3 9 10% of rated DC working voltage to a maximum of
16 20 10 12
20 26 13 16 1V at 25°C
25 33 16 21 3% of rated DC working voltage to a maximum of
35 46 23 28
50 65 33 40 0.5V at 85°C
1% of category DC working voltage to a maximum of
0.1V at 125°C
1.2.6 Non-polar operation
1.2.4 Effect of surges
If the higher reverse voltages are essential, then two capaci-
The solid Tantalum capacitor has a limited ability to with- tors, each of twice the required capacitance and of equal
stand surges (15% to 30% of rated voltage). This is in tolerance and rated voltage, should be connected in a
common with all other electrolytic capacitors and is due to back-to-back configuration, i.e., both anodes or both
the fact that they operate under very high electrical stress cathodes joined together. This is necessary in order to avoid
within the oxide layer. In the case of ‘solid’ electrolytic a reduction in life expectancy.
capacitors this is further complicated by the limited self
1.2.7 Superimposed AC voltage (Vrms) - Ripple Voltage
healing ability of the manganese dioxide semiconductor.
This is the maximum RMS alternating voltage, superim-
It is important to ensure that the voltage across the terminals
posed on a DC voltage, that may be applied to a capacitor.
of the capacitor does not exceed the surge voltage rating at
The sum of the DC voltage and the surge value of the
any time. This is particularly so in low impedance circuits
superimposed AC voltage must not exceed the category
where the capacitor is likely to be subjected to the full impact
voltage, Vc. Full details are given in Section 2.
of surges, especially in low inductance applications. Even
an extremely short duration spike is likely to cause damage. 1.2.8 Voltage derating
In such situations it will be necessary to use a higher voltage Refer to section 3.2 (page 27) for the effect of voltage
rating. derating on reliability.
20 10 35
V
F
F
0m
3m
fied frequency. (Terms also used are power factor, loss factor 1.0
DF%
and dielectric loss, Cos (90 - d) is the true power factor.) The 10
measurement of Tan d is carried out at +20°C and 120 Hz
with 2.2V DC bias max. with an AC voltage free of harmonics. 5
1
100Hz 1kHz 10kHz 100kHz
FREQUENCY
22
Technical Summary and
Application Guidelines
1.3.4 Temperature dependence of dissipation factor Typical Curves-Dissipation Factor vs. Temperature
Dissipation factor varies with temperature as the typical
curves show to the right. For maximum limits please refer to
ratings tables. 10
100mF/6V
DF %
5
1mF/35V
0
-55 -40 -20 0 20 40 60 80 100 125
Temperature °C
23
Technical Summary and
Application Guidelines
1.4.4 Temperature dependence of the impedance and ESR Temperature Dependence of the
Impedance and ESR
At 100 kHz, impedance and ESR behave identically and
decrease with increasing temperature as the typical curves
show. For maximum limits at high and low temperatures, 100
please refer to graph opposite.
ESR/Impedance Z (V)
1/35
10
10/35
1
47/35
0.1
-55 -40 -20 0 +20 +40 +60 +80 +100 +125
Temperature T (°C)
1.5 DC LEAKAGE CURRENT (DCL)
1.5.1 Leakage current (DCL) Temperature Dependence of the
The leakage current is dependent on the voltage applied, Leakage Current for a Typical Component
the time, and the capacitor temperature. It is measured
at +25°C with the rated voltage applied. A protective resis-
tance of 1000V is connected in series with the capacitor
in the measuring circuit. 10
LEAKAGE CURRENT DCLT/DCL 25°C
x
V max = 1- (T-85)
120 c x V volts
R 0.1
-55 -40 -20 0 20 40 60 80 100 125
TEMPERATURE °C
where T is the required operating temperature. Maximum
limits are given in rating tables. Effect of Voltage Derating on Leakage Current
1.5.3 Voltage dependence of the leakage current
LEAKAGE CURRENT RATIO DCL/DCL @ VR
1
The leakage current drops rapidly below the value corre-
sponding to the rated voltage VR when reduced voltages are
applied. The effect of voltage derating on the leakage
current is shown in the graph. E
NG
This will also give a significant increase in reliability for any RA
L
CA
application. See Section 3 for details. PI
TY
1.5.4 Ripple current 0.1
0.01
0 20 40 60 80 100
% OF RATED VOLTAGE (VR)
24
Technical Summary and
Application Guidelines
SECTION 2:
AC OPERATION — RIPPLE VOLTAGE AND RIPPLE CURRENT
Î
+25 1.0
P max S 0.09 +85 0.6
E (max) = Z W 0.105 +125 0.4
R
where Pmax is the maximum permissible ripple voltage as TAA – Hermetically Sealed Axial
listed for the product under consideration (see table). Temperature
Case Max. power
However, care must be taken to ensure that: size dissipation (W) derating factors
1. The DC working voltage of the capacitor must not be A 0.09 Temp. °C Factor
exceeded by the sum of the positive peak of the B 0.10 +20 1.0
applied AC voltage and the DC bias voltage. C 0.125 +85 0.9
2. The sum of the applied DC bias voltage and the negative D 0.18 +125 0.4
peak of the AC voltage must not allow a voltage reversal
in excess of that defined in the sector, ‘Reverse Voltage’. TAP – Resin Dipped Radial
Case Max. power Temperature
size dissipation (W) derating factors
2.3 MAXIMUM PERMISSIBLE POWER
A 0.045 Temp. °C Factor
DISSIPATION (WATTS) @ 25°C B 0.05 +25 1.0
The maximum power dissipation at 25°C has been calculated C 0.055
+85 0.4
for the various series and are shown in Section 2.4, together D 0.06
E 0.065 +125 0.09
with temperature derating factors up to 125°C.
F 0.075
For leaded components the values are calculated for parts G 0.08
supported in air by their leads (free space dissipation). H 0.085
The ripple ratings are set by defining the maximum tempera- J 0.09
ture rise to be allowed under worst case conditions, i.e., K 0.1
L 0.11
with resistive losses at their maximum limit. This differential
M/N 0.12
is normally 10°C at room temperature dropping to 2°C at P 0.13
125°C. In application circuit layout, thermal management, R 0.14
available ventilation, and signal waveform may significantly
25
Technical Summary and
Application Guidelines
SECTION 3:
RELIABILITY AND CALCULATION OF FAILURE RATE
3.1 STEADY-STATE
Tantalum Dielectric has essentially no wear out mechanism Voltage Correction Factor
and in certain circumstances is capable of limited self
healing, random failures can occur in operation. The failure 1.0000
rate of Tantalum capacitors will decrease with time and not
increase as with other electrolytic capacitors and other
electronic components. 0.1000
Correction Factor
0.0100
Infant
Mortalities 0.0010
0.0001
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Applied Voltage / Rated Voltage
F = FU x FT x FR x FB
where FU is a correction factor due to operating voltage/ 10.0
Correction Factor
voltage derating
FT is a correction factor due to operating
temperature 1.0
26
Technical Summary and
Application Guidelines
Circuit Impedance 3.2 DYNAMIC
All solid tantalum capacitors require current limiting As stated in Section 1.2.4, the solid Tantalum capacitor has
resistance to protect the dielectric from surges. A series a limited ability to withstand voltage and current surges.
resistor is recommended for this purpose. A lower circuit Such current surges can cause a capacitor to fail.
impedance may cause an increase in failure rate, especially The expected failure rate cannot be calculated by a simple
at temperatures higher than 20°C. An inductive low imped- formula as in the case of steady-state reliability. The two
ance circuit may apply voltage surges to the capacitor and parameters under the control of the circuit design engineer
similarly a non-inductive circuit may apply current surges known to reduce the incidence of failures are derating and
to the capacitor, causing localized over-heating and failure. series resistance.The table below summarizes the results of
The recommended impedance is 1Ω per volt. Where this is trials carried out at AVX with a piece of equipment which
not feasible, equivalent voltage derating should be used has very low series resistance and applied no derating. So
(See MIL HANDBOOK 217E). Table I shows the correction that the capacitor was tested at its rated voltage.
factor, FR, for increasing series resistance.
27
Technical Summary and
Application Guidelines
A commonly held misconception is that the leakage current An added bonus of increasing the derating applied in a
of a Tantalum capacitor can predict the number of failures circuit, to improve the ability of the capacitor to withstand
which will be seen on a surge screen. This can be disproved surge conditions, is that the steady-state reliability is
by the results of an experiment carried out at AVX on 47µF improved by up to an order. Consider the example of a
10V surface mount capacitors with different leakage 6.3 volt capacitor being used on a 5 volt rail. The steady-
currents. The results are summarized in the table below. state reliability of a Tantalum capacitor is affected by three
parameters; temperature, series resistance and voltage
Leakage Current vs Number of Surge Failures derating. Assuming 40°C operation and 0.1Ω/volt of series
Number tested Number failed surge resistance, the scaling factors for temperature and series
Standard leakage range 10,000 25 resistance will both be 0.05 [see Section 3.1]. The derating
0.1 µA to 1µA factor will be 0.15. The capacitors reliability will therefore be
Over Catalog limit 10,000 26 Failure rate = FU x FT x FR x 1%/1000 hours
5µA to 50µA = 0.15 x 0.05 x 1 x 1%/1000 hours
Classified Short Circuit 10,000 25 = 7.5% x 10-3/hours
50µA to 500µA If a 10 volt capacitor was used instead, the new scaling factor
Again, it must be remembered that these results were would be 0.017, thus the steady-state reliability would be
derived from a highly accelerated surge test machine, Failure rate = FU x FT x FR x 1%/1000 hours
and failure rates in the low ppm are more likely with the end = 0.017 x 0.05 x 1 x 1%/1000 hours
customer. = 8.5% x 10-4/ 1000 hours
So there is an order improvement in the capacitors steady-
AVX recommended derating table
state reliability.
Voltage Rail Working Cap Voltage
3.3 6.3
3.3 RELIABILITY TESTING
5 10
10 20
AVX performs extensive life testing on tantalum capacitors.
12 25
■ 2,000 hour tests as part of our regular Quality Assurance
Program.
15 35
Test conditions:
≥24 Series Combinations (11)
■ 85°C/rated voltage/circuit impedance of 3Ω max.
For further details on surge in Tantalum capacitors refer ■ 125°C/0.67 x rated voltage/circuit impedance of 3Ω max.
to J.A. Gill’s paper “Surge in Solid Tantalum Capacitors”, 3.4 Mode of Failure
available from AVX offices worldwide. This is normally an increase in leakage current which ultimately
becomes a short circuit.
28
Technical Summary and
Application Guidelines
SECTION 4:
APPLICATION GUIDELINES FOR TANTALUM CAPACITORS
270
260 Dangerous Range
250
Temperature 240
( o C)
230 Allowable Range
220 with Care
210 Allowable Range
with Preheat
200
0 2 4 6 8 10 12
Soldering Time (secs.)
SECTION 5:
MECHANICAL AND THERMAL PROPERTIES, LEADED CAPACITORS
29
Technical Summary and
Application Guidelines
QUESTIONS AND ANSWERS The two resistors are used to ensure that the leakage
currents of the capacitors does not affect the circuit
Some commonly asked questions regarding Tantalum reliability, by ensuring that all the capacitors have half the
Capacitors: working voltage across them.
Question: If I use several tantalum capacitors in serial/ Question: What are the advantages of tantalum over other
parallel combinations, how can I ensure equal current and capacitor technologies?
voltage sharing?
Answer:
Answer: Connecting two or more capacitors in series
and parallel combinations allows almost any value and 1. Tantalums have high volumetric efficiency.
rating to be constructed for use in an application. 2. Electrical performance over temperature is very stable.
For example, a capacitance of more than 60µF is required in 3. They have a wide operating temperature range -55
a circuit for stable operation. The working voltage rail is 24 degrees C to +125 degrees C.
Volts dc with a superimposed ripple of 1.5 Volts at 120 Hz. 4. They have better frequency characteristics than
The maximum voltage seen by the capacitor is V dc + aluminum electrolytics.
Vac=25.5V 5. No wear out mechanism. Because of their construction,
Applying the 50% derate rule tells us that a 50V capacitor solid tantalum capacitors do not degrade in perfor-
is required. mance or reliability over time.
Connecting two 25V rated capacitors in series will Question: If the part is rated as a 25 volt part and you have
give the required capacitance voltage rating, but the current surged it, why can’t I use it at 25 volts in a low
effective capacitance will be halved, so for greater than impedance circuit?
Answer: The high volumetric efficiency obtained using tan-
talum technology is accomplished by using an extremely
thin film of tantalum pentoxide as the dielectric. Even an
➡
33µF
16.5µF application of the relatively low voltage of 25 volts will pro-
25V duce a large field strength as seen by the dielectric. As a
50V result of this, derating has a significant impact on reliability
33µF as described under the reliability section. The following
25V example uses a 22 microfarad capacitor rated at 25 volts to
illustrate the point. The equation for determining the amount
60µF, four such series combinations are required, as of surface area for a capacitor is as follows:
shown.
C = ( (E) (E ) (A) ) / d
°
A = ( (C) (d) ) /( (E )(E) )
°
A = ( (22 x 10-6) (170 x 10-9) ) / ( (8.85 x 10-12) (27) )
33µF
25V
➡ 66µF
50V
A = 0.015 square meters (150 square centimeters)
Where C = Capacitance in farads
A = Dielectric (Electrode) Surface Area (m2)
d = Dielectric thickness (Space between dielectric) (m)
In order to ensure reliable operation, the capacitors should E = Dielectric constant (27 for tantalum)
be connected as shown below to allow current sharing of
E°= Dielectric Constant relative to a vacuum
the ac noise and ripple signals. This prevents any one
(8.855 x 10-12 Farads x m-1)
capacitor heating more than its neighbors and thus being
the weak link in the chain. To compute the field voltage potential felt by the dielectric
we use the following logic.
+
• • Dielectric formation potential = Formation Ratio x
100K Working Voltage
• •• • = 4 x 25
100K Formation Potential = 100 volts
• •• • Dielectric (Ta2O5) Thickness (d) is 1.7 x 10-9 Meters Per Volt
100K d = 0.17 µ meters
Electric Field Strength = Working Voltage / d
= (25 / 0.17 µ meters)
= 147 Kilovolts per millimeter
= 147 Megavolts per meter
30
Technical Summary and
Application Guidelines
QUESTIONS AND ANSWERS
No matter how pure the raw tantalum powder or the preci- Question: I have read that manufacturers recommend a
sion of processing, there will always be impurity sites in the series resistance of 0.1 ohm per working volt. You suggest
dielectric. We attempt to stress these sites in the factory we use 1 ohm per volt in a low impedance circuit. Why?
with overvoltage surges, and elevated temperature burn in Answer: We are talking about two very different sets of circuit
so that components will fail in the factory and not in your conditions for those recommendations. The 0.1 ohm per volt
product. Unfortunately, within this large area of tantalum recommendation is for steady-state conditions. This level of
pentoxide, impurity sites will exist in all capacitors. To mini- resistance is used as a basis for the series resistance variable
mize the possibility of providing enough activation energy for in a 1% / 1000 hours 60% confidence level reference. This
these impurity sites to turn from an amorphous state to a is what steady-state life tests are based on. The 1 ohm per
crystalline state that will conduct energy, series resistance volt is recommended for dynamic conditions which include
and derating is recommended. By reducing the electric field current in-rush applications such as inputs to power supply
within the anode at these sites, the tantalum capacitor has circuits. In many power supply topologies where the di / dt
increased reliability. Tantalums differ from other electrolytics through the capacitor(s) is limited, (such as most implementa-
in that charge transients are carried by electronic conduc- tions of buck (current mode), forward converter, and flyback),
tion rather than absorption of ions. the requirement for series resistance is decreased.
Question: What negative transients can Solid Tantalum Question: How long is the shelf life for a tantalum capacitor?
Capacitors operate under?
Answer: Solid tantalum capacitors have no limitation on
Answer: The reverse voltage ratings are designed to cover shelf life. The dielectric is stable and no reformation is
exceptional conditions of small level excursions into incor- required. The only factors that affect future performance of
rect polarity. The values quoted are not intended to cover the capacitors would be high humidity conditions and
continuous reverse operation. The peak reverse voltage extreme storage temperatures. Solderability of solder coated
applied to the capacitor must not exceed: surfaces may be affected by storage in excess of one year
10% of rated DC working voltage to a maximum of under temperatures greater than 40 degrees C or humidities
1 volt at 25 degrees C. greater than 80% relative humidity. Terminations should be
3% of rated DC working voltage to a maximum of 0.5 checked for solderability in the event an oxidation develops
volt at 85 degrees C. on the solder plating.
1% of category DC working voltage to a maximum of
0.1 volt at 125 C.
31
Technical Publications
1. Steve Warden and John Gill, “Application Guidelines 15. R.W. Franklin, “Equivalent Series Resistance of
on IR Reflow of Surface Mount Solid Tantalum Tantalum Capacitors,” AVX Ltd.
Capacitors.” 16. John Stroud, “Molded Surface Mount Tantalum
2. John Gill, “Glossary of Terms used in the Tantalum Capacitors vs Conformally Coated Capacitors,”
Industry.” AVX Corporation, Tantalum Division
3. R.W. Franklin, “Over-Heating in Failed Tantalum 17. Chris Reynolds, “Reliability Management of Tantalum
Capacitors,” AVX Ltd. Capacitors,” AVX Tantalum Corporation
4. R.W. Franklin, “Upgraded Surge Performance of 18. R.W. Franklin, “Ripple Rating of Tantalum Chip
Tantalum Capacitors,” Electronic Engineering 1985 Capacitors,” AVX Ltd.
5. R.W. Franklin, “Screening beats surge threat,” 19. Chris Reynolds, “Setting Standard Sizes for Tantalum
Electronics Manufacture & Test, June 1985 Chips,” AVX Corporation
6. AVX Surface Mounting Guide 20. John Gill, “Surge In Solid Tantalum Capacitors,”
7. Ian Salisbury, “Thermal Management of Surface AVX Ltd.
Mounted Tantalum Capacitors,” AVX 21. David Mattingly, “Increasing Reliability of SMD
8. John Gill, “Investigation into the Effects of Connecting Tantalum Capacitors in Low Impedance
Tantalum Capacitors in Series,” AVX Applications,” AVX Corporation
9. Ian Salisbury, “Analysis of Fusing Technology for 22. John Gill, “Basic Tantalum Technology,” AVX Ltd.
Tantalum Capacitors,” AVX-Kyocera Group Company 23. Ian Salisbury, “Solder Update Reflow Mounting
10. R.W. Franklin, “Analysis of Solid Tantalum Capacitor TACmicrochip Tantalum Capacitor,” AVX Ltd.
Leakage Current,” AVX Ltd. 24. Ian Salisbury, “New Tantalum Capacitor Design for
11. R.W. Franklin, “An Exploration of Leakage Current,” 0603 Size,” AVX Ltd.
AVX, Ltd. 25. John Gill, “Capacitor Technology Comparison,”
12. William A. Millman, “Application Specific SMD AVX Ltd.
Tantalum Capacitors,” Technical Operations, AVX 26. Scott Chiang, “High Performance CPU Capacitor
Ltd. Requirements, how AVX can help,” AVX Kyocera
13. R.W. Franklin, “Capacitance Tolerances for Solid Taiwan
Tantalum Capacitors,” AVX Ltd. 27. John Gill and Ian Bishop, "Reverse Voltage Behavior
14. Arch G. Martin, “Decoupling Basics,” AVX of Solid Tantalum Capacitors."
Corporation
NOTICE: Specifications are subject to change without notice. Contact your nearest AVX Sales Office for the latest specifications. All statements, information and
data given herein are believed to be accurate and reliable, but are presented without guarantee, warranty, or responsibility of any kind, expressed or implied.
Statements or suggestions concerning possible use of our products are made without representation or warranty that any such use is free of patent infringement
and are not recommendations to infringe any patent. The user should not assume that all safety measures are indicated or that other measures may not be required.
Specifications are typical and may not apply to all applications.
32
USA EUROPE ASIA-PACIFIC
http://www.avxcorp.com S-TLG13M599-C
TIP31, TIP31A, TIP31B, TIP31C
NPN SILICON POWER TRANSISTORS
Copyright © 1997, Power Innovations Limited, UK JULY 1968 - REVISED MARCH 1997
PRODUCT INFORMATION
Information is current as of publication date. Products conform to specifications in accordance
with the terms of Power Innovations standard warranty. Production processing does not
necessarily include testing of all parameters.
1
TIP31, TIP31A, TIP31B, TIP31C
NPN SILICON POWER TRANSISTORS
JULY 1968 - REVISED MARCH 1997
thermal characteristics
PARAMETER MIN TYP MAX UNIT
RθJC Junction to case thermal resistance 3.125 °C/W
RθJA Junction to free air thermal resistance 62.5 °C/W
PRODUCT INFORMATION
2
TIP31, TIP31A, TIP31B, TIP31C
NPN SILICON POWER TRANSISTORS
JULY 1968 - REVISED MARCH 1997
TYPICAL CHARACTERISTICS
1·0
100
0·1
IC = 100 mA
IC = 300 mA
IC = 1 A
IC = 3 A
10 0·01
0·001 0·01 0·1 1·0 10 0·1 1·0 10 100 1000
IC - Collector Current - A IB - Base Current - mA
Figure 1. Figure 2.
BASE-EMITTER VOLTAGE
vs
COLLECTOR CURRENT
TCS631AC
1·0
VCE = 4 V
TC = 25°C
VBE - Base-Emitter Voltage - V
0·9
0·8
0·7
0·6
0·5
0·01 0·1 1·0 10
IC - Collector Current - A
Figure 3.
PRODUCT INFORMATION
3
TIP31, TIP31A, TIP31B, TIP31C
NPN SILICON POWER TRANSISTORS
JULY 1968 - REVISED MARCH 1997
MAXIMUM FORWARD-BIAS
SAFE OPERATING AREA
SAS631AA
100
tp = 300 µs, d = 0.1 = 10%
tp = 1 ms, d = 0.1 = 10%
tp = 10 ms, d = 0.1 = 10%
DC Operation
10
IC - Collector Current - A
1·0
0·1
TIP31
TIP31A
TIP31B
TIP31C
0·01
1·0 10 100 1000
VCE - Collector-Emitter Voltage - V
Figure 4.
THERMAL INFORMATION
40
30
20
10
0
0 25 50 75 100 125 150
TC - Case Temperature - °C
Figure 5.
PRODUCT INFORMATION
4
TIP31, TIP31A, TIP31B, TIP31C
NPN SILICON POWER TRANSISTORS
JULY 1968 - REVISED MARCH 1997
MECHANICAL DATA
TO-220
3-pin plastic flange-mount package
This single-in-line package consists of a circuit mounted on a lead frame and encapsulated within a plastic
compound. The compound will withstand soldering temperature with no deformation, and circuit performance
characteristics will remain stable when operated in high humidity conditions. Leads require no additional
cleaning or processing when used in soldered assembly.
TO220
4,70
4,20
6,6
6,0
15,90
14,55
see Note C
6,1
3,5
14,1
1,70 12,7
0,97 1,07
0,61
1 2 3
2,74 0,64
2,34 0,41
5,28 2,90
4,88 2,40
VERSION 1 VERSION 2
NOTES: A. The centre pin is in electrical contact with the mounting tab. MDXXBE
B. Mounting tab corner profile according to package version.
C. Typical fixing hole centre stand off height according to package version.
Version 1, 18.0 mm. Version 2, 17.6 mm.
PRODUCT INFORMATION
5
TIP31, TIP31A, TIP31B, TIP31C
NPN SILICON POWER TRANSISTORS
JULY 1968 - REVISED MARCH 1997
IMPORTANT NOTICE
Power Innovations Limited (PI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to verify, before placing orders, that the
information being relied on is current.
PI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with PI's standard warranty. Testing and other quality control techniques are utilized to the extent PI
deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except as mandated by government requirements.
PI accepts no liability for applications assistance, customer product design, software performance, or infringement
of patents or services described herein. Nor is any license, either express or implied, granted under any patent
right, copyright, design right, or other intellectual property right of PI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.
PRODUCT INFORMATION
6
This datasheet has been download from:
www.datasheetcatalog.com