Lab. de Diseño de Circuitos y Sistemas Electrónicos. 4º Ing.

Electrónica

PRÁCTICA 2. Programación de un sumador-restador de 3 bits.

1. Introducción.

Para la realización de cálculos binarios, es imprescindible la utilización de elementos capaces de realizar

operaciones matemáticas. Las unidades aritmético-lógicas (ALU) contienen esencialmente capacidades
aritméticas de suma y multiplicación. En esta práctica se desea diseñar un módulo sumador-restador de 3 bits
sin signo de acarreo encadenado basado en un sumador de un bit con acarreo de entrada y salida. Este
sumador de un bit se puede enlazar de modo que se puede construir un sumador de tantos bits como se desee
de forma rápida y sencilla. La estructura de nivel superior de este sumador es la que se muestra en la figura
siguiente

Figura 1. Esquema de un sumador-restador de 3 bits.

Cada módulo de 1 bit posee cuatro entradas (A, B, CIN y ADDSUB) y dos salidas (S, COUT). La
entrada ADDSUB controla el resultado de la salida, efectuando la suma si su nivel lógico es ‘1’, y la resta si
su nivel lógico es ‘0’, en cualquier caso, la operación se realiza entre los operandos A, B y CIN. Como
ejemplo de funcionamiento, si A=3, B=6, el resultado de la suma es 9, y dado que la resta siempre se realiza
como A-B, el resultado es: D=13. Un ejemplo de simulación es:

Figura 2. Simulación de las operaciones del sumador-restador de 3 bits.

2. Objetivo de la práctica.

En esta práctica vamos a realizar la implementación sobre un dispositivo lógico programable, en este caso
sobre una FPGA Xilinx de la familia VirtexE modelo XCV100EPQ240-6. Los pasos a realizar son:

Profesores: Alfredo Rosado. Manuel Bataller. 1

Lab. de Diseño de Circuitos y Sistemas Electrónicos. 4º Ing. Electrónica

1. Diseño del módulo sumador-restador de un bit.

2. Simulación del módulo sumador-restador de un bit.
3. Creación de un elemento de librería para obtener un símbolo capaz de ser utilizado como un elemento
más.
4. Simulación funcional del módulo de 3 bits, probando los diversos modos de operación, es decir, en
modo suma, en modo resta, y con varias combinaciones de entrada para A y B.
5. Generación de un módulo de nivel superior donde se realice una decodificación de las salidas para ser
mostradas en un display de 7 segmentos, en este nivel también se incluirá una señal de entrada que
permita visualizar un nuevo resultado de la suma de los elementos de entrada cada vez que ocurre el
paso de estado bajo a alto para esta entrada. Se incluye una entrada de reset por la que cuando se
activa, la salida toma un valor cero.
6. Simular el sistema total.

El aspecto del dispositivo a nivel de entradas y salidas externas es el siguiente:

Figura 3. Símbolo completo con entradas y salidas del sistema fina l a diseñar.

4. Diseño y simulación.

Primeramente se debe diseñar el sumador-restador de un bit, una vez simulado, se genera un elemento de
librería para el mismo. A continuación se diseña el sistema sumador-restador de 3 bit empleando el símbolo
de librería que se acaba de crear. Una vez diseñado y simulado correctamente se genera otro símbolo de
librería para el módulo de 3 bits. Como se desea visualizar el resultado en un display de 7 segmentos, se debe
incluir en el proyecto el fichero hex2led.vhd proporcionado. Para este fichero VHDL, también se genera el
símbolo esquemático. En nuevo esquema se incluye el módulo de 3 bits, el decodificador a 7 segmentos y la
lógica necesaria para hacer que el sistema sólo actualice el cálculo cuando se le proporcione la orden desde
la entrada “Actualiza”. Se simula el sistema completo y se comprueba que funciona correctamente.

NOTA: Si se necesita poner señales de entrada a nivel lógico cero ó uno, en la librería de símbolos se
dispone de los símbolos GND y VCC respectivamente.

5. Implementación.

Una vez simulado, para que el diseño disponga de las entradas y salidas que corresponden a la ubicación
de los interruptores y LED que existen en la placa, es necesario conocer el número de patilla donde cada uno
se ubica. En los anexos a esta memoria se muestran unos esquemas y una descripción de la placa donde,
junto con la exploración física de la placa disponible en el laboratorio, debéis ser capaces de encontrar el
número de patilla que demos asignar a cada entrada y salida del diseño.

Escribe a continuación la asignación de cada patilla:

NET "suma<6>" LOC = ;
NET "suma<5>" LOC = ;
NET "suma<4>" LOC = ;
NET "suma<3>" LOC = ;
Profesores: Alfredo Rosado. Manuel Bataller. 2
Lab. de Diseño de Circuitos y Sistemas Electrónicos. 4º Ing. Electrónica

NET "suma<2>" LOC = ;

NET "suma<1>" LOC = ;
NET "suma<0>" LOC = ;
NET "reset" LOC = ;
NET "a<2>" LOC = ;
NET "a<1>" LOC = ;
NET "a<0>" LOC = ;
NET "addsub" LOC = ;
NET "actualiza" LOC = ;
NET "b<2>" LOC = ;
NET "b<1>" LOC = ;
NET "b<0>" LOC = ;

Para realizar la asignación de patillas es necesario que en la ventana de fuentes añadamos una nueva
fuente (New Source), en este caso del tipo User Constraint File. Una vez creada, aparece un fichero con
extensión .ucf, que teniéndolo seleccionado ejecutaremos la opción de la ventana de procesos llamada User
Constraints -> Assign Package Pins. Esta opción nos abre el editor PACE, donde tenemos las entradas y
salidas que podemos llevar a la patilla a asignar.

Figura 4. Imagen de PACE, editor de restricciones, empleado en este caso para asignar patillas
en el dispositivo FPGA a emplear.

Una vez realizada la asignación de patillas ya podremos proceder a la implementación del sistema. Para
ello, ejecutaremos la opción Implement Design que automáticamente realizará el proceso de asignar los
recursos lógicos. Si el proceso finaliza correctamente, visualizar los informes y buscar la información que se
solicita a continuación:

Number of Slices: …………… out of 1,200

Number of 4 input LUTs: …………… out of 2,400
Number of bonded IOBs: …………… out of 158
IOB Flip Flops: …………………………

6. Programación de la placa.

Para generar el fichero que sirve para descargar el programa en la placa se ejecuta la acción Generate
Programming File.

Profesores: Alfredo Rosado. Manuel Bataller. 3

Lab. de Diseño de Circuitos y Sistemas Electrónicos. 4º Ing. Electrónica

Figura 5. Ventanas de fuentes y procesos para el diseño de esta sesión.

Una vez finalizado el proceso estaremos en disposición de encender la fuente de alimentación de la placa
para posteriormente entrar dentro del programa iMPACT que es el encargado de configurar el proceso de
programación.

Al arrancar este programa aparece un asistente que solicita información acerca del tipo de programación que
se desea realizar. Las opciones que se deben elegir son:

Figura 6. Opciones a seleccionar en iMPACT para programar el dispositivo.

El proceso de reconocimiento automático debe reconocer dos dispositivos de programación, una memoria
EEPROM XC18v01 que no vamos a emplear y la FPGA, para ello, nos pedirá el fichero de programación de
cada dispositivo, para el caso de la memoria, le decimos que lo ignore (Bypass), y para el caso de la FPGA
procederemos a indicarle el fichero .bit que se nos ha generado en la carpeta de nuestro proyecto.

Finalmente, el aspecto de iMPACT es el que sigue:

Profesores: Alfredo Rosado. Manuel Bataller. 4

Lab. de Diseño de Circuitos y Sistemas Electrónicos. 4º Ing. Electrónica

Figura 7. Ventana principal de iMPACT.

Se selecciona la FPGA (se selecciona en un color verde), y se ejecuta la opción Operations -> Program,
procediendo a la verificación de la misma.

Profesores: Alfredo Rosado. Manuel Bataller. 5

 Xilinx® Virtex™ -E Evaluation Kit

November 28, 2000 (Version 1.1) DRAFT Advance Product Specification

Features The Virtex-E device is located in the center of the board. It

can be configured via a JTAG download or from the on
• FPGA
board configuration PROM. The configuration PROM is
Ÿ Xilinx® Virtex-E XCV100E-6PQ240C
also programmable through the JTAG cable. Over 85 IO
• SPROM
signals are connected from the FPGA to 0.1 header
Ÿ Xilinx® XC18V01SO20C
connectors for user connections. Other IO are connected
• Board I/O Connectors to 8 LED, 8 dip switches, Two push buttons, RS-232 line
Ÿ Two 50-pin, 0.1 Header connector
driver/receiver, and a digital thermometer.
Ÿ Pads for three MICTOR connectors
Ÿ Pads for one 140 pin General Purpose I/O
interface
• Power
Ÿ +5.0 Power Connector
Ÿ +3.3 V Regulated Supply
Ÿ +1.8 V Regulated Supply
Ÿ Full Bypass Capacitance
• Communication
Ÿ RS232 Serial Port
• Configuration
Ÿ JTAG Header Connector
Ÿ In-System Programmable PROM
Ÿ JTAG Download Cable
• Miscellaneous
Ÿ 8 DIP switches Demo Application.
Ÿ 2 Push-buttons, The board is supplied with complete VHDL source code
Ÿ Dual Digit 7 Segment LED, right hand decimal that:
Ÿ Infrared Transceiver 1) Sequences LEDs
Ÿ 8 LEDs 2) Reads Dip Switches/push buttons
Ÿ 40 MHz Oscillator 3) Senses Temperature and displays value on
Ÿ Digital Thermometer dual 7 segment LED
• Demonstration application (Source VHDL) 4) Transmits startup message through RS-232
Ÿ Simple RS232 connector.
Ÿ Digital Thermometer 5) Echoes RS-232 commands. (Serial cable not
Ÿ LED Patterns included)
Description
The Evaluation Virtex-E Kit is used by engineers as a
platform to test FPGA designs that are targeted to the
Xilinx Virtex-E device. It is also a great tool for beginners Ordering Information
to get aquatinted with FPGAs and VHDL. The following table lists the development system part
numbers and available software options.
Internet Link at http://www.em.avnet.com/.

Table 1 Evaluation Virtex-E Board

Part Number Hardware
ADS-XLX-VE-EVL Xilinx Virtex-E Evaluation Kit

November 28, 2000 (Version 1.1) Literature # ADS-001205 Page - 1

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All other trademarks and registered trademarks are the property of their respective owners.
Xilinx Virtex-E Evaluation Kit

ADS Evaluation Virtex-E Board Virtex-E FPGA

This section provides information basic to the design of The Virtex-E Field-Programmable Gate Array device (U1)
Evaluation Virtex-E Board board. utilized in this design is the 100+K-system gate device
(XCV100E) in a PQ240 package.

FPGA Configuration
Configuration information is provided from two sources;
the JTAG Connector (JTAG0), and configuration PROM.

Table 2 JTAG Connector

Signal Name JTAG Connector Pin #
VCC 1
TDI 2
TMS 3
TCK 4
Power TDO 5
The majority of the design is powered at 3.3V with the GND 6
Virtex-E FPGA core powered at 1.8V. The board should
be powered by a 5-volt bench supply. The 3.3V is derived Jumpers JP1, JP2 and JP3 select the configuration mode of
via a linear regulator. A linear regulator from the 3.3V the Virtex. The following table shows the jumper setting
provides the 1.8V Xilinx core voltage. A barrel connector needed for each mode.
J3 (RAPC712) is provided on the board for lab supply
connections. The center tap is +5.0 volts and the outer is Table 3 Mode Select
GND. Note: The lab supply should be regulated at 5.0
volts. While current requirements are dependent on the Configuration Pull- JP3/M2 JP2/M1 JP1/M0
Mode ups
user application, it is suggested to limit your supply to 1.5
Master-serial No OFF /LOW OFF /LOW OFF /LOW
amps on initial power up. Boundary-scan No ON /HIGH OFF /LOW ON /HIGH
SelectMAP No ON /HIGH ON /HIGH OFF /LOW
φ0.098 in
Slave-serial No ON /HIGH ON /HIGH ON /HIGH
φ0.25 in
pin diameter housing diameter Master-serial Yes ON /HIGH OFF /LOW OFF /LOW
Boundary-scan Yes OFF /LOW OFF /LOW ON /HIGH
SelectMAP Yes OFF /LOW ON /HIGH OFF /LOW
Slave-serial Yes OFF /LOW ON /HIGH ON /HIGH

The LED D1 indicates the output level of the DONE pin of

the Virtex-E device. It will illuminate when the Virtex-E
configuration is complete.
+5.0 Volts GND

System Clock
Printed Circuit Board An oscillator socket clock output is connected to the
Virtex-E device. U5 is connected to Global Clock Input #0
The Evaluation Virtex-E Board printed circuit board is an (PQ240 pin #P92), The U5 socket is populated with a 40
6-layer board with four signal layers, a full 3.3V power MHz oscillator.
plane incorporating an isolated 1.8V mini-plane, and full
ground plane. The board stack-up layers 1 through 6 is:
1) ”Component side”/signal
Asynchronous (RS232) Communication
2) Ground Plane Interface
3) Signal The ADM3222 device provides level translation for a
4) Signal single RS232 interface (DB9 connector). The second
5) Power: 3.3V and 1.8V translation port on the device is terminated and unused.
6) ”Solder side”/signal

Page - 2 Literature # ADS-001205 November 28, 2000 (Version 1.1)

©2000, Avnet, Inc. All rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc.
All other trademarks and registered trademarks are the property of their respective owners.
 Xilinx Virtex-E Evaluation Kit

Table 4 RS232 Interface Signals

Table 9 Dual Segmented LED Signals
RS232 SIGNAL Virtex-E PIN #
R1OUT P216 LED Virtex-E PIN #
T1IN P217 A1 P221
EN_N P218 B1 P222
SD_N P219
C1 P223
D1 P224
Table 5 RS232 Connector Pinout E1 P228
Signal Name P2 (DB9) connector Pin #
F1 P229
TX out 2 G1 P230
RX in 3 Dp1 P231
GND 5 A2 P234
B2 P235
C2 P236
Miscellaneous D2 P237
The “Miscellaneous” interfaces on the Virtex-E board E2 P238
consist of a single 8-position DIP switch (8-individual F2 P186
SPST switches), 8 LEDs, and two push-button switches. G2 P187
Dp2 P188
Table 6 Dip Switch Signals
DIP SW Virtex-E PIN # Table 10 Infrared Signals
#1 P194
LED Virtex-E PIN #
#2 P195
#3 P199 TXD P102
#4 P200 RXD P101
#5 P201 SHDN P100
#6 P202
#7 P203
#8 P205 Table 11 Digital Themometer
LED Virtex-E PIN #
CE P160
Table 7 Push Button Switch Signals SCLK P159
BUTTON Virtex-E PIN # SDI P161
SW1 P206 SDO P162
SW2 P208

Table 8 LED Control Signals

LED Virtex-E PIN #
D2 P27
D3 P28
D4 P3
D5 P4
D6 P5
D7 P6
D8 P7
D9 P9

November 28, 2000 (Version 1.1) Literature # ADS-001205 Page - 3

©2000, Avnet, Inc. All rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc.
All other trademarks and registered trademarks are the property of their respective owners.
Xilinx Virtex-E Evaluation Kit

Table 13 GPIO Signals JP6

I/O Signal Headers GPIO CONNECTOR PIN Virtex-E PIN #
Two 50-pin connectors provides 84 Virtex-E I/O lines and #
1 P31
6 ground pins.
2 P33
Table 12 GPIO Signals JP5 3 P34
4 P35
GPIO CONNECTOR PIN Virtex-E PIN # 5 P36
# 6 P38
1 P86 7 P39
2 P84 8 P40
3 P82 9 P41
4 P81 10 P42
5 P80 11 P46
6 P79 12 P47
7 P78 13 P48
8 P74 14 P49
9 P73 15 P50
10 P72 16 P52
11 P71 17 P53
12 P70 18 P54
13 P68 19 P56
14 P67 20 P57
15 P66 21 P10
16 P65 22 P11
17 P64 23 P12
18 P63 24 P13
19 P99 25 P17
20 P97 26 P18
21 P96 27 P19
22 P95 28 P20
23 P94 29 P21
24 P118 30 P23
25 P117 31 P24
26 P115 32 P26
27 P114 33 P128
28 P113 34 P127
29 P111 35 P126
30 P110 36 P125
31 P109 37 P175
32 P108 38 P174
33 P149 39 P173
34 P147 40 P171
35 P144 41 P170
36 P142 42 P169
37 P141 43 Reserved
38 P140 44 Reserved
39 P134 45 Reserved
40 P133 46 Reserved
41 P132 47 Reserved
42 P131 48 GND
43 P130 49 GND
44 Reserved 50 GND
45 Reserved
46 Reserved
47 Reserved
48 GND
49 GND
50 GND

Page - 4 Literature # ADS-001205 November 28, 2000 (Version 1.1)

©2000, Avnet, Inc. All rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc.
All other trademarks and registered trademarks are the property of their respective owners.
 Xilinx Virtex-E Evaluation Kit

Logic Analyzer Connector Table 15 MICTOR J5

Three AMP™ MICTOR connector pads are provided to
Connector PIN # Virtex-E Name
connect to a logic analyzer’s mass termination cable. PIN #
1 N/C N/C
2 N/C N/C
Table 14 MICTOR J4 3 N/C N/C
Connector PIN # Virtex-E Name 4 N/C N/C
PIN # 5 P213* GCK3
1 N/C N/C 6 P89* GCLK1
2 N/C N/C 7 P26 DATA31
3 N/C N/C 8 P52 DATA15
4 N/C N/C 9 P24 DATA30
5 P210* CLK_OUT 10 P50 DATA14
6 P92 OSC 11 P23 DATA29
7 P108 ADDRESS31 12 P49 DATA13
8 P65 ADDRESS15 13 P21 DATA28
9 P109 ADDRESS30 14 P48 DATA12
10 P66 ADDRESS14 15 P20 DATA27
11 P110 ADDRESS29 16 P47 DATA11
12 P67 ADDRESS13 17 P19 DATA26
13 P111 ADDRESS28 18 P46 DATA10
14 P68 ADDRESS12 19 P18 DATA25
15 P113 ADDRESS27 20 P42 DATA9
16 P70 ADDRESS11 21 P17 DATA24
17 P114 ADDRESS26 22 P41 DATA8
18 P71 ADDRESS10 23 P13 DATA23
19 P115 ADDRESS25 24 P40 DATA7
20 P72 ADDRESS9 25 P12 DATA22
21 P117 ADDRESS24 26 P39 DATA6
22 P73 ADDRESS8 27 P11 DATA21
23 P118 ADDRESS23 28 P38 DATA5
24 P74 ADDRESS7 29 P10 DATA20
25 P94 ADDRESS22 30 P36 DATA4
26 P78 ADDRESS6 31 P57 DATA19
27 P95 ADDRESS21 32 P35 DATA3
28 P79 ADDRESS5 33 P56 DATA18
29 P96 ADDRESS20 34 P34 DATA2
30 P80 ADDRESS4 35 P54 DATA17
31 P97 ADDRESS19 36 P33 DATA1
32 P81 ADDRESS3 37 P53 DATA16
33 P99 ADDRESS18 38 P31 DATA0
34 P82 ADDRESS2 39 GND GND
35 P63 ADDRESS17 40 GND GND
36 P84 ADDRESS1 41 GND GND
37 P64 ADDRESS16 42 GND GND
38 P86 ADDRESS0 43 GND GND
39 GND GND
40 GND GND
41 GND GND
42 GND GND
43 GND GND

November 28, 2000 (Version 1.1) Literature # ADS-001205 Page - 5

©2000, Avnet, Inc. All rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc.
All other trademarks and registered trademarks are the property of their respective owners.
Xilinx Virtex-E Evaluation Kit

Table 16 MICTOR J6 Table 17 AvBus Connector P2

Connector PIN # Virtex-E Name Name FPGA Connector PIN # FPGA Name
PIN # PIN # PIN #
1 N/C N/C ADDRESS0 P86 71 1 N/C N/C
2 N/C N/C GND GND 72 2 P84 ADDRESS1
3 N/C N/C ADDRESS3 P81 73 3 P82 ADDRESS3
4 N/C N/C ADDRESS4 P80 74 4 GND GND
5 P210* CLK_OUT GND GND 75 5 P79 ADDRESS5
6 P191* CLK_IN ADDRESS7 P74 76 6 P78 ADDRESS6
7 P178 DOUT ADDRESS8 P73 77 7 GND GND
8 P175 CNTL15 AUX_+3.3V +3.3V 78 8 P72 ADDRESS9
9 P208 SWITCH9 ADDRESS11 P70 79 9 P71 ADDRESS10
10 P125 CNTL14 ADDRESS12 P68 80 10 GND GND
11 P206 SWITCH8 GND GND 81 11 P67 ADDRESS13
12 P126 CNTL13 ADDRESS15 P65 82 12 P66 ADDRESS14
13 P162 TEMP_SDO ADDRESS16 P64 83 13 N/C N/C
14 P127 CNTL12 GND GND 84 14 P63 ADDRESS17
15 P161 TEMP_SDI ADDRESS19 P97 85 15 P99 ADDRESS18
16 P128 CNTL11 ADDRESS20 P96 86 16 GND GND
17 P160 TEMP_CE GND GND 87 17 P95 ADDRESS21
18 P130 CNTL10 ADDRESS23 P118 88 18 P94 ADDRESS22
19 P159 TEMP_SCLK ADDRESS24 P117 89 19 GND GND
20 P131 CNTL9 AUX_+3.3V +3.3V 90 20 P115 ADDRESS25
21 P220 RS232SD_N ADDRESS27 P113 91 21 P114 ADDRESS26
22 P132 CNTL8 ADDRESS28 P111 92 22 GND GND
23 P218 RS232EN_N GND GND 93 23 P110 ADDRESS29
24 P133 CNTL7 ADDRESS31 P108 94 24 P109 ADDRESS30
25 P217 RS232TX DATA0 P31 95 25 N/C N/C
26 P139 CNTL6 GND GND 96 26 P33 DATA1
27 P216 RS232RX DATA3 P35 97 27 P34 DATA2
28 P140 CNTL5 DATA4 P36 98 28 GND GND
29 P169 CNTL20 GND GND 99 29 P38 DATA5
30 P141 CNTL4 DATA7 P40 100 30 P39 DATA6
31 P170 CNTL19 DATA8 P41 101 31 GND GND
32 P142 CNTL3 AUX_+3.3V +3.3V 102 32 P42 DATA9
33 P171 CNTL18 DATA11 P47 103 33 P46 DATA10
34 P144 CNTL2 DATA12 P48 104 34 GND GND
35 P173 CNTL17 GND GND 105 35 P49 DATA13
36 P147 CNTL1 DATA15 P52 106 36 P50 DATA14
37 P174 CNTL16 DATA16 P53 107 37 N/C N/C
38 P149 CNTL0 GND GND 108 38 P54 DATA17
39 GND GND DATA19 P57 109 39 P56 DATA18
40 GND GND DATA20 P10 110 40 GND GND
41 GND GND GND GND 111 41 P11 DATA21
42 GND GND DATA23 P13 112 42 P12 DATA22
43 GND GND DATA24 P17 113 43 GND GND
*Note: A zero ohm resistor may be required to access the AUX_+3.3V +3.3V 114 44 P18 DATA25
noted signals. DATA27 P20 115 45 P19 DATA26
DATA28 P21 116 46 GND GND
GND GND 117 47 P23 DATA29
DATA31 P26 118 48 P24 DATA30
AvBus Connector CNTL0 P149 119 49 N/C N/C
GND GND 120 50 P147 CNTL1
High-density connector pads are located on bottom of the CNTL3 P142 121 51 P144 CNTL2
board. The signals are listed in the following table. CNTL4 P141 122 52 GND GND
GND GND 123 53 P140 CNTL5
CNTL7 P133 124 54 P139 CNTL6
CNTL8 P132 125 55 GND GND
AUX_+3.3V +3.3V 126 56 P131 CNTL9
CNTL11 P128 127 57 P130 CNTL10

Page - 6 Literature # ADS-001205 November 28, 2000 (Version 1.1)

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 Xilinx Virtex-E Evaluation Kit

Name FPGA Connector PIN # FPGA Name 8) Press the Soft Reset button SW1 to reset the
PIN # PIN # board.
CNTL12 P127 128 58 GND GND
Serial Demo
GND GND 129 59 P126 CNTL13
CNTL15 P175 130 60 P125 CNTL14 9) Press the button SW2 to send the startup message.
CNTL16 P174 131 61 N/C N/C 10) The Power up message is displayed on the serial
GND GND 132 62 P173 CNTL17 terminal.
CNTL19 P170 133 63 P171 CNTL18 11) All characters typed should be echoed to the
CNTL20 P169 134 64 GND GND terminal.
GND GND 135 65 P191* CLK_IN
12) Press the Reset button again to “reset” startup
CLK_OUT P210* 136 66 P210* CLK_OUT_FB
message.
TMS ⊕ 137 67 GND GND
AUX_+3.3V +3.3V 138 68 ⊕ TDO LED SCAN
TDI ⊕ 139 69 ⊕ TCK 13) Set the dipswitch S1 dip 1 to ON (rocker up).
TRS ⊕ 140 70 GND GND 14) The LEDs should be blinking such that the
*Note: A zero ohm resistor may be required to access the illuminated led should be scanning back and forth
noted signals. through the LED array.
⊕ Note: Reference Schematic for current JTAG signal UP COUNTER
paths. 15) Set the dipswitch S1 dip 2 to ON (rocker down).
16) The Dual segmented LEDs should be counting
up.
Demonstration Program TEMPERATURE
Supplied with the development system is a demonstration 17) Set the dipswitch S1 dip 1 to OFF (rocker down).
program file that utilizes several devices on the evaluation 18) The LED should now display the temperature in
board. The demonstration program uses the evaluation °C in two’s complement binary. See the following
development board as a standalone platform that is table.
connected to a lab supply and a terminal emulation 19) Set the dipswitch S1 dip 2 to OFF (rocker down).
program. On power up the onboard PROM will configure 20) The Dual segmented LEDs should now display
the FPGA. Upon completion of the configuration the the temperature in °C.
FPGA functionality and input/output signal will activate. 21) Hold your finger on U5 to change the
A start up serial message will be sent to the terminal port temperature.
via the RS-232 connection. The LEDs will display a back
and forth scanning pattern or 8-bit value corresponding to LED Pattern Decimal Value (°C)
the current temperature. The Dual segmented display will (D9..D2)
count up or display the current temperature. 0111 1000 +120C
0001 1001 +25C
Additional Items Needed:
0000 1010 +10C
Ÿ Lab power supply, 5.0 volts at 1.5 amps.
0000 0000 0C
Ÿ Serial Terminal or Terminal Emulator.
Ÿ RS-232 cable 1111 0101 -10C
1110 0110 -25C
Setup: 1100 1001 -55C
1) Attach the lab supply to the power connector on
the Evaluation Board.
2) Attach the serial terminal to the P1 connector of
the Evaluation Board.
3) Set the Serial Terminal to: 8 data bits, 1 stop , No
parity, 9600 baud.
4) Verify jumper are NOT installed on JP1,JP2,and
JP3.
5) Verify JP4 is installed across pins 1 and 2.
Power UP:
6) Apply power to the Evaluation Board.
7) The DONE LED D1 will light on the completion
of the download.
Reset:

November 28, 2000 (Version 1.1) Literature # ADS-001205 Page - 7

©2000, Avnet, Inc. All rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc.
All other trademarks and registered trademarks are the property of their respective owners.
Xilinx Virtex-E Evaluation Kit

Document Source
Relevant Documents XILINX XC18V01 Configuration
Documents relevant to this application are listed in the http://www.xilinx.com/parti
PROM Data Sheet
following table. nfo/ds026.pdf
Analog Devices ADM3222 3V http://www.analog.com/pdf/
Table 18. Relevant Documents and Links RS232 Line Driver/Receiver Data
Sheet
ADM3202_0.pdf
Document Source
XILINX VIRTEX-E FPGA Data http://www.xilinx.com/parti
Sheet
nfo/ds022.pdf

Block Diagram

Dual
RS-232 8-Segment
LED

JTAG Header
8 LEDS

Infrared
XILINX Transceiver
VIRTEX-E

AvBus Board to Board

XCV100E-6PQ240

140 Pin Connector

8 Dip Switches

FPGA

40MHz
3 MICTORs
Header
Header

50 Pin

OSC
50 Pin

2 Push
Digital Buttons XILINX
Thermometer
XC18V01SO20C

Configuration
PROM

Revisions
Version 1.0 Initial Release.
Version 1.1 Fixed typographical errors.

Page - 8 Literature # ADS-001205 November 28, 2000 (Version 1.1)

©2000, Avnet, Inc. All rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc.
All other trademarks and registered trademarks are the property of their respective owners.
 5 4 3 2 1

REV SHEET DESCRIPTION DATE

Mini-Virtex-E Evauation Board A ALL Initial Release 11-OCT-2000

Avnet Design Services

www.em.avnet.com

D D
Function Sheet Number

Lead Sheet 1

FPGA, SPROM 2

Power 3

Mictor and Header Connectors 4

Switch, LED, OSC 5

Daughter Board Connector 6

C C

B B
Copyright 2000, Avnet, Inc. All Rights Reserved.

This material may not bereproduced, distributed, republished, displayed, posted, transmitted or copied in
any form or by any means without the prior written permission of Avnet, Inc. AVNET and the AV logo are
registered trademarks of Avnet, Inc. All trademarks and trade names are the properties of their respective
owners and Avnet, Inc. disclaims any proprietary interest or right in trademarks, service marks and trade
names other than its own.

Avnet is not responsiblefor typographical or other errors or omissions or for direct, indirect, incidental or
consequential damages elatedr to this material or resulting from its use. Avnet makes no warranty or
representation respecting this material, which is provided on an "AS IS" basis. AVNET HEREBY
DISCLAIMS ALL WARRANTIES OR LIABILITY OF ANY KIND WITH RESPECT THERETO, INCLUDING,
WITHOUT LIMITATION, REPRESENTATIONS REGARDING ACCURACY AND COMPLETENESS, ALL
IMPLIED WARRANTIES AND CONDITIONS OF MERCHANTABILITY,SUITABILITY OR FITNESS FOR A
A
PARTICULAR PURPOSE, TITLE AND/OR NON-INFRINGEMENT. This material is not design ed, intended A
or authorized for use inmedical, life support, life sustaining or nuclear applications or applications in which LIT# ADS-001207
the failure of the product could result in personal injury, death or property damage. Any party using or
selling products for use in any suc h applications do so at their sole risk and agree that Avnet is not liable, Avnet, Inc. Design Services Copyright 2000
Title
in whole or inpart, for any claim or damage arising from such use, and agree to fully indemnify, defend and
Mini-Virtex-E Board - Lead Sheet
hold harmless Avnet from and ag ainst any and all claims, damages, loss, cost, expense or liability arising
Size Document Number Rev
out of or in connection with the use or performance of products in such applications. B H394-XLX5-MVE-1002 A

Date: Tuesday, October 17, 2000 Sheet 1 of 6

5 4 3 2 1
 5 4 3 2 1

DATA[0:31] LED[0:7]

FPGA_TDO

FPGA_TDO
CONN_TDO
CONN_TDI
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DATA16
DATA17

DATA18
DATA19

DATA20
DATA21
DATA22
DATA23

DATA24
DATA25
DATA26
DATA27
DATA28
DATA29
DATA30

DATA31
R1

DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9

SP_TDI

SP_TDI
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
CONN_TMS 1 2 TMS
Do Not Populate
R2
CONN_TCK 1 2 TCK
J1 J2

SP_TDO
Do Not Populate

3
MODE2
MODE1
MODE0
3.3V

CF_N

TMS
+1.8V

TCK

Com

Com
A

B
GCK3

240

122
239
183

225
214
198
164

148
137
104
30
31
33
34
35
36
38
39
40
41
42
44
46
47
48
49
50
52
53
54
55
56
57

10
11
12
13
15
17
18
19
20
21
23
24

25
26
27
28

62
58
60
88
77
43
32

16
3
4
5
6
7
9

2
Do Not Populate Do Not Populate
D D

IO_VREF_L54N_Y

IO_VREF_L51N_Y

IO_VREF_L50N_Y

IO_VREF_L60P_Y

IO_VREF_L57P_Y

IO_VREF_L61P_Y
IO_VREF_L55P

IO_VREF_L63N
IO_L52P_YY
IO_L52N_YY

IO_L48P_YY
IO_L48N_YY

IO_L59P_YY
IO_L59N_YY

IO_L56P_YY
IO_L56N_YY
IO_L54P_Y

IO_L53P_Y
IO_L53N_Y

IO_L51P_Y

IO_L50P_Y

IO_L49P_Y
IO_L49N_Y

IO_L61N_Y

IO_L60N_Y

IO_L58P_Y
IO_L58N_Y

IO_L57N_Y

IO_L62P_Y
IO_L62N_Y

PROGRAM
IO_L55N

IO_VREF

IO_VREF

IO_L63P

VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCO

VCCO

VCCO

VCCO

VCCO
VCCO

TCK

TMS
TDI
IO

IO

IO

IO

IO

IO

M2
M1
M0
GCK1 89 212
GCK1 VCCO VCC
GCK1_FB 87 213
ADDRESS0 IO_LVDS_DLL_L40N GCK3
86 215
IO_VREF IO_LVDS_DLL_L6N
ADDRESS[0:31] 85 216 RS232RX JP1
ADDRESS1 VCCO IO_VREF
84 217 RS232TX
ADDRESS2 IO_VREF_L41P IO_L5P_Y MODE0 1
82 218 RS232EN_N
ADDRESS3 IO_L41N IO_VREF_L5N_Y 2
81 220 RS232SD_N R3
ADDRESS4 IO IO_L4P_Y
80 221 SEG1_A 1 2 HEADER 2x1
ADDRESS5 IO IO_L4N_Y
79 222 SEG1_B
ADDRESS6 IO_L42P_YY IO 10K
78 223 SEG1_C
IO_L42N_YY IO_L3P_YY
76 224 SEG1_D JP2
ADDRESS7 VCCO IO_L3N_YY
74 226
ADDRESS8 IO_L43P_YY VCCO MODE1 1
73 228 SEG1_E
ADDRESS9 IO_VREF_L43N_YY IO_L2P_YY 2
72 229 SEG1_F R4
ADDRESS10 IO IO_VREF_L2N_YY 1 2
71 230 SEG1_G HEADER 2x1
ADDRESS11 IO_L44P_YY IO
70 231 SEG1_Dp
ADDRESS12 IO_VREF_L44N_YY IO_VREF 10K
68 232
ADDRESS13 IO_L45P_YY VCCO
67 234 SEG2_A JP3
ADDRESS14 IO_L45N_YY IO_L1P_YY
66 235 SEG2_B
ADDRESS15 IO_VREF_L46P_Y IO_L1N_YY MODE2 1
65 236 SEG2_C
ADDRESS16 IO_L46N_Y IO_VREF_L0P_Y 2
64 237 SEG2_D R5
ADDRESS17 IO_L47P_YY IO_L0N_Y 1 2
63 238 SEG2_E HEADER 2x1
IO_L47N_YY IO
61 10K
VCCO
180
ADDRESS18 VCCO CS_N
99 184
ADDRESS19 IO_L37N_Y IO_CS_L14P_YY WRITE_N
97 185
ADDRESS20 IO_VREF_L38P_Y U1 IO_WRITE_L14N_YY
96 186 SEG2_F
ADDRESS21 IO_L38N_Y IO_L13P
95 187 SEG2_G
ADDRESS22 IO_L39P IO_VREF_L13N
94 188 SEG2_Dp
IO_VREF_L39N IO_L12P_YY VCC VCC
OSC_FB 93 189 R6
IO_LVDS_DLL_L40P IO_L12N_YY
OSC 92 191 1 2 CLK_IN
GCK0 IO_VREF_L11P_YY
90 192 0R0/0805

1
ADDRESS23 VCCO VIRTEX E - PQ240 IO_L11N_YY
118 193
ADDRESS24 IO_L32P_YY IO SWITCH0 NOT POPULATED R8
117 194
IO_L32N_YY IO_VREF_L10P_YY SWITCH1 R7 Do Not Install
C 116 195 C
ADDRESS25 VCCO IO_L10N_YY Do Not Install
115 197
ADDRESS26 IO_VREF VCCO SWITCH2
114 199
ADDRESS27 IO_L33P_YY IO_L9P_YY SWITCH3 CS_N WRITE_N

2
113 200
ADDRESS28 IO_L33N_YY IO_L9N_YY SWITCH4
111 201
IO_VREF_L34P_YY IO

1
ADDRESS29 110 202 SWITCH5
ADDRESS30 IO_L34N_YY IO_L8P_Y SWITCH6 R10
109 203
ADDRESS31 IO IO_DOUT_BUSY_L15P_YY IO_L8N_Y SWITCH7 R9 Do Not Install
108 205
IO_VREF_L35P_YY IO_VREF_L7P_Y SWITCH8 Do Not Install
107 206
IO_DIN_D0_L15N_YY
IO_L35N_YY IO_L7N_Y
105 207 SWITCH[0:9]
VCCO VCCO
IO_VREF_L24N_Y

IO_VREF_L27N_Y

IO_VREF_L28N_Y

IO_VREF_L17P_Y

IO_VREF_L18P_Y

IO_VREF_L21P_Y
SWITCH9
IO_INIT_L31N_YY

2
103 208
IO_D5_L26N_YY

IO_D7_L31P_YY

IO_D2_L19P_YY
IO_L36P_YY IO_VREF

IO_VREF_L22N
IO_VREF_L30P

IO_D1_L18N_Y

IO_D3_L21N_Y
102
IO_D4_L24P_Y

IO_D6_L27P_Y

209
IR_TXD IO_L36N_YY IO_LVDS_DLL_L6P

IO_L19N_YY

IO_L23N_YY
101 210 2 1
IO_L26P_YY

IO_L23P_YY
IR_RXD IO GCK2 CLK_OUT
IO_L25N_Y

IO_L29N_Y

IO_L16N_Y

IO_L17N_Y

IO_L20N_Y
IO_L25P_Y

IO_L28P_Y

IO_L29P_Y

IO_L16P_Y

IO_L20P_Y
100 R11
IO_VREF

IO_VREF

IR_SHDN IO_L37P_Y
IO_L30N

IO_L22P
0R0/0805
VCCO

VCCO

VCCO
DONE

VCCO

VCCO

VCCO
CCLK

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NOT POPULATED
TDO

NOT POPULATED
IO

IO

IO

IO

IO
2 1 CLK_OUT_FB
149
147
146
145
144
142
141
140
139
138
136
134
133
132
131
130
128
127
126
125
124
123
121
120

181
179
178
177
176
175
174
173
171
170
169
168
167
165
163
162
161
160
159
157
156
155
154
153
152
150

233
227

219
211

204
196
190
182
172
166
158
151
143

135
129
119
112
106
R12

98
91
83

75
69
59
51
45
37
29

22

14
8

1
0R0/0805

JTAG_TRS
CNTL10
CNTL11
CNTL12
CNTL13
CNTL14

CNTL15
CNTL16
CNTL17
CNTL18
CNTL19
CNTL20

CONN_TDI
CNTL0
CNTL1

CNTL2
CNTL3
CNTL4
CNTL5
CNTL6

CNTL7
CNTL8
CNTL9

JTAG_TDI
D0

CONN_TMS
CONN_TDO JTAG_TMS
JTAG_TDO
CONN_TCK
CNTL[0:20] JTAG_TCK
FPGA_TDO

TEMP_SCLK
INIT_N

1 DONE

CCLK

TEMP_CE
TEMP_SDI
TEMP_SDO
B B
DOUT
R13
1K
2

D1
QTLP650C-4

VCC

1
R14
4.7K U2 VCC
CCLK 3 18
CLK VCC

1
INIT_N 8 20 C1
DONE RST/OE VCC

2
10 19
CE VCCO 0.1uF
11
D0 GND JTAG Header

2
1
D0/DATA VCC
16
D1
2 13
D2 CEO SP_TDI 1
15
CF_N D3 TMS TMS 2
7 5
D4/CF TMS TCK TCK 3
14 6
D5 TCK FPGA_TDO 4
9 4
D6 TDI SP_TDO 5
12 17
D7 TDO 6

XC1801SO20 R15 JTAG1

1 2
A A
Do Not Populate

Avnet, Inc. Design Services Copyright 2000

Title
Mini-Virtex-E Board - Lead Sheet
Size Document Number Rev
C H394-XLX5-MVE-1002 A

Date: Tuesday, October 17, 2000 Sheet 2 of 6

5 4 3 2 1
 5 4 3 2 1

JP4
AUX+3.3V
HEADER 3
+1.8V

1
2
3
5V 1.8V
J3 U3 L4955V3.3 3.3V
RAPC712 R16

1
Do Not Populate
1 1 3 3.3V VCC R17

1
D IN OUT D
U4 + C2

GND

TAB
2

6 14
IN OUT
1

1
7 13 270K 10% TANB_10uF
IN OUT

2
+ C3 + C4 5 15
EN FB

4
3 16
GND RST
TANC_22uF TANC_22uF

1
C5
2

2
4 18
NC NC

1
8 17 R18
NC NC

Do Not Populate
0.1uF

2
1 20
GND/HS GND/HS
2 19
GND/HS GND/HS
9 12
GND/HS GND/HS

2
10 11
GND/HS GND/HS
TPS76718QPWP

Virtex-E Decoupling Caps

C 0.1 uf per Vccco C
3.3V 47uf per Bank
1

1
C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
2

2
1

1
C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
2

2
B B
1

1
C30 + C31 + C32 + C33 + C34 + C35 + C36 + C37 +

TANC_47uF TANC_47uF TANC_47uF TANC_47uF TANC_47uF TANC_47uF TANC_47uF

TANC_47uF
2

2
Virtex-E Decoupling Caps
0.1uf per Vccint
four 47uF per device
+1.8V
one 470uF per device
1

1
C38 C39 C40 C41 C42 C43 C44 C45
1

1
C51 C52 C53 C54 C46 + C47 + C48 + C49 + C50 +
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
0.1uF 0.1uF 0.1uF 0.1uF TANC_47uF TANC_47uF TANC_47uF TANC_47uF TAND_470uF
2

2
A A

Avnet, Inc. Design Services Copyright 2000

Title
Mini-Virtex-E Board - Power
AVNET, INC. CONFIDENTIAL Size
B
Document Number Rev
A
H394-XLX5-MVE-1002
Date: Tuesday, October 17, 2000 Sheet 3 of 6
5 4 3 2 1
 5 4 3 2 1

ADDRESS[0:31] ADDRESS[0:31]
MICTOR(AMP 2-767004-2)
JP5 J4
ADDRESS0 ADDRESS1 ADDRESS0 38 37 ADDRESS16
ADDRESS2 1 2 ADDRESS3 ADDRESS1 A/D0:0 A/D2:0 ADDRESS17
36 35
ADDRESS4 3 4 ADDRESS5 ADDRESS2 A/D0:1 A/D2:1 ADDRESS18
34 33
ADDRESS6 5 6 ADDRESS7 ADDRESS3 A/D0:2 A/D2:2 ADDRESS19
32 31
ADDRESS8 7 8 ADDRESS9 ADDRESS4 A/D0:3 A/D2:3 ADDRESS20
30 29
ADDRESS10 9 10 ADDRESS11 ADDRESS5 A/D0:4 A/D2:4 ADDRESS21
28 27
D ADDRESS12 11 12 ADDRESS13 ADDRESS6 A/D0:5 A/D2:5 ADDRESS22 D
26 25
ADDRESS14 13 14 ADDRESS15 ADDRESS7 A/D0:6 A/D2:6 ADDRESS23
24 23
ADDRESS16 15 16 ADDRESS17 ADDRESS8 A/D0:7 A/D2:7 ADDRESS24
22 21
ADDRESS18 17 18 ADDRESS19 ADDRESS9 A/D1:0 A/D3:0 ADDRESS25
20 19
ADDRESS20 19 20 ADDRESS21 ADDRESS10 A/D1:1 A/D3:1 ADDRESS26
18 17
ADDRESS22 21 22 ADDRESS23 ADDRESS11 A/D1:2 A/D3:2 ADDRESS27
16 15
ADDRESS24 23 24 ADDRESS25 ADDRESS12 A/D1:3 A/D3:3 ADDRESS28
14 13
ADDRESS26 25 26 ADDRESS27 ADDRESS13 A/D1:4 A/D3:4 ADDRESS29
12 11
ADDRESS28 27 28 ADDRESS29 ADDRESS14 A/D1:5 A/D3:5 ADDRESS30
10 9
ADDRESS30 29 30 ADDRESS31 ADDRESS15 A/D1:6 A/D3:6 ADDRESS31
CNTL[0:20] 8 7
CNTL[0:20] CNTL0 31 32 CNTL1 A/D1:7 A/D3:7
6
CNTL2 33 34 CNTL3 OSC CLK:1/Q1
5 CLK_OUT
CNTL4 35 36 CNTL5 CLK:0/Q0
NOT POPULATED 4 3
CNTL6 37 38 CNTL7 n/c GND
2 1

GND
GND
GND
GND
GND
CNTL8 39 40 CNTL9 0R0/0805 n/c n/c
41 42 R19
CNTL10 1 2
43 44 GCK1_FB
OSC 2 1 1 2 OSC_FB

43
42
41
40
39
45 46
R20 DOUT 47 48 R21
0R0/0805 49 50 0R0/0805
NOT POPULATED 2-102977-5 NOT POPULATED
DATA[0:31]
MICTOR(AMP 2-767004-2)
J5
DATA0 38 37 DATA16
C A/D0:0 A/D2:0 C
DATA1 36 35 DATA17
DATA[0:31] DATA2 A/D0:1 A/D2:1 DATA18
34 33
DATA3 A/D0:2 A/D2:2 DATA19
JP6 32 31
DATA0 DATA1 DATA4 A/D0:3 A/D2:3 DATA20
30 29
DATA2 1 2 DATA3 DATA5 A/D0:4 A/D2:4 DATA21
28 27
DATA4 3 4 DATA5 DATA6 A/D0:5 A/D2:5 DATA22
26 25
DATA6 5 6 DATA7 DATA7 A/D0:6 A/D2:6 DATA23
24 23
DATA8 7 8 DATA9 DATA8 A/D0:7 A/D2:7 DATA24
22 21
DATA10 9 10 DATA11 DATA9 A/D1:0 A/D3:0 DATA25
20 19
DATA12 11 12 DATA13 DATA10 A/D1:1 A/D3:1 DATA26
18 17
DATA14 13 14 DATA15 DATA11 A/D1:2 A/D3:2 DATA27
16 15
DATA16 15 16 DATA17 DATA12 A/D1:3 A/D3:3 DATA28
14 13
DATA18 17 18 DATA19 DATA13 A/D1:4 A/D3:4 DATA29
12 11
DATA20 19 20 DATA21 DATA14 A/D1:5 A/D3:5 DATA30
10 9
DATA22 21 22 DATA23 DATA15 A/D1:6 A/D3:6 DATA31
8 7
DATA24 23 24 DATA25 A/D1:7 A/D3:7
GCK1 6
DATA26 25 26 DATA27 CLK:1/Q1
5 GCK3
DATA28 27 28 DATA29 CLK:0/Q0
4 3
DATA30 29 30 DATA31 n/c GND
2 1

GND
GND
GND
GND
GND
CNTL[0:20] CNTL11 31 32 CNTL12 CNTL[0:20] n/c n/c
CNTL13 33 34 CNTL14
CNTL15 35 36 CNTL16

43
42
41
40
39
CNTL17 37 38 CNTL18 NOT POPULATED
CNTL19 39 40 CNTL20 0R0/0805
B R22 B
41 42
1 2 CLK_IN
43 44
2 1
NOT POPULATED

45 46 CLK_OUT
47 48
2

R23 CNTL[0:20]
NOT POPULATED 49 50 0R0/0805
R24 MICTOR(AMP 2-767004-2)
2
2

2-102977-5 NOT POPULATED J6

R26 0R0/0805 CNTL0 38 37 CNTL16
R25 CNTL1 A/D0:0 A/D2:0
36 35 CNTL17
0R0/0805 CNTL2 A/D0:1 A/D2:1 CNTL18
1

0R0/0805 34 33
NOT POPULATED CNTL3 A/D0:2 A/D2:2 CNTL19
32 31
CNTL4 A/D0:3 A/D2:3 CNTL20
1
1

30 29
A/D0:4 A/D2:4
CLK_OUT_FB

CNTL5 28 27
CNTL6 A/D0:5 A/D2:5 RS232RX
26 25 RS232TX
CNTL7 A/D0:6 A/D2:6
GCK3
GCK1

24 23 RS232EN_N
CNTL8 A/D0:7 A/D2:7
22 21 RS232SD_N
CNTL9 A/D1:0 A/D3:0
20 19 TEMP_SCLK
CNTL10 A/D1:1 A/D3:1
18 17 TEMP_CE
CNTL11 A/D1:2 A/D3:2
16 15 TEMP_SDI
CNTL12 A/D1:3 A/D3:3
14 13 TEMP_SDO SWITCH[0:9]
CNTL13 A/D1:4 A/D3:4 SWITCH8
12 11
CNTL14 A/D1:5 A/D3:5 SWITCH9
10 9
CNTL15 A/D1:6 A/D3:6
8 7 DOUT
A/D1:7 A/D3:7
CLK_IN 6
A CLK:1/Q1 A
5 CLK_OUT
CLK:0/Q0
4 3
n/c GND
2 1
GND
GND
GND
GND
GND

n/c n/c
Avnet, Inc. Design Services Copyright 2000
Title
43
42
41
40
39

Mini-Virtex-E Board - Connectors

Size Document Number Rev
B H394-XLX5-MVE-1002 A

Date: Tuesday, October 17, 2000 Sheet 4 of 6

5 4 3 2 1
 5 4 3 2 1

10K R27
LED[0:7] 1 2

10K R28

LED0
1 2

LED1

LED2

LED4

LED5

LED7
LED3

LED6
SWITCH[0:9]
10K R29
1 2

10K R30 SWITCH0

D D
VCC 1 2
2

2
SWITCH1
R31 R32 R33 R34 R35 R36 R37 R38
S1 SWITCH2
1K 1K 1K 1K 1K 1K 1K 1K 1 16
2 15 SWITCH3
1

1
3 14
QTLP650C-2

QTLP650C-2

QTLP650C-2

QTLP650C-2

QTLP650C-2

QTLP650C-2

QTLP650C-2
QTLP650C-2

4 13
D2 D3 D4 D5 D6 D7 D8 D9 5 12 SWITCH4
6 11
7 10 SWITCH5
8 9
SWITCH6
3-435640-9
SWITCH7

SW1 SWITCH8
VCC 1 2
U5 4 3 SWITCH9
7914J-1-000E
8 10K R39
VCC
SW2 1 2
0R0/0805 R40 1 2

1
C 2 1 4 3 10K R41 C
C55 7914J-1-000E 1 2
OSC R42
0.1uF 10K R43
2
OSC 5 1 2 1
OUT ENABLE
1 2
Do Not Populate U6
4 VCC 10K R44
GND
1 2
3 1 10K R45
IR_TXD TXD LEDA

2
1 2
R46 R47
OSC/SOCKET 2 10K R48
LEDC
4 1 2
IR_RXD RXD 1206, 1.8R 1206, 1.8R

1
C56 C57
5 6
IR_SHDN SHDN VCC 0.1uF 0.1uF

2
VCC + C58
4.7uF, TAN
R49
R50

2
1 2 7 8 SEG1_E 1 2
Mode GND
220
B 0R0/0805 B
R51
SEG1_D 1 2
220
TFDU6101E
R52 R53
SEG1_C 1 2 1 2 SEG1_F
U7
220 220
C59 VCC 1 20
R54 E1 N/C2 R55
1 2 SEG1_Dp 1 2 2 19 1 2 SEG1_G
D1 N/C1
220 3 18 220
0.1uF C1 F1
4 17
R56 Dp1 G1 R57
SEG2_E 1 2 5 16 1 2 SEG1_A
RS232SD_N E2 A1
1

C60 220 6 15 220

U8 D2 B1
P1 7 14
0.1uF VCC R58 G2 S1 R59
1 20 5 SEG2_D 1 2 8 13 1 2 SEG1_B
RS232EN_N EN SD C2 S2
2

2 19 9 220 9 12 220
C61 C1+ VCC Dp2 F2
3 18 4 10 11
V+ GND B2 A2 R60
1 2 4 17 8 1 2 SEG2_F
C1- T1OUT R61
5 16 3 SEG2_G 1 2 MAN6141C 220
1

0.1uF C2+ R1IN

6 15 7 220
C2- R1OUT R62 R63
7 14 2 1 2 SEG2_A
C62 V- n/c R64
8 13 6 SEG2_C 1 2 220
T2OUT T1IN U9 0R0/0805
1 2 9 12 1 220
R2IN T2IN
10 11 1 8
0.1uF R2OUT n/c 747844-6 VDDD VDDA R65
2

2 7 SEG2_Dp 1 2
A ADM3222ARS TEMP_CE CE SERMODE A
3 6 TEMP_SDI 220
TEMP_SCLK SCLK SDI
C63 4 5 TEMP_SDO
GND SDO R66
2 1 SEG2_B 1 2
220 Avnet, Inc. Design Services
1

Copyright 2000
0.1uF DS1722U R67 Title
DO NOT POPULATE Mini-Virtex-E Board - Switch, LED, OSC
RS232TX Size Document Number Rev
B A
2

RS232RX H394-XLX5-MVE-1002
Date: Tuesday, October 17, 2000 Sheet 5 of 6
5 4 3 2 1
 5 4 3 2 1

ADDRESS[0:31]
AUX+3.3V
P2
ADDRESS0 71 1
IO +5V ADDRESS1
72 2
ADDRESS3 GND IO ADDRESS2
73 3
ADDRESS4 IO IO
74 4
IO GND ADDRESS5
75 5
ADDRESS7 GND IO ADDRESS6
76 6
ADDRESS8 IO IO
77 7
IO GND ADDRESS9
78 8
D ADDRESS11 +3.3V IO ADDRESS10 D
79 9
ADDRESS12 IO IO
80 10
IO GND ADDRESS13
81 11
ADDRESS15 GND IO ADDRESS14
82 12
ADDRESS16 IO IO
83 13
IO +5V ADDRESS17
84 14
ADDRESS19 GND IO ADDRESS18
85 15
ADDRESS20 IO IO
86 16
IO GND ADDRESS21
87 17
ADDRESS23 GND IO ADDRESS22
88 18
ADDRESS24 IO IO
89 19
IO GND ADDRESS25
90 20
ADDRESS27 +3.3V IO ADDRESS26
91 21
ADDRESS28 IO IO
92 22
IO GND ADDRESS29
93 23
ADDRESS31 GND IO ADDRESS30
94 24
DATA0 IO IO
95 25
IO +5V DATA1
96 26
DATA3 GND IO DATA2
97 27
DATA4 IO IO
98 28
IO GND DATA5
99 29
DATA7 GND IO DATA6
100 30
DATA8 IO IO
101 31
IO GND DATA9
C 102 32 DATA[0:31] C
DATA11 +3.3V IO DATA10
103 33
DATA12 IO IO
104 34
IO GND DATA13
105 35
DATA15 GND IO DATA14
106 36
DATA16 IO IO
107 37
DATA[0:31] IO +5V DATA17
108 38
DATA19 GND IO DATA18
109 39
DATA20 IO IO
110 40
IO GND DATA21
111 41
DATA23 GND IO DATA22
112 42
DATA24 IO IO
113 43
IO GND DATA25
114 44
DATA27 +3.3V IO DATA26
115 45
DATA28 IO IO
116 46
IO GND DATA29
117 47
DATA31 GND IO DATA30
118 48
CNTL0 IO IO
119 49
IO +5V CNTL1
120 50
CNTL3 GND IO CNTL2
121 51
CNTL4 IO IO
122 52
IO GND CNTL5
123 53
CNTL7 GND IO CNTL6
124 54
CNTL8 IO IO
125 55
IO GND CNTL9
B 126 56 B
CNTL11 +3.3V IO CNTL10
127 57
CNTL12 IO IO
128 58
IO GND CNTL13
129 59
CNTL15 GND IO CNTL14
130 60
CNTL16 IO IO
131 61
IO +5V CNTL17 NOT POPULATED
132 62
CNTL19 GND IO CNTL18
133 63 R68
CNTL20 IO IO
134 64 CNTL[0:20] 0R0/0805
0R0/0805 R69 IO GND
135 65 2 1 CLK_IN
CNTL[0:20] GND IO
2 1 136 66 2 1 CLK_OUT_FB
CLK_OUT IO IO
137 67 R70
NOT POPULATED JTAG_TMS TMS GND
138 68 JTAG_TDO
+3.3V TDO 0R0/0805
139 69 JTAG_TCK
JTAG_TDI TDI TCK NOT POPULATED
140 70
JTAG_TRS TRST GND
5-179010-6

A A

Avnet, Inc. Design Services Copyright 2000

Title
Mini-Virtex-E Board - Daughter Board Connector
Size Document Number Rev
B H394-XLX5-MVE-1002 A

Date: Tuesday, October 17, 2000 Sheet 6 of 6

5 4 3 2 1