PD - 94499A

AUTOMOTIVE MOSFET IRFR3504

IRFU3504
Features HEXFET® Power MOSFET
● Advanced Process Technology
● Ultra Low On-Resistance D
● 175°C Operating Temperature VDSS = 40V
● Fast Switching
● Repetitive Avalanche Allowed up to Tjmax RDS(on) = 9.2mΩ
Description G
Specifically designed for Automotive applications, this HEXFET®
Power MOSFET utilizes the latest processing techniques to ID = 30A
S
achieve extremely low on-resistance per silicon area. Addi-
tional features of this product are a 175°C junction operating
temperature, fast switching speed and improved repetitive
avalanche rating. These features combine to make this design
an extremely efficient and reliable device for use in Automotive
applications and a wide variety of other applications.

The D-Pak is designed for surface mounting using vapor

phase, infrared, or wave soldering techniques. The straight
lead version (IRFU series) is for through-hole mounting
applications. Power dissipation levels up to 1.5 watts are D-Pak I-Pak
possible in typical surface mount applications. IRFR3504 IRFU3504

Absolute Maximum Ratings

Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon limited) 87
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (See Fig.9) 61 A
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package limited) 30
IDM Pulsed Drain Current  350
PD @TC = 25°C Power Dissipation 140 W
Linear Derating Factor 0.92 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy‚ 240 mJ
EAS (tested) Single Pulse Avalanche Energy Tested Value‡ 480
IAR Avalanche Current See Fig.12a, 12b, 15, 16 A
EAR Repetitive Avalanche Energy† mJ
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range °C
Soldering Temperature, for 10 seconds 300 (1.6mm from case )

Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 1.09
RθJA Junction-to-Ambient (PCB mount)ˆ ––– 50 °C/W
RθJA Junction-to-Ambient ––– 110

HEXFET(R) is a registered trademark of International Rectifier.

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IRFR/U3504
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 40 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.041 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 7.8 9.2 mΩ VGS = 10V, ID = 30A „
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = 10V, ID = 250µA
gfs Forward Transconductance 40 ––– ––– S VDS = 10V, ID = 30A
––– ––– 20 VDS = 40V, VGS = 0V
IDSS Drain-to-Source Leakage Current µA
––– ––– 250 VDS = 40V, VGS = 0V, TJ = 125°C
Gate-to-Source Forward Leakage ––– ––– 200 VGS = 20V
IGSS nA
Gate-to-Source Reverse Leakage ––– ––– -200 VGS = -20V
Qg Total Gate Charge ––– 48 71 ID = 30A
Qgs Gate-to-Source Charge ––– 12 18 nC VDS = 32V
Qgd Gate-to-Drain ("Miller") Charge ––– 13 20 VGS = 10V„
td(on) Turn-On Delay Time ––– 11 ––– VDD = 20V
tr Rise Time ––– 53 ––– ID = 30A
ns
td(off) Turn-Off Delay Time ––– 36 ––– RG = 6.8Ω
tf Fall Time ––– 22 ––– VGS = 10V „
D
LD Internal Drain Inductance ––– 4.5 ––– Between lead,
nH 6mm (0.25in.)
G
LS Internal Source Inductance ––– 7.5 ––– from package
and center of die contact S

Ciss Input Capacitance ––– 2150 ––– VGS = 0V

Coss Output Capacitance ––– 580 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 46 ––– pF ƒ = 1.0MHz, See Fig. 5
Coss Output Capacitance ––– 2830 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss Output Capacitance ––– 510 ––– VGS = 0V, VDS = 32V, ƒ = 1.0MHz
Coss eff. Effective Output Capacitance … ––– 870 ––– VGS = 0V, VDS = 0V to 32V

Source-Drain Ratings and Characteristics

Parameter Min. Typ. Max. Units Conditions
D
IS Continuous Source Current MOSFET symbol
––– ––– 87
(Body Diode) showing the
A
I SM Pulsed Source Current integral reverse G

––– ––– 350

(Body Diode)  p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 30A, VGS = 0V „
trr Reverse Recovery Time ––– 53 80 ns TJ = 25°C, IF = 30A, VDD = 20V
Q rr Reverse Recovery Charge ––– 86 130 nC di/dt = 100A/µs „
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

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 IRFR/U3504

1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
100 7.0V
ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

7.0V
6.0V 6.0V
5.5V 100 5.5V
5.0V 5.0V
10 4.5V 4.5V
BOTTOM 4.0V BOTTOM 4.0V

1 10
4.0V
0.1 4.0V
1
0.01
20µs PULSE WIDTH 20µs PULSE WIDTH
Tj = 25°C Tj = 175°C
0.001 0.1
0.1 1 10 100 1000 0.1 1 10 100 1000
VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000.00 80

70
G fs , Forward Transconductance (S)
ID, Drain-to-Source Current (Α)

T J = 175°C
T J = 25°C
100.00 60

50

10.00 TJ = 175°C
40

30
TJ = 25°C
1.00 20
VDS = 25V
VDS = 25V
20µs PULSE WIDTH 10
 20µs PULSE WIDTH
0.10
0
2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0
0 20 40 60 80 100 120
VGS, Gate-to-Source Voltage (V)
ID,Drain-to-Source Current (A)

Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance

Vs. Drain Current
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IRFR/U3504

100000 12
I D = 30A
VGS = 0V, f = 1 MHZ VDS = 32V
Ciss = Cgs + Cgd, C ds SHORTED VDS = 20V
Crss = Cgd 10 VDS = 8V

Coss = Cds + Cgd

10000

VGS , Gate-to-Source Voltage (V)

C, Capacitance(pF)

Ciss

1000 Coss 6

100
Crss

10 0
0 10 20 30 40 50
1 10 100
QG, Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance Vs. Fig 6. Typical Gate Charge Vs.

Drain-to-Source Voltage Gate-to-Source Voltage

1000 1000
OPERATION IN THIS AREA
LIMITED BY R DS (on)
ID, Drain-to-Source Current (A)

100
I SD , Reverse Drain Current (A)

TJ = 175 °C
100

100µsec
10

°C
10 1msec
TJ = 25
1
Tc = 25°C
Tj = 175°C
10msec
Single Pulse
V GS = 0 V
0.1 1
0.0 0.5 1.0 1.5 2.0 2.5 3.0
1 10 100 1000
V SD,Source-to-Drain Voltage (V)
VDS, Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage
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 IRFR/U3504

100 2.5
I D = 87A
LIMITED BY PACKAGE

80 2.0

RDS(on) , Drain-to-Source On Resistance

ID , Drain Current (A)

(Normalized)
1.5
60

1.0
40

0.5
20

V GS = 10V
0.0
0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
25 50 75 100 125 150 175
TJ , Junction Temperature ( ° C)
TC , Case Temperature ( °C)

Fig 9. Maximum Drain Current Vs. Fig 10. Normalized On-Resistance

Case Temperature Vs. Temperature

10
(Z thJC )

D = 0.50
Thermal Response

0.20

0.10 P DM

0.1
0.05 t1
SINGLE PULSE
0.02 t2
0.01 (THERMAL RESPONSE)

Notes:
1. Duty factor D = t1 / t 2
2. Peak T J = P DM x Z thJC +TC
0.01
0.00001 0.0001 0.001 0.01 0.1 1

t1, Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRFR/U3504

500
15V ID
TOP 12A
21A
L DRIVER 400 BOTTOM 30A
VDS

E AS , Single Pulse Avalanche Energy (mJ)

RG D.U.T + 300
V
- DD
IAS A
20V
VGS
tp 0.01Ω
200

Fig 12a. Unclamped Inductive Test Circuit

V(BR)DSS
100
tp

0
25 50 75 100 125 150 175
Starting Tj, Junction Temperature ( ° C)

I AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
Vs. Drain Current
QG

10 V
QGS QGD 4.0
VGS(th) Gate threshold Voltage (V)

VG
3.5

Charge 3.0
Fig 13a. Basic Gate Charge Waveform ID = 250µA
Current Regulator
Same Type as D.U.T. 2.5

50KΩ

12V .2µF
.3µF
2.0
+
V
D.U.T. - DS
1.5
VGS
-75 -50 -25 0 25 50 75 100 125 150 175 200
3mA
T J , Temperature ( °C )
IG ID
Current Sampling Resistors

Fig 13b. Gate Charge Test Circuit Fig 14. Threshold Voltage Vs. Temperature
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 IRFR/U3504

10000

Duty Cycle = Single Pulse

1000
Allowed avalanche Current vs
Avalanche Current (A)

avalanche pulsewidth, tav

100 assuming ∆ Tj = 25°C due to
0.01
avalanche losses

0.05
10 0.10

0.1
1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)

Fig 15. Typical Avalanche Current Vs.Pulsewidth

250 Notes on Repetitive Avalanche Curves , Figures 15, 16:

TOP Single Pulse (For further info, see AN-1005 at www.irf.com)
BOTTOM 10% Duty Cycle 1. Avalanche failures assumption:
ID = 30A Purely a thermal phenomenon and failure occurs at a
EAR , Avalanche Energy (mJ)

200
temperature far in excess of T jmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
150 not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
100 4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
50 6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
T jmax (assumed as 25°C in Figure 15, 16).
0 tav = Average time in avalanche.
25 50 75 100 125 150 175 D = Duty cycle in avalanche = tav ·f
Starting T J , Junction Temperature (°C) ZthJC(D, tav ) = Transient thermal resistance, see figure 11)

PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC

Fig 16. Maximum Avalanche Energy Iav = 2DT/ [1.3·BV·Zth]
Vs. Temperature EAS (AR) = PD (ave)·t av
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IRFR/U3504

Driver Gate Drive

D.U.T P.W.
Period D=
P.W.
Period
+

ƒ
*
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
‚
-
„ +
Recovery
Current
Body Diode Forward
Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by RG V DD Re-Applied

• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• I SD controlled by Duty Factor "D" - Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs

RD
V DS

V GS
D.U.T.
RG
+
-V DD

10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %

Fig 18a. Switching Time Test Circuit

VDS
90%

10%
VGS
td(on) tr t d(off) tf

Fig 18b. Switching Time Waveforms

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 IRFR/U3504

D-Pak (TO-252AA) Package Outline

Dimensions are shown in millimeters (inches)

2.38 (.094)
6.73 (.265) 2.19 (.086)
6.35 (.250) 1.14 (.045)
0.89 (.035)
-A-
5.46 (.215) 1.27 (.050) 0.58 (.023)
5.21 (.205) 0.88 (.035) 0.46 (.018)

6.45 (.245)
5.68 (.224)
6.22 (.245)
5.97 (.235) 10.42 (.410)
1.02 (.040) 9.40 (.370) LEAD ASSIGNMENTS
1.64 (.025) 1 2 3
1 - GATE
0.51 (.020) 2 - DRAIN
-B- MIN. 3 - SOURCE
1.52 (.060) 4 - DRAIN
1.15 (.045)
0.89 (.035)
3X
0.64 (.025) 0.58 (.023)
1.14 (.045) 0.46 (.018)
2X 0.25 (.010) M A M B
0.76 (.030)

2.28 (.090) NOTES:

1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
4.57 (.180) 2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).

D-Pak (TO-252AA) Part Marking Information

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www.irf.com 9
IRFR/U3504

I-Pak (TO-251AA) Package Outline

Dimensions are shown in millimeters (inches)

6.73 (.265) 2.38 (.094)

6.35 (.250) 2.19 (.086)
-A-
1.27 (.050) 0.58 (.023)
5.46 (.215)
0.88 (.035) 0.46 (.018)
5.21 (.205)
LEAD ASSIGNMENTS
4 1 - GATE
6.45 (.245) 2 - DRAIN
5.68 (.224) 3 - SOURCE
1.52 (.060) 6.22 (.245) 4 - DRAIN
1.15 (.045) 5.97 (.235)

1 2 3

-B- NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2.28 (.090) 9.65 (.380) 2 CONTROLLING DIMENSION : INCH.
1.91 (.075) 8.89 (.350) 3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).

1.14 (.045) 1.14 (.045)

3X 0.89 (.035)
0.76 (.030) 3X 0.89 (.035)
0.64 (.025)

2.28 (.090) 0.25 (.010) M A M B 0.58 (.023)

0.46 (.018)
2X

I-Pak (TO-251AA) Part Marking Information

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 IRFR/U3504
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR TRR TRL

16.3 ( .641 ) 16.3 ( .641 )

15.7 ( .619 ) 15.7 ( .619 )

12.1 ( .476 ) 8.1 ( .318 )

FEED DIRECTION FEED DIRECTION
11.9 ( .469 ) 7.9 ( .312 )

NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.

Notes:
 Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
‚ Limited by TJmax, starting TJ = 25°C,
L = 0.52mH, RG = 25Ω, IAS = 30A, VGS =10V.
Part not recommended for use above this
value.
ƒ ISD ≤ 30A, di/dt ≤ 170A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C.
„ Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
… Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
† Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
‡ This value determined from sample failure population. 100%
tested to this value in production.
ˆ When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to
application note #AN-994.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 12/02
www.irf.com 11
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/