ADC Tm4c1294ncpdt - En.es

tiva ™ TM4C1294NCPDT microcontrolador
15 de analógico a digital (ADC)

Un convertidor de analógico a digital (ADC) es un periférico que convierte una tensión analógica continua a un número digital discreto. Dos módulos de convertidor
idénticas están incluidos, que comparten 20 canales de entrada. El módulo TM4C1294NCPDT ADC tiene una resolución de la conversión de 12 bits y soporta 20
canales de entrada, además de un sensor de temperatura interno. Cada módulo ADC contiene cuatro secuenciadores programables que permiten el muestreo de
múltiples fuentes de entrada analógicas sin intervención del controlador. Cada secuenciador muestra proporciona una programación flexible con fuente totalmente
configurable de entrada, eventos de disparo, la generación de interrupción, y la prioridad secuenciador. Además, el valor de conversión opcionalmente puede ser
desviado a un módulo comparador digital. Cada módulo ADC proporciona ocho comparadores digitales. Cada comparador digital evalúa el valor de conversión
ADC en contra de sus dos valores definidos por el usuario para determinar el radio de acción de la señal. La fuente de disparo para ADC0 y ADC1 puede ser
independiente o los dos módulos ADC puede funcionar de la misma fuente de disparo y operar en el mismo o diferentes entradas. Un desplazador de fase puede
retrasar el inicio de muestreo por un ángulo de fase especificado. Cuando se utilizan dos módulos de ADC, es posible configurar los convertidores de iniciar las
conversiones por coincidencia o dentro de una fase relativa entre sí, ver “muestra de la fase de control” en la página 1060. Un desplazador de fase puede retrasar
el inicio de muestreo por un ángulo de fase especificado. Cuando se utilizan dos módulos de ADC, es posible configurar los convertidores de iniciar las
conversiones por coincidencia o dentro de una fase relativa entre sí, ver “muestra de la fase de control” en la página 1060. Un desplazador de fase puede retrasar
el inicio de muestreo por un ángulo de fase especificado. Cuando se utilizan dos módulos de ADC, es posible configurar los convertidores de iniciar las
conversiones por coincidencia o dentro de una fase relativa entre sí, ver “muestra de la fase de control” en la página 1060.
El microcontrolador TM4C1294NCPDT proporciona dos módulos ADC y cada una tiene las siguientes características:
■ 20 canales de entrada analógica compartidos
■ Precisión ADC de 12 bits
■ y configuraciones de entrada diferencial de terminación única
■ En el chip sensor de temperatura interno
■ velocidad de muestreo máxima de dos millones de muestras / segundo
■ , Retardo de fase programable opcional
■ De la muestra y la ventana de retención programabilidad
■ Cuatro secuenciadores de conversión muestra programables de uno a ocho entradas de largo, con FIFOs resultado de la
conversión correspondiente
■ control de disparo flexibles
- Controlador (software)
- temporizadores
- comparadores analógicos
- PWM
- GPIO
■ promediado Hardware de hasta 64 muestras
■ Ocho comparadores digitales
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Texas Instruments-Producción de Datos
Analógico a digital (ADC)
■ Convertidor utiliza señales VREFA + y GNDA como la referencia de tensión
■ Potencia y tierra para la circuitería analógica es independiente de la potencia digital y tierra
■ transferencias eficientes utilizando Controlador de Acceso Directo (Micro Memory μDMA)
- canal dedicado para cada muestra de secuenciador
- Módulo ADC utiliza solicitudes se rompió para el DMA
■ Reloj mundial alternativo (ALTCLK) de recursos o reloj del sistema (SYSCLK) se pueden utilizar para generar un reloj ADC
15.1 Diagrama de bloques

El microcontrolador TM4C1294NCPDT contiene dos módulos idénticos conversión analógica-digital. Estos twomodules, ADC0 y ADC1, comparten
los mismos 20 canales de entrada analógicos. Cada ADCmodule funciona de manera independiente y por lo tanto puede ejecutar diferentes
secuencias de la muestra, la muestra cualquiera de los canales de entrada analógicos en cualquier momento, y generar diferentes interrupciones y
disparadores. Figura 15-1 en la página 1054 muestra cómo los dos módulos están conectados a las entradas analógicas y el bus de sistema.
Figura 15-1. Implementación de dos bloques de ADC
Los canales
disparadores ADC 0
de entrada
Interrupciones /
disparadores
ADC 1
Interrupciones /
disparadores
Figura 15-2 en la página 1055 proporciona detalles sobre la configuración interna de los controles de ADC y registros de datos.
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Figura 15-2. Diagrama de bloques del módulo ADC
VDDA / GNDA Externa Voltaje Ref
Activadores de eventos
comparador Sequencer
PWM Muestra 0
Control / Estado
GPIO ES3
ADCSSMUX0
temporizador
ADCSSCTL0 Análogo a digital
ADCACTSS
Convertidor
ADCOSTAT ADCSSFSTAT0
comparador Entradas analógicas ( AINx)
PWM ADCUSTAT ADCSSEMUX0

GPIO SS2
ADCTSSEL
temporizador
ADCSSPRI Sequencer
Muestra 1
ADCSPC
comparador
ADCSSMUX3
PWM ADCPP Averager hardware
GPIO SS1 ADCSSCTL1
ADCPC
temporizador ADCSAC
ADCSSFSTAT1
ADCCC
ADCSSEMUX1
comparador
PWM
GPIO SS0 Sequencer

temporizador Muestra 2
ADCSSMUX2
Comparador
ADCSSCTL2
Bloquear FIFO Digital ADCSSOPn
ADCEMUX
ADCSSFSTAT2
ADCSSDCn
ADCPSSI ADCSSEMUX2 ADCSSFIFO3
ADCDCCTLn
ADCSSFIFO0
ADCDCCMPn
Sequencer ADCSSFIFO1
Muestra 3
ADCSSFIFO2 ADCDCRIC
SS0 Interrupt SS1 SS2
ADCSSMUX1
de interrupción de
interrupción de interrupción ADCSSCTL3
interrupción SS3
ADCIM control de ADCSSFSTAT3
ADCSSEMUX3
ADCISC ADCRIS
ADCDCISC Las interrupciones de corriente continua
PWM de activación
15.2 Descripción de la señal
La siguiente tabla enumera las señales externas del módulo ADC y se describe la función de cada uno. los AINx las señales son funciones
analógicas para algunas señales GPIO. La columna en la tabla de abajo titulada "Asignación Pin Mux / Pin" enumera la colocación pin GPIO
para las señales de ADC. Estas señales se configuran en la limpieza de la correspondiente GUARIDA poco en el GPIO digitales permiten
(GPIODEN) registrar y establecer la correspondiente AMSEL poco en el GPIO modo analógico Seleccione (GPIOAMSEL) registro. Para
obtener más información sobre la configuración GPIO, consulte “Uso General entradas / salidas (GPIO)” en la página 742. La VREFA + de
señal (con la palabra "fijo" en la columna de la asignación de pines Mux / Pin) tiene una asignación de contactos fijo y la función.
Tabla 15-1. Las señales de ADC (128TQFP)
Nombre pin Número de PIN Pin Mux / Asignación espigas de Tipo Tipo de búfer Descripción
de terminales
AIN0 12 PE3 yo Conversión analógica-digital de entrada 0. Analog
AIN1 13 PE2 yo Conversión analógica-digital de entrada analógica 1.
AIN2 14 PE1 yo Conversión analógica-digital de entrada analógica 2.
AIn3 15 PE0 yo Conversión analógica-digital de entrada 3. analógico
AIN4 128 PD7 yo Conversión analógica-digital de entrada 4. analógico
AIN5 127 PD6 yo Conversión analógica-digital de entrada 5. analógico
AIN6 126 PD5 yo Conversión analógica-digital de entrada 6. Analog
AIN7 125 PD4 yo Conversión analógica-digital de entrada analógica 7.
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Tabla 15-1. Las señales de ADC () (128TQFP continuado)
Nombre pin Número de PIN Pin Mux / Asignación espigas de Tipo Tipo de búfer Descripción
de terminales
AIN10 121 PB4 yo Conversión analógica-digital de entrada 10. analógico
AIN11 120 PB5 yo Conversión analógica-digital de entrada 11. Analog
AIN16 18 PK0 yo Conversión analógica-digital de entrada 16. analógico
AIN19 21 PK3 yo Conversión analógica-digital de entrada 19. Analog
VREFA + 9 fijo - Un voltaje de referencia utilizado para especificar la tensión a la

que el ADC convierte a un valor máximo. Este pin se utiliza en
conjunción con GNDA. La tensión que se aplica a VREFA + es la
página 1861. Analog
tensión con la que una Ainn señal se convierte a 4095. La VREFA
+
tensión está limitada a la gama especificada en la Tabla 27-44 en la
15.3 descripcion funcional

El TM4C1294NCPDT ADC recoge datos de la muestra mediante el uso de un enfoque basado en secuencia programable en lugar de los enfoques
de muestreo doble simple o tradicionales que se encuentran en muchos módulos ADC. Cada secuencia de muestras es una serie totalmente
programada de muestras consecutivas (espalda contra espalda), permitiendo que el ADC para recoger datos procedentes de múltiples fuentes de
entrada sin tener que ser re-configurado o mantenido por el procesador. La programación de cada muestra en la secuencia de muestra incluye
parámetros tales como la fuente de entrada y el modo (diferencial frente a la entrada de un solo extremo), la generación de interrupción en la
terminación de la muestra, y el indicador para la última muestra de la secuencia. Además, el μDMA se puede utilizar para mover de manera más
eficiente los datos de los secuenciadores de ejemplo y sin intervención de la CPU.
15.3.1 Secuenciadores de ejemplo
La captura de control de muestreo y los datos es manejado por los secuenciadores de muestra. Todos los secuenciadores son idénticos en
aplicación excepto por el número de muestras que se pueden capturar y la profundidad de la FIFO. Tabla 15-2 en la página 1056 muestra el
número máximo de muestras que cada secuenciador puede capturar y su correspondiente profundidad FIFO. Cada muestra que se captura se
almacena en la FIFO. En esta implementación, cada entrada FIFO es una palabra de 32 bits, con los 12 bits inferiores que contienen el
resultado de la conversión.
Tabla 15-2. Las muestras y la profundidad de FIFO Secuenciadores
secuenciador Número de muestras La profundidad de FIFO
ES3 1 1
SS2 4 4
SS1 4 4
SS0 8 8
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Para una secuencia de muestra dado, cada muestra está definida por los campos de bits en el ADC Muestra Secuencia entrada del multiplexor
Select (ADCSSMUXn), Secuencia ADC Muestra extendido entrada del multiplexor Select (ADCSSEMUXn) y ADC Secuencia Muestra de
Control (ADCSSCTLn) registros, donde "n" corresponde al número de secuencia. los ADCSSMUXn y ADCSSEMUXn campos seleccionar el pin de
entrada, mientras que el ADCSSCTLn campos contienen los bits de control de muestra correspondientes a parámetros tales como la selección de
sensor de temperatura, habilitación de interrupción, final de la secuencia, y diferenciado modo de entrada. secuenciadores de muestra están
activados mediante el establecimiento de la respectiva ASENn poco en el ADC Sequencer Muestra activa (ADCACTSS) registrar y debe ser
configurado antes de ser activado. El muestreo se inicia entonces mediante el establecimiento de la SSN poco en el ADC Secuencia Sample
Processor Iniciar (ADCPSSI)
registro. Además, las secuencias de la muestra pueden ser iniciadas en múltiples módulos ADC utilizando simultáneamente el GSync y SYNCWAIT
bits en el ADCPSSI registrarse durante la configuración de cada módulo ADC. Para obtener más información sobre el uso de estos bits,
consulte la página 1103.
Al configurar una secuencia de muestras, se permiten múltiples usos de la misma patilla de entrada dentro de la misma secuencia. En el ADCSSCTLn registro,
la IEn los bits se pueden establecer para cualquier combinación de las muestras, lo que permite las interrupciones que se generen después de cada
muestra en la secuencia si es necesario. También el FINAL
bit se puede ajustar en cualquier punto dentro de una secuencia de la muestra. Por ejemplo, si se utiliza Sequencer 0, la FINAL
bit se puede ajustar en el nibble asociada con la quinta muestra, lo que permite Sequencer 0 para completar la ejecución de la secuencia de la
muestra después de la quinta muestra.
Después de una secuencia de muestras completa la ejecución, los datos del resultado se pueden recuperar de la ADC Muestra Secuencia
Resultado FIFO (ADCSSFIFOn) registros. Los FIFO son tampones circulares simples que leen una sola dirección a "pop" datos de resultados.
Para los propósitos de depuración de software, las posiciones de la FIFOhead y punteros de la cola son visibles en el ADCSample Secuencia
FIFOStatus (ADCSSFSTATn)
registra junto con COMPLETO y VACÍO indicadores de estado. Si una escritura que se intente cuando el FIFO está lleno, la escritura no se
produce una condición de desbordamiento y se indica. Extracto y refinado condiciones se controlan usando el ADCOSTAT y ADCUSTAT registros.
Módulo de control 15.3.2

Fuera de los secuenciadores de muestra, el resto de la lógica de control es responsable de tareas tales como:
■ generación de interrupciones
■ operación de DMA
■ priorización secuencia
■ configuración del disparador
■ configuración comparador
■ referencia de tensión externa
■ control de fase de la muestra
■ módulo de reloj
15.3.2.1 interrupciones
Las configuraciones de registro de los secuenciadores de muestra y comparadores digitales dictan qué eventos generar interrupciones primas,
pero no tienen control sobre si la interrupción se envía en realidad para el controlador de interrupciones. señales de interrupción del módulo
ADC están controladas por el estado de la MÁSCARA bits en el Máscara ADC de interrupción (ADCIM) registro. Estado de alarma puede ser
visto en dos lugares: la
ADC cruda de interrupción de estado (ADCRIS) registrar, que muestra el estado en bruto de los diversos interrupción
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señales; y el ADC de interrupción de estado y Clear (ADCISC) registro, que muestra las interrupciones activas que están habilitados por la ADCIM
registro. interrupciones del secuenciador se borran escribiendo un 1 en la correspondiente EN en poco ADCISC. interrupciones comparadores
digitales se borran escribiendo un 1 a la ADC digital Comparador de interrupción de estado y Clear (ADCDCISC) registro.
15.3.2.2 Operación DMA
DMAmay ser utilizado para aumentar la eficiencia al permitir que cada secuenciador muestra para operar independientemente y transferencia
de datos sin la intervención del procesador o de reconfiguración. El ADC afirma señales de petición individuales y de ráfaga μDMA ( dma_sreq y
dma_req) al controlador μDMA basado en el nivel FIFO. los dma_req señal se genera cuando el FIFO en cuestión es un medio completo (es
decir, a las 4 muestras para SS0, 2 muestras para SS1 y SS2, y al 1 muestra para SS3). Si, por ejemplo, el ADCSSCTL0 registro tiene seis
muestras a transferencia, una explosión de cuatro valores se produce seguido de dos transferencias individuales ( dma_sreq). los dma_done señales
(uno por secuenciador muestra) se envían al ADC para permitir una activación de DMAINRn los bits de interrupción en el ADCRIS registro. El
μDMA está habilitada para un secuenciador muestra específica estableciendo la adecuada ADENn poco en el ADCACTSS
registrarse en el offset 0x000.
Para utilizar el μDMA con el ADCmodule, la aplicación debe habilitar el canal a través del ADC Canal DMA Mapa Seleccionar n
(DMACHMAPn) inscribirse en el μDMA.
Consulte la “Micro acceso directo a memoria (μDMA)” en la página 678 para más detalles sobre la programación del controlador μDMA.
15.3.2.3 Priorización
Cuando los eventos de muestreo (disparadores) ocurren simultáneamente, se priorizan para su procesamiento por los valores de la ADC
secuenciador Muestra Prioridad (ADCSSPRI) registro. Los valores válidos son prioritarios en el rango de 0-3, donde 0 es la prioridad más alta y 3 el
más bajo. Múltiples unidades de muestra de secuenciador activas con la misma prioridad no proporcionan resultados consistentes, por lo que el
software debe garantizar que todas las unidades de la muestra del secuenciador activos tienen un valor de prioridad única.
15.3.2.4 eventos de muestreo
Muestra de activación para cada secuenciador muestra se define en el ADC Evento multiplexor Select (ADCEMUX) registro. fuentes de
disparo incluyen procesador (por defecto), comparadores analógicos, una señal externa en una GPIO especificado por el Control de ADC GPIO
(GPIOADCCTL) registrarse, un temporizador GP, un generador de PWM, y el muestreo continuo. El procesador desencadena muestreo
mediante el establecimiento de la SSx bits en el ADC Secuencia Sample Processor Iniciar (ADCPSSI) registro.
Se debe tener cuidado al usar el gatillo muestreo continuo. Si la prioridad de un secuenciador es demasiado alto, es posible morir de hambre
otros secuenciadores de menor prioridad. En general, un secuenciador muestra usando el muestreo continuo se debe establecer la prioridad
más baja. Muestreo continuo se puede utilizar con un comparador digital para causar una interrupción cuando un voltaje particular, se ve en
una entrada.
15.3.2.5 Muestreo y retención Control de ventana
El módulo ADC proporciona la capacidad de programar el muestreo y retención ventana de cada paso en una secuencia a través de la
ADC Muestra Secuencia n Muestreo y retención Tiempo (ADCSSTSHn)
registro. Cada TSHn campo puede ser escrito con una muestra y retención ancho diferente, que está representado en los relojes de ADC. La siguiente
tabla muestra las codificaciones permitidas:
Tabla 15-3. Muestreo y retención Ancho en los relojes de ADC
TSHn codificación norte SH
0x0 4
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Tabla 15-3. Muestreo y retención Ancho de ADC Relojes ( continuado)
TSHn codificación norte SH
0x1 reservado
0x2 8
0x3 reservado
0x4 dieciséis
0x5 reservado
0x6 32
0x7 reservado
0x8 64
0x9 reservado
0xA 128
0xB reservado
0xC 256
0xD-0xF reservado
La frecuencia de conversión ADC es una función del número de muestreo y retención, dada por la siguiente ecuación:
F = CONV 1 / ((N SH + 12) * T ADC)
dónde:
■ N SH es la anchura de la muestra y de retención en los relojes de ADC
■ T ADC es el periodo de reloj de conversión ADC, que es la inversa de la frecuencia de reloj ADC F ADC
Ahora, la máxima resistencia de fuente externa permisible (R S) también cambia con el valor de N SH,
como el tiempo total de sedimentación de la circuitería de entrada debe ser lo suficientemente rápido para resolver a dentro de la resolución ADC en un
intervalo de muestreo único. La circuitería de entrada incluye la resistencia de la fuente externa, así como la resistencia de entrada y la capacitancia de
la ADC (R ADC y C ADC).
Los valores para R S y F CONV para variar N SH valores, con F ADC = 16MHz y F ADC = 32MHz se dan en las tablas 18-4 y 18-4-a-b. El
diseñador del sistema debe tener en cuenta estos dos factores para un funcionamiento óptimo del ADC.
Tabla 15-4. R S y F CONV Valores con diferentes N SH Valores y F ADC = 16 MHz
norte SH ( ciclos) 4 8 dieciséis 32 64 128 256
F CONV ( KSPS) 1000 800 571 364 211 114 60
R S Max (Ω) 500 3500 9500 21500 45500 93500 189500
Tabla 15-5. R S y F CONV Valores con diferentes N SH Valores y F ADC = 32 MHz
norte SH ( ciclos) 4 8 dieciséis 32 64 128 256
F CONV ( KSPS) 2000 1600 1143 727 421 229 119
R S Max (Ω) 250 500 3500 9500 21500 45500 93500
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15.3.2.6 Muestra de control de fase de
La fuente de disparo para ADC0 y ADC1 puede ser independiente o los dos módulos ADC puede funcionar de la misma fuente de disparo y
operar en el mismo o diferentes entradas. Si los convertidores están funcionando a la misma frecuencia de muestreo, pueden ser
configurados para iniciar las conversiones por coincidencia o un ADC pueden ser programados a retrasarse hasta 15 ciclos de reloj respecto
a la otra ADC. El tiempo de la muestra se puede retrasar el tiempo de muestreo estándar mediante la programación del FASE en el campo ADC
Muestra de control de fase (ADCSPC) registro. Figura 15-3 en la página 1060 muestra un ejemplo de diferentes relaciones de fase.
La Figura 15-3. Fases de ejemplo de ADC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dieciséis 17 18 19
ADC Muestra Reloj
0x0 PHASE (sin retraso)
FASE 0x1 (1 ADC lag reloj)
. . . .
. . . .
. . . .
FASE 0xE ( 14 ADC desfase de reloj)
FASE 0xF ( 15 ADC desfase de reloj)
Esta característica se puede utilizar para duplicar la velocidad de muestreo de una entrada. Tanto Módulo ADC 0 y ADC módulo 1 puede ser
programado para muestrear la misma entrada. ADCmodule 0 puede muestrear en la posición estándar (el FASE en el campo ADCSPC registrarse es
0x0). ADCModule 1 se puede configurar para muestra con un retardo de fase ( FASE es distinto de cero). Para una frecuencia de muestreo de dos
millones de muestras / segundo a 16 MHz, la TSHn campo de la totalidad de las muestras del secuenciador de ambos ADC debe ser programado para
0x0 y el
FASE campo de uno de los ADCmodules se debe establecer en 0x8. Los twomodules pueden ser sincronizados usando el GSync y SYNCWAIT
bits en el ADCProcessor Muestra Secuencia Iniciar (ADCPSSI)
registro. Software puede entonces combinar los resultados de los dos módulos para crear una frecuencia de muestreo de dos millones de muestras /
segundo a 16 MHz como se muestra en la Figura 15-4 en la página 1.060.
Figura 15-4. La duplicación de la frecuencia de muestreo del ADC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dieciséis 17 18
ADC Muestra Reloj
GSync
ADC 0x0 0 PHASE (0,0 °)
ADC 1 FASE 0x8 (180,0 °)
Utilizando la ADCSPC registro, ADC0 y ADC1 puede proporcionar una serie de aplicaciones interesantes:
■ muestreo continuo coincidentes de diferentes señales. Los pasos secuencia de muestras corren coincidentemente en ambos convertidores.
En esta situación, el TSHn de hacer coincidir pasos de ejemplo de los dos secuenciadores módulo ADC debe ser la misma y la FASE campo
debe ser 0x0 tanto en el módulo ADC ADCSPC
registros. los TSHn campo se encuentra en el ADC Muestra Secuencia n Muestreo y retención Tiempo (ADCSSTSHn) registro.
- ADC Módulo 0, ADCSPC = 0x0, el muestreo AIN0
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Nota: Si dos ADCs están configurados para muestrear la misma señal, un skew (retardo de fase) debe añadirse a uno de los
módulos ADC para evitar muestreo coincidentes. retraso de fase se puede añadir mediante la programación del FASE en el
campo ADCSPC registro.
■ muestreo sesgada de la misma señal. La oblicuidad se determina tanto por el TSHn en el campo
ADCSSTSHn registros y la FASE en el campo ADCSPC registro. Para la frecuencia de muestreo más rápido sesgado, toda TSHn campos
deben ser programados para 0x0. Si TSHn = 0x0 para todos los secuenciadores y la FASE campo de un ADC es 0x8, la configuración
duplica el ancho de banda de conversión de una sola entrada cuando el software combina los resultados como se muestra en la Figura
15-5 en la página 1.061.
Tenga en cuenta que no es necesario que el TSHn campos sean los mismos en una muestra sesgada. Si una aplicación ha variando la resistencia de
entrada analógica, entonces TSHn y FASE pueden variar de acuerdo con los requisitos operacionales.
La Figura 15-5. El muestreo sesgado
ADC1 S1 S2 S3 S4 S5 S6 S7 S8
ADC0 S1 S2 S3 S4 S5 S6 S7 S8
15.3.2.7 Módulo Clocking
El bloque digital ADC está sincronizado por el reloj del sistema y el bloque analógico ADC tiene una velocidad de un reloj de conversión
separado (ADC Reloj). La frecuencia de reloj ADC puede ser de hasta 32 MHz para generar una tasa de conversión de 2 Msps. Un reloj
ADC 16 MHz proporciona una tasa de muestreo 1 Msps. Hay tres fuentes del reloj ADC:
■ PLL VCO dividida. La frecuencia PLL VCO puede ser configurado para generar hasta un reloj de 32 MHz para una tasa de conversión
de 2 Msps. los CS en el campo ADCCC registro debe ser programado para 0x0 para seleccionar el PLL VCO y la CLKDIV campo se
utiliza para ajustar el divisor de reloj adecuada para la frecuencia deseada.
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■ 16 MHz PIOSC. Uso de la PIOSC proporciona una velocidad de conversión de cerca de 1 Msps. Para utilizar el PIOSC al reloj del ADC,
primero encienda el PLL y luego permitir que el PIOSC en el CS campo de bits en el
ADCCC inscribirse, a continuación, desactivar el PLL.
■ MOSC. La fuente de reloj MOSC debe ser 16 MHz para una tasa de conversión 1 Msps y 32 MHz para una tasa de conversión de 2
Msps.
El reloj del sistema debe estar en la misma frecuencia o mayor que el reloj del ADC. Todos los módulos ADC comparten la misma fuente
de reloj para facilitar la sincronización de muestras de datos entre las unidades de conversión, la selección y programación de que es
proporcionada por ADC0 de ADCCC registro. Los módulos ADC no se ejecutan en diferentes tasas de conversión.
15.3.2.8 en estado de ocupado
los OCUPADO poco de la ADCACTSS registro se utiliza para indicar cuando el ADC está ocupado con una conversión actual. Cuando no hay
disparadores pendientes y que se puede iniciar una nueva conversión en el ciclo inmediato o próximos ciclos, el OCUPADO poco lee como 0. El
software debe leer el estado de la OCUPADO tan clara antes de deshabilitar el reloj ADC por escrito al Convertidor Run Modo de reloj de
control de apertura de puerta de analógico a digital (RCGCADC) registro.
15.3.3 Hardware Circuito de muestra media

resultados más altos de precisión se pueden generar utilizando el circuito de promediación hardware, sin embargo, los mejores resultados
son a costa de rendimiento. Hasta 64 muestras pueden ser acumulados y promediados para formar una única entrada de datos en la FIFO
secuenciador. Throughput se disminuye proporcionalmente al número de muestras en el cálculo del promedio. Por ejemplo, si el circuito de
promediado está configurado para promediar 16 muestras, el rendimiento se reduce por un factor de 16.
Por defecto, el circuito de promediación está apagado, y todos los datos procedentes del convertidor pasa a través de la FIFO secuenciador. El
hardware de promediado es controlado por el ADC de control de muestra media (ADCSAC)
registrarse (véase la página 1105). Un circuito de promediado solo se ha aplicado, por lo tanto todos los canales de entrada reciben la misma
cantidad de un promedio de si son o diferencial de terminación única. La Figura 15-6 muestra un ejemplo en el que la ADCSAC registro se establece
en 0x2 para el hardware de sobremuestreo 4x y la IE1 bit se establece para la secuencia de muestras, dando como resultado una interrupción
después del segundo valor promediado se almacena en la FIFO.
1062 18 de junio 2014

La Figura 15-6. Muestra Ejemplo Promediando
A+B+C+D A+B+C+D
4 4
EN T
15.3.4 conversión analógica-digital

El módulo (ADC) de analógico a digital utiliza una arquitectura de aproximaciones sucesivas de Registro (SAR) para ofrecer un bajo consumo de
energía, valor de conversión de alta precisión de 12 bits. La aproximación sucesiva utiliza una matriz de condensadores conmutados para llevar a
cabo la doble función de muestreo y la celebración de la señal, así como proporcionar la operación DAC de 12 bits.
La Figura 15-7 muestra el diagrama de ADC equivalencia de entrada; para los valores de los parámetros, véase “analógico a digital (ADC)” en la
página 1861.
18 de junio 2014 1063

La Figura 15-7. Equivalencia de entrada ADC
Tiva ™ microcontrolador
Realizar una
entrada de circuito
V DD
ZS equivalente Z ADC
R ADC
rs Alfiler 12 bits SAR
ADC
Convertidor
ESD 12-bit de la
VS V ADCIN yo L
cs Abrazadera palabra
Realizar una
R ADC
Alfiler
entrada de circuito
equivalente
Realizar una
R ADC
Alfiler
entrada de circuito
equivalente
C ADC
El ADC opera tanto desde el 3,3-V de potencia digital de suministros de 1.2 V y analógicas. El reloj ADC se puede configurar para reducir el
consumo de energía cuando no se necesita una conversión ADC (ver “Control del sistema” en la página 239). Las entradas analógicas están
conectadas a la ADC a través de rutas de entrada especialmente equilibrados para minimizar la distorsión y la diafonía en las entradas. Información
detallada sobre las fuentes de alimentación de ADC y entradas analógicas se puede encontrar en la “conversión analógica-digital (ADC)” en la
página 1861.
15.3.4.1 Referencia de tensión
El ADC utiliza señales internas VREFP y VREFN como referencias para producir un valor de conversión de la entrada analógica seleccionada.
VREFP se puede conectar a cualquiera de los dos VREFA + o VDDA y VREFN está conectado a GNDA como se ha configurado por el VREF poco
en el Control de ADC (ADCCTL) registrar, como se muestra en la Figura 15-8.
La Figura 15-8. Referencia de tensión ADC
VDDA
VREFP
VREFA +
El voltaje de referencia
seleccionado mediante el
campo VREF en el Registro
ADCCTL
VREFN
GNDA GNDA ADC
1064 18 de junio 2014

El rango de este valor de conversión es de 0x000 a 0xFFF. En el modo de composición de una sola entrada, el valor 0x000
corresponde al nivel de tensión en VREFN; el valor 0xFFF se corresponde con el nivel de tensión en VREFP. Esta configuración resulta
en una resolución que se puede calcular usando la siguiente ecuación:
mV por código de ADC = (VREFP - VREFN) / 4096
Mientras las almohadillas de entrada analógicas pueden manejar voltajes más allá de este intervalo, las tensiones de entrada analógicas deben
permanecer dentro de los límites prescritos por la Tabla 27-44 en la página 1861 para producir resultados precisos. La V REFA + especificación define el
rango útil para la referencia de tensión externa en VREFA + y
GNDA, ver Tabla 27-44 en la página 1861. Caremust ser tomado para suministrar una tensión de referencia de aceptable quality.Figure 15-9 en la
página 1065 muestra la función de conversión ADC de las entradas analógicas.
La Figura 15-9. Resultado ADC Conversión
0xFFF
0xc00
0x800
0x400
V EN
N
P
EF
EF
VR
)
VR
)
N
N
EF
EF
EF
R
R
-V
-V
-V
P
P
EF
EF
EF
R
R
(V
(V
(V
¼
- Saturación de entrada
15.3.5 Muestreo diferencial

Además de muestreo de un solo extremo tradicional, el módulo ADC apoya muestreo diferencial de dos canales de entrada analógicos.
Para habilitar el muestreo diferencial, el software debe establecer el dn poco en el
ADCSSCTL0n registrarse en nibble la configuración de un paso.
Cuando un paso de secuencia está configurado para el muestreo diferencial, el par de entrada a la muestra se debe configurar en el ADCSSMUXn
registro. par diferencial 0 muestras entradas analógicas 0 y 1; diferencial
18 de junio 2014 1065

Analog-to-Digital Converter (ADC)
pair 1 samples analog inputs 2 and 3; and so on (see Table 15-6 on page 1066). The ADC does not support other
differential pairings such as analog input 0 with analog input 3.
Table 15-6. Differential Sampling Pairs
Differential Pair Analog Inputs
0 0 and 1
1 2 and 3
2 4 and 5
3 6 and 7
4 8 and 9
5 10 and 11
6 12 and 13
7 14 and 15
8 16 and 17
9 18 and 19
The voltage sampled in differential mode is the difference between the odd and even channels:
■ Input Positive Voltage: VIN+ = V IN_EVEN ( even channel)
■ Input Negative Voltage: VIN- = V IN_ODD ( odd channel) The input differential voltage is
defined as: VIN D = VIN+ - VIN-, therefore:
■ If VIN D = 0, then the conversion result = 0x800
■ If VIN D > 0, then the conversion result > 0x800 (range is 0x800–0xFFF)
■ If VIN D < 0, then the conversion result < 0x800 (range is 0–0x800)
When using differential sampling, the following definitions are relevant:
■ Input Common Mode Voltage: VIN CM = ( VIN+ + VIN-) / 2
■ Reference Positive Voltage: VREFP
■ Reference Negative Voltage: VREFN
■ Reference Differential Voltage: VREF D = VREFP - VREFN
■ Reference Common Mode Voltage: VREF CM = ( VREFP + VREFN) / 2 The following
conditions provide optimal results in differential mode:
■ Both V IN_EVEN and V IN_ODD must be in the range of (VREFP to VREFN) for a valid conversion result
■ The maximum possible differential input swing, or the maximum differential range, is: -VREF D to
+ VREF D, so the maximum peak-to-peak input differential signal is (+VREF D - - VREF D) = 2 * VREF D= 2 * (VREFP -
VREFN)
1066 June 18, 2014

Texas Instruments-Production Data
Tiva ™ TM4C1294NCPDT Microcontroller
■ In order to take advantage of the maximum possible differential input swing, VIN CM should be very close to VREF CM, see
Table 27-44 on page 1861. If VIN CM is not equal to VREF CM, the differential input signal may clip at either maximum or
minimum voltage, because either single ended input can never be larger than VREFP or smaller than VREFN, and it is not
possible to achieve full swing. Thus any difference in common mode between the input voltage and the reference voltage
limits the differential dynamic range of the ADC. Because the maximum peak-to-peak differential signal voltage is 2 *
(VREFP - VREFN), the ADC codes are interpreted as:
mV per ADC code = (2 *(VREFP - VREFN)) / 4096
Figure 15-10 shows how the differential voltage, ∆V, is represented in ADC codes.
Figure 15-10. Differential Voltage Representation
0xFFF
0x800
- (VREFP - VREFN) 0 VREFP - VREFN
- Input Saturation
15.3.6 Internal Temperature Sensor

The temperature sensor serves two primary purposes: 1) to notify the system that internal temperature is too high or low for
reliable operation and 2) to provide temperature measurements for calibration of the Hibernate module RTC trim value.
The temperature sensor does not have a separate enable, because it also contains the bandgap reference and must
always be enabled. The reference is supplied to other analog modules; not just the ADC. In addition, the temperature
sensor has a second power-down input in the 3.3 V domain which provides control by the Hibernation module.
The internal temperature sensor converts a temperature measurement into a voltage. This voltage value, V TSENS, is given
by the following equation (where TEMP is the temperature in °C):
V TSENS = 2.7 - ((TEMP + 55) / 75)
This relation is shown in Figure 15-11 on page 1068.
June 18, 2014 1067

Figure 15-11. Internal Temperature Sensor Characteristic
V TSENS
V TSENS = 2.7 V – (TEMP+55)
75
2.5 V
1.633 V
0.833 V
- 40° C 25° C 85° C Temp
The temperature sensor reading can be sampled in a sample sequence by setting the TSn bit in the ADCSSCTLn register.
The sample and hold width should be configured for at least 16 ADC clocks using the ADCSSTSHn register. The
temperature reading from the temperature sensor can also be given as a function of the ADC value. The following formula
calculates temperature (TEMP in ℃) based on the ADC reading (ADC CODE, given as an unsigned decimal number from 0 to
4095) and the maximum ADC voltage range (VREFP - VREFN):
TEMP = 147.5 - ((75 * (VREFP - VREFN) × ADC CODE) / 4096)
15.3.7 Digital Comparator Unit

An ADC is commonly used to sample an external signal and to monitor its value to ensure that it remains in a given range.
To automate this monitoring procedure and reduce the amount of processor overhead that is required, each module provides
eight digital comparators. Conversions from the ADC that are sent to the digital comparators are compared against the user
programmable limits in the ADC Digital Comparator Range (ADCDCCMPn) registers. The ADC can be configured to
generate an interrupt depending on whether the ADC is operating within the low, mid or high-band region configured in the ADCDCCMPn
bit fields. The digital comparators four operational modes (Once, Always, Hysteresis Once, Hysteresis Always) can be
additionally applied to the interrupt configuration.
15.3.7.1 Output Functions
ADC conversions can either be stored in the ADC Sample Sequence FIFOs or compared using the digital comparator
resources as defined by the SnDCOP bits in the ADC Sample Sequence n Operation (ADCSSOPn) register. These
selected ADC conversions are used by their respective digital comparator to monitor the external signal. Each comparator
has two possible output functions: processor interrupts and triggers.
Each function has its own state machine to track the monitored signal. Even though the interrupt and trigger functions
can be enabled individually or both at the same time, the same conversion
1068 June 18, 2014

data is used by each function to determine if the right conditions have been met to assert the associated output.
Interrupts
The digital comparator interrupt function is enabled by setting the CIE bit in the ADC Digital Comparator Control
(ADCDCCTLn) register. This bit enables the interrupt function state machine to start monitoring the incoming ADC
conversions. When the appropriate set of conditions is met, and the DCONSSx bit is set in the ADCIM register, an interrupt is
sent to the interrupt controller.
Note: For a 1 to 2 Msps rate, as the system clock frequency approaches the ADC clock frequency,
it is recommended that the application use the µDMA to store conversion data from the FIFO to memory before
processing rather than an interrupt-driven single data read. Using the µDMA to store multiple samples before
interrupting the processor amortizes interrupt overhead across multiple transfers and prevents loss of sample
data.
Note: Only a single DCONSSn bit should be set at any given time. Setting more than one of these
bits results in the INRDC bit from the ADCRIS register being masked, and no interrupt is generated on any of
the sample sequencer interrupt lines. It is recommended that when interrupts are used, they are enabled on
alternating samples or at the end of the sample sequence.
Triggers
The digital comparator trigger function is enabled by setting the CTE bit in the ADCDCCTLn register. This bit enables the
trigger function state machine to start monitoring the incoming ADC conversions. When the appropriate set of conditions is
met, the corresponding digital comparator trigger to the PWM module is asserted.
15.3.7.2 Operational Modes
Four operational modes are provided to support a broad range of applications and multiple possible signaling requirements:
Always, Once, Hysteresis Always, and Hysteresis Once. The operational mode is selected using the CIM or CTM field in the ADCDCCTLn
register.
Always Mode
In the Always operational mode, the associated interrupt or trigger is asserted whenever the ADC conversion value meets
its comparison criteria. The result is a string of assertions on the interrupt or trigger while the conversions are within the
appropriate range.
Once Mode
In the Once operational mode, the associated interrupt or trigger is asserted whenever the ADC conversion value meets
its comparison criteria, and the previous ADC conversion value did not. The result is a single assertion of the interrupt or
trigger when the conversions are within the appropriate range.
Hysteresis-Always Mode
The Hysteresis-Always operational mode can only be used in conjunction with the low-band or high-band regions because
the mid-band region must be crossed and the opposite region entered to clear the hysteresis condition. In the
Hysteresis-Always mode, the associated interrupt or trigger is asserted in the following cases: 1) the ADC conversion value
meets its comparison criteria or 2) a previous ADC conversion value has met the comparison criteria, and the hysteresis
condition has not been cleared by entering the opposite region. The result is a string of assertions on the interrupt or trigger
that continue until the opposite region is entered.
June 18, 2014 1069

Hysteresis-Once Mode
The Hysteresis-Once operational mode can only be used in conjunction with the low-band or high-band regions because
the mid-band region must be crossed and the opposite region entered to clear the hysteresis condition. In the
Hysteresis-Once mode, the associated interrupt or trigger is asserted only when the ADC conversion value meets its
comparison criteria, the hysteresis condition is clear, and the previous ADC conversion did not meet the comparison criteria.
The result is a single assertion on the interrupt or trigger.
15.3.7.3 Function Ranges
The two comparison values, COMP0 and COMP1, in the ADC Digital Comparator Range (ADCDCCMPn) register effectively
break the conversion area into three distinct regions. These regions are referred to as the low-band (less than COMP0), mid-band
(greater than COMP0 but less than or equal to COMP1), and high-band (greater than or equal to COMP1) regions. COMP0 and COMP1
may be programmed to the same value, effectively creating two regions, but COMP1 must always be greater than or equal to
the value of COMP0. A COMP1 value that is less than COMP0 generates unpredictable results.
Low-Band Operation
To operate in the low-band region, the CIC field or the CTC field in the ADCDCCTLn register must be programmed to 0x0.
This setting causes interrupts or triggers to be generated in the low-band region as defined by the programmed operational
mode. An example of the state of the interrupt/trigger signal in the low-band region for each of the operational modes is
shown in Figure 15-12 on page 1070. Note that a "0" in a column following the operational mode name (Always, Once,
Hysteresis Always, and Hysteresis Once) indicates that the interrupt or trigger signal is deasserted and a "1" indicates that
the signal is asserted.
Figure 15-12. Low-Band Operation (CIC=0x0 and/or CTC=0x0)
COMP0 COMP1
Hysteresis Once –
Always – 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1
Once – 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1
Hysteresis Always – 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1
1070 June 18, 2014

Mid-Band Operation
To operate in the mid-band region, the CIC field or the CTC field in the ADCDCCTLn register must be programmed to 0x1.
This setting causes interrupts or triggers to be generated in the mid-band region according the operation mode. Only the
Always and Once operational modes are available in the mid-band region. An example of the state of the interrupt/trigger
signal in the mid-band region for each of the allowed operational modes is shown in Figure 15-13 on page 1071. Note that a
"0" in a column following the operational mode name (Always or Once) indicates that the interrupt or trigger signal is
deasserted and a "1" indicates that the signal is asserted.
Figure 15-13. Mid-Band Operation (CIC=0x1 and/or CTC=0x1)
COMP0 COMP1
Hysteresis Once –
Always – 0
Once – 0
Hysteresis Always – - - - - - - - - - - - - - - - -
-00 -11 -10 -00 -00 -00 -11 -10 -10 -00 -00 -11 -10 -00 -00 -
High-Band Operation
To operate in the high-band region, the CIC field or the CTC field in the ADCDCCTLn register must be programmed to 0x3.
This setting causes interrupts or triggers to be generated in the high-band region according the operation mode. An example
of the state of the interrupt/trigger signal in the high-band region for each of the allowed operational modes is shown in Figure
15-14 on page 1072. Note that a "0" in a column following the operational mode name (Always, Once, Hysteresis Always,
and Hysteresis Once) indicates that the interrupt or trigger signal is deasserted and a "1" indicates that the signal is asserted.
June 18, 2014 1071

Figure 15-14. High-Band Operation (CIC=0x3 and/or CTC=0x3)
COMP0 COMP1
Hysteresis Once –
Always – 0 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1
Once – 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0
Hysteresis Always – 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1
0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0
15.4 Initialization and Configuration
15.4.1 Module Initialization

Initialization of the ADC module is a simple process with very few steps: enabling the clock to the ADC, disabling the
analog isolation circuit associated with all inputs that are to be used, and reconfiguring the sample sequencer priorities (if
needed). The initialization sequence for the ADC is as follows:
1. Enable the ADC clock using the RCGCADC register (see page 396).
2. Enable the clock to the appropriate GPIOmodules via the RCGCGPIO register (see page 382).
To find out which GPIO ports to enable, refer to “Signal Description” on page 1055.
3. Set the GPIO AFSEL bits for the ADC input pins (see page 770). To determine which GPIOs to
configure, see Table 26-4 on page 1797.
4. Configure the AINx signals to be analog inputs by clearing the corresponding DEN bit in the
GPIO Digital Enable (GPIODEN) register (see page 781).
5. Disable the analog isolation circuit for all ADC input pins that are to be used by writing a 1 to
the appropriate bits of the GPIOAMSEL register (see page 786) in the associated GPIO block.
6. If required by the application, reconfigure the sample sequencer priorities in the ADCSSPRI
register. The default configuration has Sample Sequencer 0 with the highest priority and Sample Sequencer 3 as the
lowest priority.
1072 June 18, 2014

15.4.2 Sample Sequencer Configuration

Configuration of the sample sequencers is slightly more complex than the module initialization because each sample
sequencer is completely programmable. The configuration for each sample sequencer should be as follows:
1. Ensure that the sample sequencer is disabled by clearing the corresponding ASENn bit in the
ADCACTSS register. Programming of the sample sequencers is allowed without having them enabled. Disabling the
sequencer during programming prevents erroneous execution if a trigger event were to occur during the configuration
process.
2. Configure the trigger event for the sample sequencer in the ADCEMUX register.
3. When using a PWM generator as the trigger source, use the ADC Trigger Source Select
(ADCTSSEL) register to specify in which PWM module the generator is located. The default register reset selects
PWM module 0 for all generators.
4. For each sample in the sample sequence, configure the corresponding input source in the
ADCSSMUXn and ADCSSEMUXn registers.
5. For each sample in the sample sequence, configure the sample control bits in the corresponding
nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit is set. Failure to set the END
bit causes unpredictable behavior.
6. If interrupts are to be used, set the corresponding MASK bit in the ADCIM register.
7. Enable the sample sequencer logic by setting the corresponding ASENn bit in the ADCACTSS
register.
15.5 Register Map

Table 15-7 on page 1073 lists the ADC registers. The offset listed is a hexadecimal increment to the register's address,
relative to that ADC module's base address of:
■ ADC0: 0x4003.8000
■ ADC1: 0x4003.9000
Note that the ADC module clock must be enabled before the registers can be programmed (see page 396). There must be a
delay of 3 system clocks after the ADC module clock is enabled before any ADC module registers are accessed.
Table 15-7. ADC Register Map
See
Offset Name Type Reset Description
page
0x000 ADCACTSS 0x0000.0000 RW ADC Active Sample Sequencer 1077
0x004 ADCRIS 0x0000.0000 RO ADC Raw Interrupt Status 1079
0x008 ADCIM 0x0000.0000 RW ADC Interrupt Mask 1082
0x00C ADCISC RW1C 0x0000.0000 ADC Interrupt Status and Clear 1085
0x010 ADCOSTAT RW1C 0x0000.0000 ADC Overflow Status 1089
0x014 ADCEMUX 0x0000.0000 RW ADC Event Multiplexer Select 1091
June 18, 2014 1073

Table 15-7. ADC Register Map ( continued)
See
page
0x018 ADCUSTAT RW1C 0x0000.0000 ADC Underflow Status 1096
0x01C ADCTSSEL 0x0000.0000 RW ADC Trigger Source Select 1097
0x020 ADCSSPRI 0x0000.3210 RW ADC Sample Sequencer Priority 1099
0x024 ADCSPC 0x0000.0000 RW ADC Sample Phase Control 1101
0x028 ADCPSSI RW - ADC Processor Sample Sequence Initiate 1103
0x030 ADCSAC 0x0000.0000 RW ADC Sample Averaging Control 1105
0x034 ADCDCISC RW1C 0x0000.0000 ADC Digital Comparator Interrupt Status and Clear 1106
0x038 ADCCTL 0x0000.0000 RW ADC Control 1108
0x040 ADCSSMUX0 0x0000.0000 RW ADC Sample Sequence Input Multiplexer Select 0 1109
0x044 ADCSSCTL0 0x0000.0000 RW ADC Sample Sequence Control 0 1111
0x048 ADCSSFIFO0 RO - ADC Sample Sequence Result FIFO 0 1118
0x04C ADCSSFSTAT0 0x0000.0100 RO ADC Sample Sequence FIFO 0 Status 1119
0x050 ADCSSOP0 0x0000.0000 RW ADC Sample Sequence 0 Operation 1121
0x054 ADCSSDC0 0x0000.0000 RW ADC Sample Sequence 0 Digital Comparator Select 1123
ADCSample Sequence Extended Input Multiplexer Select 0

0x058 ADCSSEMUX0 0x0000.0000 RW 1125
0x05C ADCSSTSH0 0x0000.0000 RW ADC Sample Sequence 0 Sample and Hold Time 1127

0x078 ADCSSEMUX1 0x0000.0000 RW 1137
1074 June 18, 2014

Table 15-7. ADC Register Map ( continued)
See
page

0x098 ADCSSEMUX2 0x0000.0000 RW 1137
0x0A0 ADCSSMUX3 0x0000.0000 RW ADC Sample Sequence Input Multiplexer Select 3 1141
0x0A4 ADCSSCTL3 0x0000.0000 RW ADC Sample Sequence Control 3 1142
0x0A8 ADCSSFIFO3 RO - ADC Sample Sequence Result FIFO 3 1118
0x0ACADCSSFSTAT3 0x0000.0100 RO ADC Sample Sequence FIFO 3 Status 1119
0x0B0 ADCSSOP3 0x0000.0000 RW ADC Sample Sequence 3 Operation 1144
0x0B4 ADCSSDC3 0x0000.0000 RW ADC Sample Sequence 3 Digital Comparator Select 1145

0x0B8 ADCSSEMUX3 0x0000.0000 RW 1146
0x0BCADCSSTSH3 0x0000.0000 RW ADC Sample Sequence 3 Sample and Hold Time 1147
0xD00 ADCDCRIC WO 0x0000.0000 ADC Digital Comparator Reset Initial Conditions 1148
0xE00 ADCDCCTL0 0x0000.0000 RW ADC Digital Comparator Control 0 1153
0xE0CADCDCCTL3 0x0000.0000 RW ADC Digital Comparator Control 3 1153
0xE1CADCDCCTL7 0x0000.0000 RW ADC Digital Comparator Control 7 1153
0xE40 ADCDCCMP0 0x0000.0000 RW ADC Digital Comparator Range 0 1156
0xE4CADCDCCMP3 0x0000.0000 RW ADC Digital Comparator Range 3 1156
0xE5CADCDCCMP7 0x0000.0000 RW ADC Digital Comparator Range 7 1156
0xFC0 ADCPP 0x01B0.2147 RO ADC Peripheral Properties 1157
0xFC4 ADCPC 0x0000.0007 RW ADC Peripheral Configuration 1159
0xFC8 ADCCC 0x0000.0001 RW ADC Clock Configuration 1160
June 18, 2014 1075

15.6 Register Descriptions

The remainder of this section lists and describes the ADC registers, in numerical order by address offset.
1076 June 18, 2014

Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000

This register controls the activation of the sample sequencers. Each sample sequencer can be enabled or disabled
independently.
ADC Active Sample Sequencer (ADCACTSS)

ADC0 base: 0x4003.8000 ADC1
base: 0x4003.9000 Offset 0x000
Type RW, reset 0x0000.0000
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved BUSY
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type RO
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved ADEN1 ADEN2 ADEN3

ADEN0 reserved ASEN1 ASEN2 ASEN3
ASEN0
RW RW RW RO RO RO RO RW RW RW RW RO RO RO RO Type RW
Reset 000000000000000 0
Bit/Field Name Type Reset Description
31:17 reserved RO future

operation.
Software
products,
0 should
the not
value
relyofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
across
compatibility
a read-modify-write
with
16 BUSY RO 0 ADC Busy
Value
Description
ADC is idle 0
ADC is busy 1
Note: In order to use the BUSY bit, the ADC Event Multiplexer Select
(ADCEMUX) register must be programmed such that no trigger is selected
(bit field encoding is 0xE). The NEVER encoding in the ADCEMUX register
allows the ADC to safely be put in Deep-Sleep mode.

operation.
Software
products,
0 should
the not
value
relyofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
across
compatibility
a read-modify-write
with
11 ADEN3 RW ADC SS3 DMA Enable
Value
Description
DMA for Sample Sequencer 3 is disabled. 0
DMA for Sample Sequencer 3 is enabled. 1 0
Value
Description
June 18, 2014 1077

Value
Description
Value
Description

operation.
Software
products,
0 should
the not
value
relyofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
across
compatibility
a read-modify-write
with
3 ASEN3 RW ADC SS3 Enable
Value
Description
Sample Sequencer 3 is disabled. 0
Sample Sequencer 3 is enabled. 1 0
Value
Description
Value
Description
Value
Description
1078 June 18, 2014

Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004

This register shows the status of the raw interrupt signal of each sample sequencer. These bits may be polled by software to
look for interrupt conditions without sending the interrupts to the interrupt controller.
ADC Raw Interrupt Status (ADCRIS)

Type RO, reset 0x0000.0000
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved INRDC
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved DMAINR1 DMAINR2 DMAINR3

DMAINR0 reserved INR1 INR2 INR3 INR0
Reset 000000000000000 0
31:17 reserved future products,

operation.
Software
0x000the
RO
should
valuenot
of arely
reserved
on the bit
value
should
of abe
reserved
preserved
bit. To
across
provide
a read-modify-write
compatibility with
16 INRDC RO Digital Comparator Raw Interrupt Status
Value
Description
comparator interrupt
All bits has occurred.
in the ADCDCISC 1 0 are clear. 0
register
At least one bit in the ADCDCISC register is set, meaning that a digital

operation.
Software
products,
0 should
the not
value
relyofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
across
compatibility
a read-modify-write
with
11 DMAINR3 RO SS3 DMA Raw Interrupt Status
Value
Description
The DMA interrupt has not occurred. 0
The sample sequence 3 DMA interrupt is asserted. 1
This bit is cleared by writing a 1 to the DMAINR3 bit in the ADCISC

register. 0
Value
Description

register. 0
June 18, 2014 1079

Value
Description

register. 0
Value
Description

register. 0

operation.
Software
products,
0 should
the not
value
relyofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
across
compatibility
a read-modify-write
with
3 INR3 RO SS3 Raw Interrupt Status
Value
Description
An interrupt has not occurred. 0
A sample has completed conversion and the respective

ADCSSCTL3 IEn bit is set, enabling a raw interrupt. 1
This bit is cleared by writing a 1 to the IN3 bit in the ADCISC register. 0
Value
Description

Value
Description

1080 June 18, 2014

Value
Description

June 18, 2014 1081

Register 3: ADC Interrupt Mask (ADCIM), offset 0x008

This register controls whether the sample sequencer and digital comparator raw interrupt signals are sent to the interrupt
controller. Each raw interrupt signal can be masked independently.
Note: For a 1 to 2 Msps rate, as the system clock frequency approaches the ADC clock frequency,
it is recommended that the application use the µDMA to store conversion data from the FIFO to memory before
processing rather than an interrupt-driven single data read. Using the µDMA to store multiple samples before
interrupting the processor amortizes interrupt overhead across multiple transfers and prevents loss of sample
data.
Note: Only a single DCONSSn bit should be set at any given time. Setting more than one of these
bits results in the INRDC bit from the ADCRIS register being masked, and no interrupt is generated on any of
the sample sequencer interrupt lines. It is recommended that when interrupts are used, they are enabled on
alternating samples or at the end of the sample sequence.
ADC Interrupt Mask (ADCIM)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved DCONSS1 DCONSS2DCONSS0

DCONSS3
RW RW RW RO RO RO RO RO RO RO RO RO RO RO RO Type RW
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved DMAMASK3 DMAMASK2 DMAMASK1 DMAMASK0 reserved MASK1 MASK2 MASK3

MASK0
RW RW RW RO RO RO RO RW RW RW RW RO RO RO RO Type RW
Reset 000000000000000 0

operation.
Software
0x000the
RO
should
valuenot
of arely
reserved
on the bit
value
should
of abe
reserved
preserved
bit. To
across
provide
a read-modify-write
compatibility with
19 DCONSS3 RW Digital Comparator Interrupt on SS3
Value
Description
0 The status of the digital comparators does not affect the SS3 interrupt status.
line. 1 0
The raw interrupt signal from the digital comparators ( INRDC

bit in the ADCRIS register) is sent to the interrupt controller on the SS3 interrupt
Value
Description
line. 1 0

1082 June 18, 2014

Value
Description
line. 1 0

Value
Description
line. 1 0


operation.
Software
products,
0 should
the not
value
relyofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
across
compatibility
a read-modify-write
with
11 DMAMASK3 RW SS3 DMA Interrupt Mask
Value
Description
status.
The 0status of Sample Sequencer 3 DMA does not affect the SS3 interrupt
bit) is sent to the interrupt controller. 1 0
The raw interrupt signal from Sample Sequencer 3 DMA ( ADCRIS register DMAINR3
Value
Description
status.
Value
Description
status.
June 18, 2014 1083

Value
Description
status.

operation.
Software
products,
0 should
the not
value
relyofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
across
compatibility
a read-modify-write
with
3 MASK3 RW SS3 Interrupt Mask
Value
Description
0 The status of Sample Sequencer 3 does not affect the SS3 interrupt status.
The raw interrupt signal from Sample Sequencer 3 ( ADCRIS

register INR3 bit) is sent to the interrupt controller. 1 0
Value
Description

Value
Description

Value
Description

1084 June 18, 2014

Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C

This register provides themechanism for clearing sample sequencer interrupt conditions and shows the status of interrupts
generated by the sample sequencers and the digital comparators which have been sent to the interrupt controller. When
read, each bit field is the logical AND of the respective
INR and MASK bits. Sample sequencer interrupts are cleared by writing a 1 to the corresponding bit position. Digital
comparator interrupts are cleared by writing a 1 to the appropriate bits in the
ADCDCISC register. If software is polling the ADCRIS instead of generating interrupts, the sample sequence INRn bits are
still cleared via the ADCISC register, even if the INn bit is not set.
ADC Interrupt Status and Clear (ADCISC)

base: 0x4003.9000 Offset 0x00C
Type RW1C, reset 0x0000.0000
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved DCINSS1 DCINSS2 DCINSS3

DCINSS0
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved DMAIN1 DMAIN2 DMAIN3

DMAIN0 reserved IN1 IN2 IN3 IN0
RW1C RW1C RW1C RO RO RO RO Type RW1C RW1C RW1C RW1C RO RO RO RO RW1C

Reset 000000000000000 0

operation.
Software
0x000the
RO
should
valuenot
of arely
reserved
on the bit
value
should
of abe
reserved
preserved
bit. To
across
provide
a read-modify-write
compatibility with
19 DCINSS3 RO Digital Comparator Interrupt Status on SS3
Value
Description
No interrupt has occurred or the interrupt is masked. 0
Both the INRDC bit in the ADCRIS register and the DCONSS3
interrupt controller. 1
bit in the ADCIM register are set, providing a level-based interrupt to the
This bit is cleared by writing a 1 to it. Clearing this bit also clears the
INRDC bit in the ADCRIS register. 0
Value
Description
June 18, 2014 1085

Value
Description
Value
Description

operation.
Software
products,
0 should
the not
value
relyofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
across
compatibility
a read-modify-write
with
11 DMAIN3 RW1C SS3 DMA Interrupt Status and Clear
Value
Description
Both the DMAINR3 bit in the ADCRIS register and the DMAMASK3
This bit is cleared by writing a 1. Clearing this bit also clears the
DMAINR3 bit in the ADCRIS register. 0
Value
Description
1086 June 18, 2014

Value
Description
Value
Description

operation.
Software
products,
0 should
the not
value
relyofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
across
compatibility
a read-modify-write
with
3 IN3 RW1C SS3 Interrupt Status and Clear
Value
Description
areBoth
set,the
providing
INR3 bit
a level-based
in the ADCRIS
interrupt
register
to the
andinterrupt
the MASK3controller.
bit in the
1 ADCIM register
This bit is cleared by writing a 1. Clearing this bit also clears the INR3
bit in the ADCRIS register. 0
Value
Description
areBoth
set,the
providing
INR2 bit
a level-based
in the ADCRIS
interrupt
register
to the
andinterrupt
bit in the
1 ADCIM register
June 18, 2014 1087

Value
Description
areBoth
set,the
providing
INR1 bit
a level-based
in the ADCRIS
interrupt
register
to the
andinterrupt
bit in the
1 ADCIM register
Value
Description
areBoth
set,the
providing
INR0 bit
a level-based
in the ADCRIS
interrupt
register
to the
andinterrupt
bit in the
1 ADCIM register
1088 June 18, 2014

Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010

This register indicates overflow conditions in the sample sequencer FIFOs. Once the overflow condition has been
handled by software, the condition can be cleared by writing a 1 to the corresponding bit position.
ADC Overflow Status (ADCOSTAT)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved OV1 OV2 OV3 OV0
RW1C RW1C RW1C RO RO RO RO RO RO RO RO RO RO RO RO Type RW1C

Reset 000000000000000 0
31:4 reserved 0x0000.000 RO Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
3 OV3 RW1C SS3 FIFO Overflow
Value
Description
The FIFO has not overflowed. 0
theThe
mostFIFO
recent
FIFO
is full
write
for and
Sample
is adropped.
write
Sequencer
was
1 requested.
3 has hit
When
an overflow
an overflow
condition,
is detected,
meaning
thethat
This bit is cleared by writing a 1. 0
Value
Description
theThe
mostFIFO
recent
FIFO
is full
write
for and
Sample
is adropped.
write
Sequencer
was
1 requested.
2 has hit
When
an overflow
an overflow
condition,
is detected,
meaning
thethat
Value
Description
theThe
mostFIFO
recent
FIFO
is full
write
for and
Sample
is adropped.
write
Sequencer
was
1 requested.
1 has hit
When
an overflow
an overflow
condition,
is detected,
meaning
thethat
June 18, 2014 1089

Value
Description
theThe
mostFIFO
recent
FIFO
is full
write
for and
Sample
is adropped.
write
Sequencer
was
1 requested.
0 has hit
When
an overflow
an overflow
condition,
is detected,
meaning
thethat
1090 June 18, 2014

Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014

The ADCEMUX selects the event (trigger) that initiates sampling for each sample sequencer. Each sample sequencer can
be configured with a unique trigger source.
ADC Event Multiplexer Select (ADCEMUX)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
EM3 EM2 EM1 EM0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type RW
Reset 000000000000000 0
31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with
June 18, 2014 1091

15:12 EM3 RW SS3 Trigger Select
This field selects the trigger source for Sample Sequencer 3. The valid
configurations for this field are:
Value Event
0x0 Processor (default) The trigger is initiated by setting the SSn bit in the ADCPSSI
register.
Control
Analog0 (ACCTL0)
Comparator
register
0 This (page
trigger1665).
is configured
0x1 by the AnalogComparator
Control
Analog1 (ACCTL1)
Comparator
register
1 This (page
trigger1665).
is configured
Control
Analog2 (ACCTL2)
Comparator
register
2 This (page
trigger1665).
is configured
External (GPIO Pins)

(see “ADCTrigger Source” on page 750). 0x4
This trigger is connected to the GPIO interrupt for the correspondingGPIO
Timer
register (page 986). 0x5
In addition, the trigger must be enabled with the TnOTE bit in the GPTMCTL
PWM generator 0
0x6 The PWM generator 0 trigger can be configured with the
PWM0 Interrupt and Trigger Enable (PWM0INTEN) register (page 1713).
PWM generator 1
The PWM generator 1 trigger can be configured with the

PWM1INTEN register (page 1713). 0x7
PWM generator 2

PWM generator 3

0xA-0xD
reserved
Never Trigger (No triggers are allowed to the ADC digital interface) 0xE
Always (continuously sample) 0xF 0x0
1092 June 18, 2014

Value Event
register.
Control
Analog0 (ACCTL0)
Comparator
register
0 This (page
trigger1665).
is configured
Control
Analog1 (ACCTL1)
Comparator
register
1 This (page
trigger1665).
is configured
Control
Analog2 (ACCTL2)
Comparator
register
2 This (page
trigger1665).
is configured

Timer
PWM generator 0
PWM generator 1

PWM generator 2

PWM generator 3

0xA-0xD
reserved
June 18, 2014 1093

Value Event
register.
Control
Analog0 (ACCTL0)
Comparator
register
0 This (page
trigger1665).
is configured
Control
Analog1 (ACCTL1)
Comparator
register
1 This (page
trigger1665).
is configured
Control
Analog2 (ACCTL2)
Comparator
register
2 This (page
trigger1665).
is configured

Timer
PWM generator 0
PWM generator 1

PWM generator 2

PWM generator 3

0xA-0xD
reserved
1094 June 18, 2014

This field selects the trigger source for Sample Sequencer 0 The valid
Value Event
register.
Control
Analog0 (ACCTL0)
Comparator
register
0 This (page
trigger1665).
is configured
Control
Analog1 (ACCTL1)
Comparator
register
1 This (page
trigger1665).
is configured
Control
Analog2 (ACCTL2)
Comparator
register
2 This (page
trigger1665).
is configured

Timer
PWM generator 0
PWM generator 1

PWM generator 2

PWM generator 3

0xA-0xD
reserved
June 18, 2014 1095

Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018

This register indicates underflow conditions in the sample sequencer FIFOs. The corresponding underflow condition is
cleared by writing a 1 to the relevant bit position.
ADC Underflow Status (ADCUSTAT)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved UV1 UV2 UV3 UV0
RW1C RW1C RW1C RO RO RO RO RO RO RO RO RO RO RO RO Type RW1C

Reset 000000000000000 0
3 UV3 RW1C SS3 FIFO Underflow
The valid configurations for this field are shown below. This bit is cleared by writing a 1.
read does not move the FIFO pointers, and 0s are returned. 1 0
Value
Description
meaning
The that
FIFOthe FIFO
has is empty and a
not underflowed. 0 read was requested. The problematic
The FIFO for the Sample Sequencer has hit an underflow condition,

writing a 1. 0
The valid configurations are the same as those for the UV3 field. This bit is cleared by

writing a 1. 0

writing a 1. 0
1096 June 18, 2014

Register 8: ADC Trigger Source Select (ADCTSSEL), offset 0x01C

If a PWM Generator n is selected as a trigger source through the EMn bit field in the ADC Event Multiplexer Select
(ADCEMUX) register, the ADCTSSEL register is programmed to identify in which PWM module instance the generator
creating the trigger is located. The register resets to 0x0000.0000, which selects PWMmodule 0 for all generators. Note that
field PS3 selects the PWM module that maps to Generator 3; PS2 selects the PWM module that maps to Generator 2, and
so on.
ADC Trigger Source Select (ADCTSSEL)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved PS3 reserved PS2 reserved
RO RO RO RW RW RO RO RO RO RO RO RW RW RO RO Type RO
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved PS1 reserved PS0 reserved
RO RO RO RW RW RO RO RO RO RO RO RW RW RO RO Type RO
Reset 000000000000000 0

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
29:28 PS3 RW Generator 3 PWM Module Trigger Select This field selects in which PWMmodule the
generator 3 trigger is located.
0x1-0x3 0x0 Description

Value
Use Generator 3 (and its trigger) in PWM module 0 0x0
reserved

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
21:20 PS2 RW Generator 2 PWM Module Trigger Select This field selects in which PWM module
the Generator 2 trigger is located.
0x1-0x3 0x0
Value Description
reserved

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
June 18, 2014 1097

0x1-0x3 0x0
Value Description
reserved

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
0x1-0x3 0x0
Value Description
reserved

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
1098 June 18, 2014

Register 9: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020

This register sets the priority for each of the sample sequencers. Out of reset, Sequencer 0 has the highest priority, and
Sequencer 3 has the lowest priority. When reconfiguring sequence priorities, each sequence must have a unique priority for
the ADC to operate properly.
ADC Sample Sequencer Priority (ADCSSPRI)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved SS3 reserved SS2 reserved SS1 reserved SS0
RW RO RO RW RW RO RO RW RW RO RO RW RW RO RO Type RW
Reset 000100001001100 0
31:14 reserved RO 0x0000.0 Software should not rely on the value of a reserved bit. To provide compatibility with
13:12 SS3 RW SS3 Priority

ifassigned
two or more fields are equal.
to the 0x3be uniquely mapped. The ADC may not operate properly
Sequencer
This field 3. A sequencers
priority
contains
must
encoding of 0x0value
a binary-encoded is highest and 0x3 the
that specifies is lowest.
priorityThe priorities
encoding of Sample

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with

ifassigned
Sequencer
priority
contains
must
encoding of Sample

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with

ifassigned
Sequencer
priority
contains
must
encoding of Sample

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
June 18, 2014 1099


ifassigned
Sequencer
priority
contains
must
encoding of Sample
1100 June 18, 2014

Register 10: ADC Sample Phase Control (ADCSPC), offset 0x024

The ADC Sample Phase Control (ADCSPC) register is used to insert a delay in ADC module sampling. This feature can be
used with the SYNCWAIT and GSYNC bit in the ADCPSSI register to provide concurrent sampling of two different signals by
two different ADC modules or skewed sampling of two ADC modules to increase the effective sampling rate. For concurrent
sampling, the
PHASE field of each ADC module must be the same and the sample and hold times ( TSHn) for the matching sample steps of
each ADC must be the same. For example, both ADC0 and ADC1 would program PHASE = 0x0 in the ADCSPC register and
might both have the following configuration for their ADCSSTSH0 register:
■ TSH7= 0x4
■ TSH6= 0x2
■ TSH5= 0x2
■ TSH4= 0x8
■ TSH3= 0x6
■ TSH2= 0x2
■ TSH1= 0x4
■ TSH0= 0x2
For skewed sampling with a consistent phase lag, the TSHn field in the ADCSSTSHn register must be the same for all
sample steps of an ADC and for both ADC Modules. The desired lag can be calculated by adding the sample and hold time ( TSHn)
to the twelve clock conversion time to determine the total number of clocks in a sample period. For example to create a
180.0° phase lag, the PHASE of the lagging ADC is calculated as: PHASE = ( TSHn+ 12)/2, where TSHn is in ADC_Clocks
For situations where a predictable phase lag is not required, sample and hold times (TSHn) of ADC modules can vary.
Note: Care should be taken when the PHASE field is non-zero, as the resulting delay in sampling
the AINx input may result in undesirable system consequences. The time fromADC trigger to sample is increased
and could make the response time longer than anticipated. The added latency could have ramifications in the
system design. Designers should carefully consider the impact of this delay.
June 18, 2014 1101

ADC Sample Phase Control (ADCSPC)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved PHASE
Reset 000000000000000 0
3:0 PHASE RW Phase Lag
This field selects the sample phase lag from the standard sample time.
Value
Description
The ADC samples are concurrent. 0x0
The ADC sample lags by 1 ADC clock 0x1
The ADC sample lags by 2 ADC clocks 0x2
The ADC sample lags by 3 ADC clocks 0x3
The ADC sample lags by 4 clocks 0x4
The ADC sample lags by 10 clocks 0xA
The ADC sample lags by 11 clocks 0xB
The ADC sample lags by 12 clocks 0xC
The ADC sample lags by 13 clocks 0xD
The ADC sample lags by 14 clocks 0xE
The ADC sample lags by 15 clocks 0xF 0x0
1102 June 18, 2014

Register 11: ADCProcessor Sample Sequence Initiate (ADCPSSI), offset 0x028

This register provides a mechanism for application software to initiate sampling in the sample sequencers. Sample
sequences can be initiated individually or in any combination. When multiple sequences are triggered simultaneously, the
priority encodings in ADCSSPRI dictate execution order.
This register also provides a means to configure and then initiate concurrent sampling on all ADC modules. To do this, the
first ADC module should be configured. The ADCPSSI register for that module should then be written. The appropriate SS bits
should be set along with the SYNCWAIT bit. Additional ADC modules should then be configured following the same
procedure. Once the final ADC module is configured, its ADCPSSI register should be written with the appropriate SS bits set
along with the GSYNC bit. All of the ADC modules then begin concurrent sampling according to their configuration.
ADC Processor Sample Sequence Initiate (ADCPSSI)

Type RW, reset -
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
GSYNC reserved SYNCWAIT reserved
RO RO RO RO RO RO RO RO RO RO RW RO RO RO RW Type RO
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved SS1 SS2 SS3 SS0
WO WO WO RO RO RO RO RO RO RO RO RO RO RO RO Type WO
Reset 00000000000 0 - - - -
31 GSYNC RW Global Synchronize
Value
Description
This bit is cleared once sampling has been initiated. 0
This bit initiates sampling in multiple ADCmodules at the same time. Any ADC
module that has been initialized by setting an
SSn bit and the SYNCWAIT bit starts sampling once this bit is written. 1 0

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
27 SYNCWAIT RW Synchronize Wait
Value
Description
bit is set. 10
Sampling begins when a sample sequence has been initiated. 0
This bit allows the sample sequences to be initiated, but delays sampling until the GSYNC
June 18, 2014 1103

3 SS3 WO - SS3 Initiate
Value
Description
No effect. 0
register.
Begin1sampling on Sample Sequencer 3, if the sequencer is enabled in the ADCACTSS
Only a write by software is valid; a read of this register returns no meaningful data.
Value
Description
No effect. 0
register.
Value
Description
No effect. 0
register.
Value
Description
No effect. 0
register.
1104 June 18, 2014

Register 12: ADC Sample Averaging Control (ADCSAC), offset 0x030

This register controls the amount of hardware averaging applied to conversion results. The final conversion result stored in
the FIFO is averaged from2 AVG consecutive ADC samples at the specified ADC speed. If AVG is 0, the sample is passed
directly through without any averaging. If AVG=6, then 64 consecutive ADC samples are averaged to generate one result in
the sequencer FIFO. An AVG=7 provides unpredictable results.
ADC Sample Averaging Control (ADCSAC)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved AVG
RW RW RO RO RO RO RO RO RO RO RO RO RO RO RO Type RW
Reset 000000000000000 0
2:0 AVG RW Hardware Averaging Control
Specifies the amount of hardware averaging that will be applied to ADC samples. The AVG
field can be any value between 0 and 6. Entering a value of 7 creates unpredictable
results.
Value
Description
No hardware oversampling 0x0
0x7 0x0 2x hardware oversampling 0x1
4x hardware oversampling 0x2
reserved
June 18, 2014 1105

Register 13: ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034
This register provides status and acknowledgement of digital comparator interrupts. One bit is provided for each
comparator.
ADC Digital Comparator Interrupt Status and Clear (ADCDCISC)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved DCINT1 DCINT2 DCINT3 DCINT4 DCINT5 DCINT6DCINT0

DCINT7
RW1C RW1C RW1C RW1C RW1C RW1C RW1C RO RO RO RO RO RO RO RO Type RW1C

Reset 000000000000000 0
7 DCINT7 RW1C Digital Comparator 7 Interrupt Status and Clear
Value
Description
No interrupt. 0
Digital Comparator 7 has generated an interrupt. 1
Value
Description
No interrupt. 0
Value
Description
No interrupt. 0
1106 June 18, 2014

Value
Description
No interrupt. 0
Value
Description
No interrupt. 0
Value
Description
No interrupt. 0
Value
Description
No interrupt. 0
Value
Description
No interrupt. 0
June 18, 2014 1107

Register 14: ADC Control (ADCCTL), offset 0x038

This register configures the voltage reference. The voltage references for the conversion can be
VREFA+ and GNDA or VDDA and GNDA. Note that values set in this register apply to all ADCmodules, it is not possible to set one
module to use internal references and another to use external references.
ADC Control (ADCCTL)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved VREF
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type RW
Reset 000000000000000 0
0 VREF RW Voltage Reference Select
Value
Description
0x1 0x0 VDDA and GNDA are the voltage references for all ADCmodules. 0x0
The external VREFA+ and GNDA are the voltage references for all ADC modules.
1108 June 18, 2014

Register 15: ADCSample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040
This register, along with the ADCSSEMUX0 register, defines the analog input configuration for each sample in a sequence
executed with Sample Sequencer 0. If the corresponding EMUXn bit in the
ADCSSEMUX0 register is set, the MUXn field in this register selects from AIN[19:16]. When the corresponding EMUXn bit is
clear, the MUXn field selects from AIN[15:0]. This register is 32 bits wide and contains information for eight possible
samples.
Note: Channels AIN[31:20] do not exist on this microcontroller. Configuring MUXn to be 0xC-0xF
when the corresponding EMUXn bit is set results in undefined behavior.
ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
MUX7 MUX6 MUX5 MUX4
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
MUX3 MUX2 MUX1 MUX0
Reset 000000000000000 0
31:28 MUX7 RW 8th Sample Input Select The MUX7 field is used during the eighth sample of a sequence
executed with the sample sequencer. It specifies which of the analog inputs is sampled for
the analog-to-digital conversion. The value set here indicates the corresponding pin, for
example, a value of 0x1 when EMUX7 is clear indicates the input is AIN1. A value of 0x1
when EMUX7 is set indicates the input is AIN17.
must be set to the pair number "i", where the paired inputs are "2i and 2i+1". 0x0
If differential sampling is enabled (the D7 bit in the ADCSSCTL0 register is set), this field
27:24 MUX6 RW sequence

sampled
7th Sample
for
executed
theInput
analog-to-digital
with
Select
theThe
sample
MUX6
conversion.
sequencer.
field is 0x0
used
It specifies
during the
which
seventh
of the
sample
analogofinputs
a is
23:20 MUX5 RW executed

the6th
analog-to-digital
Sample
with the
Input
sample
Select
conversion.
sequencer.
The MUX5
0x0 Itfield
specifies
is used
which
during
of the sixth
analogsample
inputsofisasampled
sequence
for

the5th
analog-to-digital
Sample
with the
Input
sample
Select
conversion.
sequencer.
The MUX4
0x0 Itfield
specifies
is used
which
during
of the fifth
analogsample
inputs
of isa sampled
sequencefor
June 18, 2014 1109


the4th
analog-to-digital
Sample
with the
Input
sample
Select
conversion.
sequencer.
The MUX3
0x0 Itfield
specifies
is used
which
during
of the fourth
analogsample
inputs is
of sampled
a sequence
for

the3rd
analog-to-digital
Sample
with the
Input
sample
Select
conversion.
sequencer.
The MUX2
0x0 Itfield
specifies
is used
which
during
of the analog
third sample
inputsofisasampled
sequence
for
7:4 MUX1 RW sequence

sampled
2nd Sample
for
executed
theInput
analog-to-digital
with
Select
theThe
sample
MUX1
conversion.
sequencer.
field is0x0
used
It specifies
during the
which
second
of the
sample
analogofinputs
a is

the1st
analog-to-digital
Sample
with the
Inputsample
Select
conversion.
sequencer.
The MUX0
0x0 Itfield
specifies
is used
which
during
of the first
analogsample
inputs
of is
a sampled
sequencefor
1110 June 18, 2014

Register 16: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044

This register contains the configuration information for each sample for a sequence executed with a sample sequencer.
When configuring a sample sequence, the END bit must be set for the final sample, whether it be after the first sample,
eighth sample, or any sample in between. This register is 32 bits wide and contains information for eight possible samples.
ADC Sample Sequence Control 0 (ADCSSCTL0)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
IE7 TS7 END7 IE6 TS6 D7 END6 IE5 TS5 D6 END5 IE4 TS4 D5 END4 D4
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
Reset 000000000000000 0
31 TS7 RW 8th Sample Temp Sensor Select
Value
Description
eighth
Thesample
input pin
ofspecified
the sample
by sequence.
the ADCSSMUXn
0 register is read during the
sequence. 1 0
The temperature sensor is read during the eighth sample of the sample
30 IE7 RW 8th Sample Interrupt Enable
Value
Description
The raw interrupt is not asserted to the interrupt controller. 0
The raw interrupt signal ( INR0 bit) is asserted at the end of the eighth sample's
conversion. If the MASK0 bit in the ADCIM
register is set, the interrupt is promoted to the interrupt controller. 1
It is legal to havemultiple samples within a sequence generate interrupts. 0
29 END7 RW 8th Sample is End of Sequence
Value
Description
Another
are not requested forsample in theeven
conversion sequence
thoughisthe
thefields
final may
sample. 0
be non-zero. 0
somewhere The eighth

within sample is Samples
the sequence. the last sample
definedofafter
the the
sequence.
sample 1containing a set ENDn bit
It is possible to end the sequence on any sample position. Software must set an ENDn bit
June 18, 2014 1111

28 D7 RW 8th Sample Differential Input Select
Value
Description
The analog inputs are not differentially sampled. 0

be set when the TS7 bit is set. 0
The analog input is differentially sampled. The corresponding
are "2i and 2i+1". 1
ADCSSMUXn nibble must be set to the pair number "i", where the paired inputs
Because the temperature sensor does not have a differential option, this bit must not
Value
Description
seventh
The input
sample
pin of
specified
the sample
by the
sequence.
ADCSSMUXn
sequence. 1 0
The temperature sensor is read during the seventh sample of the sample
Value
Description
The raw interrupt signal ( INR0 bit) is asserted at the end of the seventh sample's
Value
Description
Another
conversion sequence
thoughisthe
thefields
final may
sample. 0
be non-zero. 0
somewhere The seventh

within sample is
the sequence. the lastdefined
Samples sampleafter
of the sequence.
the 1
sample containing a set ENDn bit
Value
Description

1112 June 18, 2014

Value
Description
sample
The input
of thepin
sample
specified
sequence.
by the ADCSSMUXn
0 register is read during the sixth
sequence. 1 0
The temperature sensor is read during the sixth sample of the sample
Value
Description
conversion.
to The
the interrupt
raw interrupt
If the
controller.
MASK0
signal1bit
( INR0
in thebit)
ADCIM
is asserted
register
at the
is set,
endthe
of interrupt
the sixth is
sample's
promoted
Value
Description
Another
conversion sequence
thoughisthe
thefields
final may
sample. 0
be non-zero. 0
somewhere The sixth

within thesample is the
sequence. last sample
Samples of the
defined aftersequence. 1 containing a set ENDn bit
the sample
Value
Description

Value
Description
sample
The input
of thepin
sample
specified
sequence.
by the ADCSSMUXn
0 register is read during the fifth
sequence. 1 0
The temperature sensor is read during the fifth sample of the sample
June 18, 2014 1113

Value
Description
conversion.
to The
the interrupt
raw interrupt
If the
controller.
MASK0
signal1bit
( INR0
in thebit)
ADCIM
is asserted
register
at the
is set,
endthe
of interrupt
the fifth sample's
is promoted
Value
Description
Another
conversion sequence
thoughisthe
thefields
final may
sample. 0
be non-zero. 0
somewhere The fifth

within thesample is theSamples
sequence. last sample of the
defined sequence.
after 1 containing a set ENDn bit
the sample
Value
Description

Value
Description
sample
The input
of thepin
sample
specified
sequence.
by the ADCSSMUXn
0 register is read during the fourth
sequence. 1 0
The temperature sensor is read during the fourth sample of the sample
Value
Description
The raw interrupt signal ( INR0 bit) is asserted at the end of the fourth sample's
1114 June 18, 2014

Value
Description
Another
conversion sequence
thoughisthe
thefields
final may
sample. 0
be non-zero. 0
somewhere The fourth

within sample is the
the sequence. last sample
Samples definedofafter
the sequence.
the sample1containing a set ENDn bit
Value
Description

11 TS2 RW 3rd Sample Temp Sensor Select
Value
Description
sample
The input
of thepin
sample
specified
sequence.
by the ADCSSMUXn
0 register is read during the third
sequence. 1 0
The temperature sensor is read during the third sample of the sample
10 IE2 RW 3rd Sample Interrupt Enable
Value
Description
conversion.
to The
the interrupt
raw interrupt
If the
controller.
MASK0
signal1bit
( INR0
in thebit)
ADCIM
is asserted
register
at the
is set,
endthe
of interrupt
the third is
sample's
promoted
9 END2 RW 3rd Sample is End of Sequence
Value
Description
Another
conversion sequence
thoughisthe
thefields
final may
sample. 0
be non-zero. 0
somewhere The third

Samples of the
defined sequence.
the sample
June 18, 2014 1115

8 D2 RW 3rd Sample Differential Input Select
Value
Description

7 TS1 RW 2nd Sample Temp Sensor Select
Value
Description
second
The input
sample
pinofspecified
the sample
by the
sequence.
ADCSSMUXn
sequence. 1 0
The temperature sensor is read during the second sample of the sample
6 IE1 RW 2nd Sample Interrupt Enable
Value
Description
The raw interrupt signal ( INR0 bit) is asserted at the end of the second sample's
5 END1 RW 2nd Sample is End of Sequence
Value
Description
Another
conversion sequence
thoughisthe
thefields
final may
sample. 0
be non-zero. 0
somewhere The second

within sample isSamples
defined of thethe
after sequence. 1
4 D1 RW 2nd Sample Differential Input Select
Value
Description

1116 June 18, 2014

3 TS0 RW 1st Sample Temp Sensor Select
Value
Description
sample
The input
of thepin
sample
specified
sequence.
by the ADCSSMUXn
0 register is read during the first
sequence. 1 0
The temperature sensor is read during the first sample of the sample
2 IE0 RW 1st Sample Interrupt Enable
Value
Description
conversion.
to The
the interrupt
raw interrupt
If the
controller.
MASK0
signal1bit
( INR0
in thebit)
ADCIM
is asserted
register
at the
is set,
endthe
of interrupt
the first sample's
is promoted
1 END0 RW 1st Sample is End of Sequence
Value
Description
Another
conversion sequence
thoughisthe
thefields
final may
sample. 0
be non-zero. 0
somewhere The first

defined sequence.
the sample
0 D0 RW 1st Sample Differential Input Select
Value
Description

June 18, 2014 1117

Register 17: ADCSample SequenceResult FIFO0 (ADCSSFIFO0), offset 0x048 Register 18:
ADCSample SequenceResult FIFO1 (ADCSSFIFO1), offset 0x068 Register 19: ADCSample
SequenceResult FIFO2 (ADCSSFIFO2), offset 0x088 Register 20: ADC Sample Sequence Result
FIFO 3 (ADCSSFIFO3), offset 0x0A8
Important: This register is read-sensitive. See the register description for details. This register contains the conversion
results for samples collected with the sample sequencer (the

ADCSSFIFO0 register is used for Sample Sequencer 0, ADCSSFIFO1 for Sequencer 1,
ADCSSFIFO2 for Sequencer 2, and ADCSSFIFO3 for Sequencer 3). Reads of this register return conversion result data in
the order sample 0, sample 1, and so on, until the FIFO is empty. If the FIFO is not properly handled by software, overflow
and underflow conditions are registered in the
ADCOSTAT and ADCUSTAT registers.
ADC Sample Sequence Result FIFO n (ADCSSFIFOn)

Type RO, reset -
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved DATA
Reset 000 0 - - - - - - - - - - - -
11:0 DATA RO - Conversion Result Data
1118 June 18, 2014

Register 21: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C
Register 24: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC
This register provides a window into the sample sequencer, providing full/empty status information as well as the positions of
the head and tail pointers. The reset value of 0x100 indicates an empty FIFO with the head and tail pointers both pointing to
index 0. The ADCSSFSTAT0 register provides status on FIFO0, which has 8 entries; ADCSSFSTAT1 on FIFO1, which has
4 entries;
ADCSSFSTAT2 on FIFO2, which has 4 entries; and ADCSSFSTAT3 on FIFO3 which has a single entry.
ADC Sample Sequence FIFO n Status (ADCSSFSTATn)

Type RO, reset 0x0000.0100
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved FULL reserved EMPTY HPTR TPTR
Reset 000000010000000 0
12 FULL RO FIFO Full
Value
Description
The FIFO is not currently full. 0
The FIFO is currently full. 1 0

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
8 EMPTY RO FIFO Empty
Value
Description
The FIFO is not currently empty. 0
The FIFO is currently empty. 1 1
June 18, 2014 1119

7:4 HPTR RO FIFO Head Pointer
This field contains the current "head" pointer index for the FIFO, that is, the next entry to
0x0
be written.
Valid values are 0x0-0x7 for FIFO0; 0x0-0x3 for FIFO1 and FIFO2; and 0x0 for FIFO3.
3:0 TPTR RO FIFO Tail Pointer
This field contains the current "tail" pointer index for the FIFO, that is, the next entry to
0x0
be read.
Valid values are 0x0-0x7 for FIFO0; 0x0-0x3 for FIFO1 and FIFO2; and 0x0 for FIFO3.
1120 June 18, 2014

Register 25: ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050

This register determines whether the sample from the given conversion on Sample Sequence 0 is saved in the Sample
Sequence FIFO0 or sent to the digital comparator unit.
ADC Sample Sequence 0 Operation (ADCSSOP0)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved S7DCOP reserved S6DCOP reserved S5DCOP reserved S4DCOP
RO RO RO RW RO RO RO RW RO RO RO RW RO RO RO Type RW
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
Reset 000000000000000 0

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
28 S7DCOP RW Sample 7 Digital Comparator Operation
Value
Description
TheADCSSDC0
bit in the eighth sample is saved
register, and in
theSample
value isSequence
not writtenFIFO0. 0
to the FIFO. 10
The eighth sample is sent to the digital comparator unit specified by the S7DCSEL

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
24 S6DCOP RW during
Sample
the seventh
6 Digitalsample.
Comparator
0 Operation Same definition as S7DCOP but used

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
20 S5DCOP RW during
Sample
the sixth
5 Digital
sample.
Comparator

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
16 S4DCOP RW during
Sample
the fifth
4 Digital
sample.
Comparator

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
June 18, 2014 1121

12 S3DCOP RW during
Sample
the fourth
3 Digital
sample.
Comparator

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
8 S2DCOP RW during
Sample
the third
2 Digital
sample.
Comparator

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
4 S1DCOP RW during
Sample
the second
1 Digital
sample.
Comparator

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
0 S0DCOP RW during
Sample
the first
0 Digital
sample.
Comparator
1122 June 18, 2014

Register 26: ADCSample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054
This register determines which digital comparator receives the sample from the given conversion on Sample Sequence 0, if
the corresponding SnDCOP bit in the ADCSSOP0 register is set.
ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
S7DCSEL S6DCSEL S5DCSEL S4DCSEL
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
Reset 000000000000000 0
31:28 S7DCSEL RW 0x0 Sample 7 Digital Comparator Select When the S7DCOP bit in the ADCSSOP0 register is
set, this field indicates which digital comparator unit (and its associated set of control
registers) receives the eighth sample from Sample Sequencer 0.
Note: Values not listed are reserved.
Value
Description
0x0 Digital Comparator Unit 0 ( ADCDCCMP0 and ADCDCCTL0)
27:24 S6DCSEL RW is used

Sample
during
6 Digital
the seventh
Comparator
sample.
Select
0x0 This field has the same encodings as S7DCSEL but

Sample
during
5 Digital
the sixth
Comparator
sample. 0x0
Select This field has the same encodings as S7DCSEL but

Sample
during
4 Digital
the fifth
Comparator
sample. 0x0

Sample
during
3 Digital
the fourth
Comparator
sample. Select
June 18, 2014 1123


Sample
during
2 Digital
the third
Comparator
sample. 0x0

Sample
during
1 Digital
the second
Comparator
sample.Select

Sample
during
0 Digital
the first
Comparator
sample. 0x0
1124 June 18, 2014

Register 27: ADC Sample Sequence Extended Input Multiplexer Select 0 (ADCSSEMUX0),
offset 0x058
This register, along with the ADCSSMUX0 register, defines the analog input configuration for each sample in a sequence
executed with Sample Sequencer 0. If a bit in this register is set, the corresponding MUXn field in the ADCSSMUX0 register
selects from AIN[19:16]. When a bit in this register is clear, the corresponding MUXn field selects from AIN[15:0]. This
register is 32 bits wide and contains information for eight possible samples.
Note that this register is not used when the differential channel designation is used (the Dn bit is set in the ADCSSCTL0 register)
because the ADCSSMUX0 register can select all the available pairs.
ADC Sample Sequence Extended Input Multiplexer Select 0 (ADCSSEMUX0)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved EMUX7 reserved EMUX6 reserved EMUX5 reserved EMUX4
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
Reset 000000000000000 0

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
28 EMUX7 RW 8th Sample Input Select (Upper Bit) The EMUX7 field is used during the eighth
sample of a sequence executed with the sample sequencer.
Value
Description
The eighth sample input is selected from AIN[15:0] using the

ADCSSMUX0 register. For example, if the MUX7 field is 0x0,
AIN0 is selected. 0
The eighth sample input is selected from AIN[19:16] using the ADCSSMUX0 register.
For example, if the MUX7 field is 0x0,
AIN16 is selected. 1 0x0

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
24 EMUX6 RW 0x0 7th Sample Input Select (Upper Bit) The EMUX6 field is used during the seventh sample of
a sequence executed with the sample sequencer. This bit has the same description as EMUX7.

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
June 18, 2014 1125

20 EMUX5 RW 0x0 6th Sample Input Select (Upper Bit) The EMUX5 field is used during the sixth sample of a
sequence executed with the sample sequencer. This bit has the same description as EMUX7.

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
16 EMUX4 RW 0x0 5th Sample Input Select (Upper Bit) The EMUX4 field is used during the fifth sample of a

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
12 EMUX3 RW 0x0 4th Sample Input Select (Upper Bit) The EMUX3 field is used during the fourth sample of a

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
8 EMUX2 RW 0x0 3rd Sample Input Select (Upper Bit) The EMUX2 field is used during the third sample of a

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
4 EMUX1 RW 0x0 2th Sample Input Select (Upper Bit) The EMUX1 field is used during the second sample of

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
0 EMUX0 RW 0x0 1st Sample Input Select (Upper Bit) The EMUX0 field is used during the first sample of a
1126 June 18, 2014

Register 28: ADC Sample Sequence 0 Sample and Hold Time (ADCSSTSH0), offset 0x05C
This register controls the sample period size for each sample of sequencer 0. Each sample and hold period select
specifies the time allocated to the sample and hold circuit as shown by the encodings in Table 15-3 on page 1058.
Note: If sampling the internal temperature sensor, the sample and hold width should be at least 16 ADC clocks ( TSHn
= 0x4).
Table 15-8. Sample and Hold Width in ADC Clocks
TSHn Encoding N SH
0x0 4
0x1 reserved
0x2 8
0x3 reserved
0x4 16
0x5 reserved
0x6 32
0x7 reserved
0x8 64
0x9 reserved
0xA 128
0xB reserved
0xC 256
0xD-0xF reserved
ADC Sample Sequence 0 Sample and Hold Time (ADCSSTSH0)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
TSH7 TSH6 TSH5 TSH4
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
TSH3 TSH2 TSH1 TSH0
Reset 000000000000000 0
31:28 TSH7 RW sequence

8th Sample
executed
and Hold
with the
Period
sample
Select
sequencer.
The TSH70x0
field is used during the eighth sample of a
27:24 TSH6 RW sample

7th Sample
of a sequence
and Hold
executed
Period Select
with the
The
sample
TSH6sequencer.
field is used
0x0
during the seventh
June 18, 2014 1127

23:20 TSH5 RW 6th Sample and Hold Period Select

sequencer. 0x0
The TSH5 field is used during the sixth sample of a sequence executed with the sample

5th Sample
executed
and Hold
with the
Period
sample
Select
sequencer.
The TSH40x0
field is used during the fifth sample of a

4th Sample
executed
and Hold
with the
Period
sample
Select
sequencer.
The TSH30x0
field is used during the fourth sample of a

3rd Sample
executed
and Hold
with the
Period
sample
Select
sequencer.
The TSH20x0
field is used during the third sample of a
7:4 TSH1 RW sample

2nd Sample
of a sequence
and Hold
executed
Period with
Select
theThe
sample
TSH1sequencer.
field is used
0x0
during the second

1st Sample
executed
and Hold
with Period
the sample
Select
sequencer.
The TSH00x0
field is used during the first sample of a
1128 June 18, 2014

This register, along with the ADCSSEMUX1 or ADCSSEMUX2 register, defines the analog input configuration for each
sample in a sequence executed with Sample Sequencer 1 or 2. If the corresponding EMUXn bit in the ADCSSEMUX1 or ADCSSEMUX2
register is set, the MUXn field in this register selects from AIN[19:16]. When the corresponding EMUXn bit is clear, the MUXn field
selects from AIN[15:0]. These registers are 16 bits wide and contain information for four possible samples. See the ADCSSMUX0
register on page 1109 for detailed bit descriptions. The ADCSSMUX1
register affects Sample Sequencer 1 and the ADCSSMUX2 register affects Sample Sequencer 2.
Note: Channels AIN[31:20] do not exist on this microcontroller. Configuring MUXn to be 0xC-0xF
when the corresponding EMUXn bit is set results in undefined behavior.
ADC Sample Sequence Input Multiplexer Select n (ADCSSMUXn)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
MUX3 MUX2 MUX1 MUX0
Reset 000000000000000 0
15:12 MUX3 RW 4th Sample Input Select 0x0
11:8 MUX2 RW 3rd Sample Input Select 0x0
7:4 MUX1 RW 2nd Sample Input Select 0x0
3:0 MUX0 RW 1st Sample Input Select 0x0
June 18, 2014 1129

Register 31: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 Register 32: ADC
Sample Sequence Control 2 (ADCSSCTL2), offset 0x084

These registers contain the configuration information for each sample for a sequence executed with Sample Sequencer 1 or
2. When configuring a sample sequence, the END bit must be set for the final sample, whether it be after the first sample,
fourth sample, or any sample in between. These registers are 16-bits wide and contain information for four possible samples.
See the ADCSSCTL0
register on page 1111 for detailed bit descriptions. The ADCSSCTL1 register configures Sample Sequencer 1 and the ADCSSCTL2
register configures Sample Sequencer 2.
ADC Sample Sequence Control n (ADCSSCTLn)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
Reset 000000000000000 0
Value
Description
sample
The input
of thepin
sample
specified
sequence.
by the ADCSSMUXn
0 register is read during the fourth
sequence. 1 0
The temperature sensor is read during the fourth sample of the sample
Value
Description
The raw interrupt signal ( INR0 bit) is asserted at the end of the fourth sample's
1130 June 18, 2014

Value
Description
Another
conversion sequence
thoughisthe
thefields
final may
sample. 0
be non-zero. 0
somewhere The fourth

within sample is the
the sequence. last sample
Samples definedofafter
the sequence.
the sample1containing a set ENDn bit
Value
Description

11 TS2 RW 3rd Sample Temp Sensor Select
Value
Description
sample
The input
of thepin
sample
specified
sequence.
by the ADCSSMUXn
0 register is read during the third
sequence. 1 0
The temperature sensor is read during the third sample of the sample
10 IE2 RW 3rd Sample Interrupt Enable
Value
Description
conversion.
to The
the interrupt
raw interrupt
If the
controller.
MASK0
signal1bit
( INR0
in thebit)
ADCIM
is asserted
register
at the
is set,
endthe
of interrupt
the third is
sample's
promoted
9 END2 RW 3rd Sample is End of Sequence
Value
Description
Another
conversion sequence
thoughisthe
thefields
final may
sample. 0
be non-zero. 0
somewhere The third

Samples of the
defined sequence.
the sample
June 18, 2014 1131

8 D2 RW 3rd Sample Differential Input Select
Value
Description

7 TS1 RW 2nd Sample Temp Sensor Select
Value
Description
second
The input
sample
pinofspecified
the sample
by the
sequence.
ADCSSMUXn
sequence. 1 0
The temperature sensor is read during the second sample of the sample
6 IE1 RW 2nd Sample Interrupt Enable
Value
Description
The raw interrupt signal ( INR0 bit) is asserted at the end of the second sample's
5 END1 RW 2nd Sample is End of Sequence
Value
Description
Another
conversion sequence
thoughisthe
thefields
final may
sample. 0
be non-zero. 0
somewhere The second

within sample isSamples
defined of thethe
after sequence. 1
4 D1 RW 2nd Sample Differential Input Select
Value
Description

1132 June 18, 2014

Value
Description
sample
The input
of thepin
sample
specified
sequence.
by the ADCSSMUXn
sequence. 1 0
2 IE0 RW 1st Sample Interrupt Enable
Value
Description
conversion.
to The
the interrupt
raw interrupt
If the
controller.
MASK0
signal1bit
( INR0
in thebit)
ADCIM
is asserted
register
at the
is set,
endthe
of interrupt
the first sample's
is promoted
1 END0 RW 1st Sample is End of Sequence
Value
Description
Another
conversion sequence
thoughisthe
thefields
final may
sample. 0
be non-zero. 0
somewhere The first

defined sequence.
the sample
0 D0 RW 1st Sample Differential Input Select
Value
Description

June 18, 2014 1133

Register 33: ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 Register 34: ADC
Sample Sequence 2 Operation (ADCSSOP2), offset 0x090

This register determines whether the sample from the given conversion on Sample Sequence n is saved in the Sample
Sequence n FIFO or sent to the digital comparator unit. The ADCSSOP1
register controls Sample Sequencer 1 and the ADCSSOP2 register controls Sample Sequencer 2.
ADC Sample Sequence n Operation (ADCSSOPn)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
Reset 000000000000000 0
Value
Description
TheADCSSDC0n
bit in the fourth sample is saved
register, inthe
and Sample
value Sequence FIFOn.
is not written to the0FIFO. 1 0
The fourth sample is sent to the digital comparator unit specified by the S3DCSEL

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
8 S2DCOP RW during
Sample
the third
2 Digital
sample.
Comparator

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
4 S1DCOP RW during
Sample
the second
1 Digital
sample.
Comparator

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
0 S0DCOP RW during
Sample
the first
0 Digital
sample.
Comparator
1134 June 18, 2014

These registers determine which digital comparator receives the sample from the given conversion on Sample Sequence n if
the corresponding SnDCOP bit in the ADCSSOPn register is set. The
ADCSSDC1 register controls the selection for Sample Sequencer 1 and the ADCSSDC2 register controls the selection for
Sample Sequencer 2.
ADC Sample Sequence n Digital Comparator Select (ADCSSDCn)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
Reset 000000000000000 0
15:12 S3DCSEL RW 0x0 Sample 3 Digital Comparator Select When the S3DCOP bit in the ADCSSOPn register is
registers) receives the eighth sample from Sample Sequencer n.
Value
Description
0x0 Digital Comparator Unit 0 ( ADCDCCMP0 and ADCCCTL0)

Sample
during
2 Digital
the third
Comparator
sample. 0x0
June 18, 2014 1135


Sample
during
1 Digital
the second
Comparator
sample.Select

Sample
during
0 Digital
the first
Comparator
sample. 0x0
1136 June 18, 2014

offset 0x078
offset 0x098
This register, along with the ADCSSMUX1 or ADCSSMUX2 register, defines the analog input configuration for each sample
in a sequence executed with either Sample Sequencer 1 or 2. If a bit in this register is set, the corresponding MUXn field in
the ADCSSMUX1 or ADCSSMUX2 register selects from AIN[19:16]. When a bit in this register is clear, the corresponding MUXn
field selects from AIN[15:0]. This register is 16 bits wide and contains information for four possible samples. The ADCSSEMUX1
register controls Sample Sequencer 1 and the ADCSSEMUX2 register controls Sample Sequencer 2.
Note that this register is not used when the differential channel designation is used (the Dn bit is set in the ADCSSCTL1 or ADCSSCTL2
register) because the ADCSSMUX1 or ADCSSMUX2 register can select all the available pairs.
ADC Sample Sequence Extended Input Multiplexer Select n (ADCSSEMUXn)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
Reset 000000000000000 0
12 EMUX3 RW 4th Sample Input Select (Upper Bit) The EMUX3 field is used during the fourth sample of a
sequence executed with the sample sequencer.
Value
Description
The fourth sample input is selected from AIN[15:0] using the

ADCSSMUX1 or ADCSSMUX2 register. For example, if the
MUX3 field is 0x0, AIN0 is selected. 0
The fourth sample input is selected from AIN[19:16] using the ADCSSMUX1 or
ADCSSMUX2 register. For example, if the
MUX3 field is 0x0, AIN16 is selected. 1 0x0

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
June 18, 2014 1137

8 EMUX2 RW 0x0 3rd Sample Input Select (Upper Bit) The EMUX2 field is used during the third sample of a

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
4 EMUX1 RW 0x0 2th Sample Input Select (Upper Bit) The EMUX1 field is used during the second sample of

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
0 EMUX0 RW 0x0 1st Sample Input Select (Upper Bit) The EMUX0 field is used during the first sample of a
1138 June 18, 2014

These registers control the sample period size for each sample step of sequencer 1 and sequencer
2. Each sample and hold period select specifies the time allocated to the sample and hold circuit as shown by the
encodings in Table 15-3 on page 1058.
= 0x4).
TSHn Encoding N SH
0x0 4
0x1 reserved
0x2 8
0x3 reserved
0x4 16
0x5 reserved
0x6 32
0x7 reserved
0x8 64
0x9 reserved
0xA 128
0xB reserved
0xC 256
0xD-0xF reserved
ADC Sample Sequence n Sample and Hold Time (ADCSSTSHn)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
TSH3 TSH2 TSH1 TSH0
Reset 000000000000000 0
June 18, 2014 1139

15:12 TSH3 RW 4th Sample and Hold Period Select

sequencer. 0x0
The TSH3 field is used during the fourth sample of a sequence executed with the sample
11:8 TSH2 RW 3rd Sample and Hold Period Select

sequencer. 0x0
The TSH2 field is used during the third sample of a sequence executed with the sample
7:4 TSH1 RW sample

2nd Sample
of a sequence
and Hold
executed
Period with
Select
theThe
sample
TSH1sequencer.
field is used
0x0
during the second
3:0 TSH0 RW 1st Sample and Hold Period Select

sequencer. 0x0
The TSH0 field is used during the first sample of a sequence executed with the sample
1140 June 18, 2014

Register 41: ADCSample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0
This register, along with the ADCSSEMUX3 register, defines the analog input configuration for the sample in a sequence
executed with Sample Sequencer 3. If the EMUX0 bit in the ADCSSEMUX3
register is set, the MUX0 field in this register selects from AIN[19:16]. When the EMUX0 bit is clear, the MUX0 field selects
from AIN[15:0]. This register is four bits wide and contains information for one possible sample. See the ADCSSMUX0 register
on page 1109 for detailed bit descriptions.
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3)

base: 0x4003.9000 Offset 0x0A0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved MUX0
Reset 000000000000000 0
3:0 MUX0 RW 1st Sample Input Select 0
June 18, 2014 1141

Register 42: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4

This register contains the configuration information for a sample executed with Sample Sequencer
3. This register is 4 bits wide and contains information for one possible sample. See the ADCSSCTL0
register on page 1111 for detailed bit descriptions.
Note: When configuring a sample sequence in this register, the END0 bit must be set.
ADC Sample Sequence Control 3 (ADCSSCTL3)

base: 0x4003.9000 Offset 0x0A4
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved IE0 TS0 END0 D0
Reset 000000000000000 0
Value
Description
sample
The input
of thepin
sample
specified
sequence.
by the ADCSSMUXn
sequence. 1 0
2 IE0 RW Sample Interrupt Enable
Value
Description
conversion.
to The
the interrupt
raw interrupt
If the
controller.
MASK0
signal1bit
( INR0
in thebit)
ADCIM
is asserted
register
at the
is set,
endthe
of interrupt
this sample's
is promoted
1 END0 RW End of Sequence
This bit must be set before initiating a single sample sequence.
Value
Description
Sampling and conversion continues. 0
This is the end of sequence. 1 0
1142 June 18, 2014

0 D0 RW Sample Differential Input Select
Value
Description

June 18, 2014 1143

Register 43: ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0

This register determines whether the sample from the given conversion on Sample Sequence 3 is saved in the Sample
Sequence 3 FIFO or sent to the digital comparator unit.
ADC Sample Sequence 3 Operation (ADCSSOP3)

base: 0x4003.9000 Offset 0x0B0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved S0DCOP
Reset 000000000000000 0
Value
Description
The sampleregister,
the ADCSSDC03 is savedand
in Sample Sequence
the value FIFO3.
is not written 0 FIFO. 1 0
to the
The sample is sent to the digital comparator unit specified by the S0DCSEL bit in
1144 June 18, 2014

Register 44: ADCSample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4
This register determines which digital comparator receives the sample from the given conversion on Sample Sequence 3 if
the corresponding SnDCOP bit in the ADCSSOP3 register is set.
ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved S0DCSEL
Reset 000000000000000 0
3:0 S0DCSEL RW 0x0 Sample 0 Digital Comparator Select When the S0DCOP bit in the ADCSSOP3 register is
registers) receives the sample from Sample Sequencer 3.
Value
Description
June 18, 2014 1145

offset 0x0B8
This register, along with the ADCSSMUX3 register, defines the analog input configuration for the sample in a sequence
executed with Sample Sequencer 3. If EMUX0 is set, the MUX0 field in the
ADCSSMUX3 register selects from AIN[19:16]. When EMUX0 is clear, the MUX0 field selects from
AIN[15:0]. This register is 1 bit wide and contains information for one possible sample. Note that this register is not used
when the differential channel designation is used (the Dn bit is set in the ADCSSCTL3 register) because the ADCSSMUX3 register
can select all the available pairs.
ADC Sample Sequence Extended Input Multiplexer Select 3 (ADCSSEMUX3)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved EMUX0
Reset 000000000000000 0
0 EMUX0 RW 1st Sample Input Select (Upper Bit) The EMUX0 field is used during the only sample of a
sequence executed with the sample sequencer.
Value
Description
The sample input is selected from AIN[15:0] using the

AIN0 is selected. 0
The sample input is selected from AIN[19:16] using the

AIN16 is selected. 1 0x0
1146 June 18, 2014

Register 46: ADC Sample Sequence 3 Sample and Hold Time (ADCSSTSH3), offset 0x0BC
This register controls the sample period size for the sample in sequencer 3. The sample and hold period select specifies the
time allocated to the sample and hold circuit as shown by the encodings in Table 15-3 on page 1058
= 0x4).
TSHn Encoding N SH
0x0 4
0x1 reserved
0x2 8
0x3 reserved
0x4 16
0x5 reserved
0x6 32
0x7 reserved
0x8 64
0x9 reserved
0xA 128
0xB reserved
0xC 256
0xD-0xF reserved
ADC Sample Sequence 3 Sample and Hold Time (ADCSSTSH3)

base: 0x4003.9000 Offset 0x0BC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved TSH0
Reset 000000000000000 0

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
3:0 TSH0 RW 1st Sample and Hold Period Select

sequencer. 0x0
The TSH0 field is used during the first sample of a sequence executed with the sample
June 18, 2014 1147

Register 47: ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00
This register provides the ability to reset any of the digital comparator interrupt or trigger functions back to their initial
conditions. Resetting these functions ensures that the data that is being used by the interrupt and trigger functions in the
digital comparator unit is not stale.
ADC Digital Comparator Reset Initial Conditions (ADCDCRIC)

base: 0x4003.9000 Offset 0xD00
Type WO, reset 0x0000.0000
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved DCTRIG1 DCTRIG2 DCTRIG3 DCTRIG4 DCTRIG5DCTRIG0

DCTRIG7 DCTRIG6
WO WO WO WO WO WO WO RO RO RO RO RO RO RO RO Type WO
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved DCINT1 DCINT2 DCINT3 DCINT4 DCINT5 DCINT6DCINT0

DCINT7
WO WO WO WO WO WO WO RO RO RO RO RO RO RO RO Type WO
Reset 000000000000000 0

operation.
Software
products,
0x00
should
the value
not rely
of on
a reserved
the valuebit
ofshould
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
23 DCTRIG7 WO Digital Comparator Trigger 7
ValueDescription
should wait until the bit clears before continuing. 0
No effect. 0
starting a new sequence so that stale data is not used. After setting this bit, software
Resets the Digital Comparator 7 trigger unit to its initial conditions. 1
assert the trigger, it is important to reset the digital comparator to initial conditions when
comparators use the current and previous ADC conversion values to determine when to
When the trigger has been cleared, this bit is automatically cleared. Because the digital
Value
Description
starting a new
No sequence
effect. 0 so that stale data is not used. 0
assert the trigger,

Resetsitthe
is important to reset the
Digital Comparator digital comparator
6 trigger to initial
unit to its initial conditions
conditions. 1 when
1148 June 18, 2014

Value
Description
starting a new
No sequence
assert the trigger,

Resetsitthe
conditions. 1 when
Value
Description
starting a new
No sequence
assert the trigger,

Resetsitthe
conditions. 1 when
Value
Description
starting a new
No sequence
assert the trigger,

Resetsitthe
conditions. 1 when
Value
Description
starting a new
No sequence
assert the trigger,

Resetsitthe
conditions. 1 when
June 18, 2014 1149

Value
Description
starting a new
No sequence
assert the trigger,

Resetsitthe
conditions. 1 when
Value
Description
starting a new
No sequence
assert the trigger,

Resetsitthe
conditions. 1 when

operation.
Software
products,
0x00
should
the value
not rely
of on
a reserved
the valuebit
ofshould
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
7 DCINT7 WO Digital Comparator Interrupt 7
Value
Description
starting a new
No sequence
assert the interrupt,

Resets theit isDigital
important to reset 7
Comparator the digital comparator
interrupt to initial
conditions. 1 when
When the interrupt has been cleared, this bit is automatically cleared. Because the digital
Value
Description
starting a new
No sequence

conditions. 1 when
1150 June 18, 2014

Value
Description
starting a new
No sequence

conditions. 1 when
Value
Description
starting a new
No sequence

conditions. 1 when
Value
Description
starting a new
No sequence

conditions. 1 when
Value
Description
starting a new
No sequence

conditions. 1 when
June 18, 2014 1151

Value
Description
starting a new
No sequence

conditions. 1 when
Value
Description
starting a new
No sequence

conditions. 1 when
1152 June 18, 2014

Register 48: ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 Register 49: ADC
Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 Register 50: ADC Digital Comparator
Control 2 (ADCDCCTL2), offset 0xE08 Register 51: ADC Digital Comparator Control 3
(ADCDCCTL3), offset 0xE0C Register 52: ADC Digital Comparator Control 4 (ADCDCCTL4),
offset 0xE10 Register 53: ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14
Register 54: ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 Register 55: ADC
Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C
This register provides the comparison encodings that generate an interrupt and/or PWM trigger. See
“Interrupt/ADC-Trigger Selector” on page 1675 for more information on using the ADC digital comparators to trigger a
PWM generator.
ADC Digital Comparator Control n (ADCDCCTLn)

base: 0x4003.9000 Offset 0xE00
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved CTE CTC CTM reserved CIE CIC CIM
RW RW RW RW RO RO RO RW RW RW RW RW RO RO RO Type RW
Reset 000000000000000 0
12 CTE RW Comparison Trigger Enable
Value
Description
CTM fields. 1 0
by Disables
the triggerthe
function.
trigger 0
function state machine. ADC conversion data is ignored
determine if a trigger should be generated according to the programming of the CTC and
Enables the trigger function statemachine. The ADC conversion data is used to
June 18, 2014 1153

11:10 CTC RW Comparison Trigger Condition
This field specifies the operational region in which a trigger is generated when the ADC
conversion data is compared against the values of COMP0
and COMP1. The COMP0 and COMP1 fields are defined in the
ADCDCCMPx registers.
Value
Description
0x0 Low Band ADC Data < COMP0 ≤ COMP1
0x1 Mid Band
COMP0 < ADC Data ≤ COMP1
0x2 reserved
High Band
COMP0 ≤ COMP1 ≤ ADC Data 0x3 0x0
9:8 CTM RW Comparison Trigger Mode
This field specifies the mode by which the trigger comparison is made.
Value
Description
Always
the selected operational region. 0x0
This mode generates a trigger every time the ADC conversion data falls within
Once
data enters the selected operational region. 0x1
This mode generates a trigger the first time that the ADC conversion
Hysteresis Always
0x0 This mode generates a trigger when the ADC conversion data falls within the
selected operational region and continues to generate the trigger until the
hysteresis condition is cleared by entering the opposite operational region.
Note that the hysteresis modes are only defined for CTC
encodings of 0x0 and 0x3. 0x2
Hysteresis Once
This mode generates a trigger the first time that the ADC conversion data falls
within the selected operational region. No additional triggers are generated
until the hysteresis condition is cleared by entering the opposite operational
region. Note that the hysteresis modes are only defined for CTC

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
1154 June 18, 2014

4 CIE RW Comparison Interrupt Enable
Value
Description
and CIM fields. 1 0
interrupt
Disables
generation.
the comparison
0 interrupt. ADC conversion data has no effect on
determine if an interrupt should be generated according to the programming of the CIC
Enables the comparison interrupt. The ADC conversion data is used to
3:2 CIC RW Comparison Interrupt Condition
This field specifies the operational region in which an interrupt is generated when the ADC
conversion data is compared against the values of COMP0 and COMP1. The COMP0 and COMP1
fields are defined in the ADCDCCMPx registers.
Value
Description
0x0 Low Band ADC Data < COMP0 ≤ COMP1
0x1 Mid Band
COMP0 ≤ ADC Data < COMP1
0x2 reserved
High Band
COMP0 < COMP1 ≤ ADC Data 0x3 0x0
1:0 CIM RW Comparison Interrupt Mode
This field specifies the mode by which the interrupt comparison is made.
Value
Description
Always
the selected operational region. 0x0
Thismode generates an interrupt every time the ADC conversion data falls within
Once
data enters the selected operational region. 0x1
This mode generates an interrupt the first time that the ADC conversion
Hysteresis Always
0x0 This mode generates an interrupt when the ADC conversion data falls within
the selected operational region and continues to generate the interrupt until the
hysteresis condition is cleared by entering the opposite operational region.
Note that the hysteresis modes are only defined for CTC
Hysteresis Once
This mode generates an interrupt the first time that the ADC conversion data
falls within the selected operational region. No additional interrupts are
generated until the hysteresis condition is cleared by entering the opposite
operational region. Note that the hysteresis modes are only defined for CTC
June 18, 2014 1155

Register 56: ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 Register 57: ADC
Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 Register 58: ADC Digital Comparator
Range 2 (ADCDCCMP2), offset 0xE48 Register 59: ADC Digital Comparator Range 3
(ADCDCCMP3), offset 0xE4C Register 60: ADC Digital Comparator Range 4 (ADCDCCMP4),
offset 0xE50 Register 61: ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54
Register 62: ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 Register 63: ADC
Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C
This register defines the comparison values that are used to determine if the ADC conversion data falls in the appropriate
operating region.
Note: The value in the COMP1 field must be greater than or equal to the value in the COMP0 field
or unexpected results can occur.
ADC Digital Comparator Range n (ADCDCCMPn)

base: 0x4003.9000 Offset 0xE40
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved COMP1
RW RW RW RW RW RW RW RW RW RW RW RO RO RO RO Type RW
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved COMP0
RW RW RW RW RW RW RW RW RW RW RW RO RO RO RO Type RW
Reset 000000000000000 0

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
27:16 COMP1 RW 0x000 Compare 1
The value in this field is compared against the ADC conversion data. The result of the
comparison is used to determine if the data lies within the high-band region. Note that the
value of COMP1 must be greater than or equal to the value of COMP0.

operation.
Software
products,
0x0
should
the not
value
rely
ofon
a reserved
the valuebit
of should
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
11:0 COMP0 Compare 0

comparison is used to determine if the data lies within the low-band region. 0x000 RW
The value in this field is compared against the ADC conversion data. The result of the
1156 June 18, 2014

Register 64: ADC Peripheral Properties (ADCPP), offset 0xFC0

The ADCPP register provides information regarding the properties of the ADC module.
ADC Peripheral Properties (ADCPP)

base: 0x4003.9000 Offset 0xFC0
Type RO, reset 0x01B0.2147
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved APSHT TS RSL TYPE
Reset 000110110000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
DC CH MCR
Reset 110001010000100 1

operation.
Software
products,
0x00
should
the value
not rely
of on
a reserved
the valuebit
ofshould
a reserved
be preserved
bit. To provide
acrosscompatibility
a read-modify-write
with
24 APSHT RO capability
Application-Programmable
of allowing the application
Sample-and-Hold
to adjust theTime
sample
This
and
bit hold
indicates
window
theperiod.
ADC has0x1the
23 TS RO Temperature Sensor
Value
Description
The ADC module does not have a temperature sensor. 0
The ADC module has a temperature sensor. 1
This field provides the similar information as the legacy DC1 register
TEMPSNS bit. 0x1
22:18 RSL RO Resolution

sample. The field is encoded as a binary value, in the range of 0 to 32 bits. 0xC
This field specifies themaximumnumber of binary bits used to represent the converted
17:16 TYPE RO ADC Architecture
Value Description
0x1 - 0x3 0x0
0x0 SAR
Reserved
15:10 DC RO Digital Comparator Count
This field specifies the number of ADC digital comparators available to the converter.
The field is encoded as a binary value, in the range of 0 to 63.
This field provides similar information to the legacy DC9 register

ADCnDCn bits. 0x8
June 18, 2014 1157

9:4 CH RO ADC Channel Count
This field specifies the number of ADC input channels available to the converter. This
field is encoded as a binary value, in the range of 0 to
63.
This field provides similar information to the legacy DC3 and DC8 register
ADCnAINn bits. 0x14
3:0 MCR RO Maximum Conversion Rate
This field specifies the maximum value that may be programmed into the ADCPC register's
CR field.
0x8 - 0xF 0x7 Description

Value
0x0-0x6
Reserved
0x7 Full conversion rate (F CONV) as defined by T ADC and N SH.
Reserved
1158 June 18, 2014

Register 65: ADC Peripheral Configuration (ADCPC), offset 0xFC4

The ADCPC register provides information regarding the configuration of the peripheral.
ADC Peripheral Configuration (ADCPC)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved MCR
Reset 110000000000000 1
3:0 MCR RW Conversion Rate
This field specifies the relative sample rate of the ADC and is used in run, sleep, and
deep-sleep modes. It allows the application to reduce the rate at which conversions are
generated relative to the maximum conversion rate.
Value Description
0x0 Reserved
for 112
Eighth
T ADC
conversion
periods before
rate. After
starting
a conversion
the next conversion.
completes, the
0x1 logic pauses
0x20x7 Reserved
0x8 - 0xF
for 48
Quarter
T ADCconversion
periods before
rate.starting
After a the
conversion
next conversion.
completes,
0x3
the logic pauses
0x4 Reserved
T ADC
Half
periods
conversion
beforerate.
starting
Afterthe
a conversion
next conversion.
completes,
0x5 the logic pauses for 16
0x6 Reserved
0x7 Full conversion rate (F CONV) as defined by T ADC and N SH.
Reserved
June 18, 2014 1159

Register 66: ADC Clock Configuration (ADCCC), offset 0xFC8

The ADCCC register controls the clock source for the ADC module.
ADC Clock Configuration (ADCCC)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16
reserved
Reset 000000000000000 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
reserved CLKDIV CS
RW RW RW RW RW RW RW RW RW RO RO RO RO RO RO Type RW
Reset 000000000000000 1
9:4 CLKDIV RW PLL VCO Clock Divisor
Value
Description
0x0 /1
0xN 0x0
0x1 /2
0x2 /3
/(N + 1)
3:0 CS RW ADC Clock Source
Value Description
PLL VCO divided by CLKDIV. 0x0

0x2 - 0xF 0x1
Control
Alternate
Module.
clock
0x1source as defined by ALTCLKCFG register in System
0x2 MOSC
Reserved
1160 June 18, 2014


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tiva ™ TM4C1294NCPDT microcontrolador

15 de analógico a digital (ADC)

■ 20 canales de entrada analógica compartidos

■ Precisión ADC de 12 bits

■ y configuraciones de entrada diferencial de terminación única

■ En el chip sensor de temperatura interno

■ velocidad de muestreo máxima de dos millones de muestras / segundo

■ , Retardo de fase programable opcional

■ De la muestra y la ventana de retención programabilidad

■ control de disparo flexibles

■ promediado Hardware de hasta 64 muestras

■ Ocho comparadores digitales

18 de junio 2014 1053

■ Convertidor utiliza señales VREFA + y GNDA como la referencia de tensión

■ Potencia y tierra para la circuitería analógica es independiente de la potencia digital y tierra

■ transferencias eficientes utilizando Controlador de Acceso Directo (Micro Memory μDMA)

- canal dedicado para cada muestra de secuenciador

- Módulo ADC utiliza solicitudes se rompió para el DMA

15.1 Diagrama de bloques

Figura 15-1. Implementación de dos bloques de ADC

1054 18 de junio 2014

Figura 15-2. Diagrama de bloques del módulo ADC

VDDA / GNDA Externa Voltaje Ref

PWM ADCUSTAT ADCSSEMUX0

GPIO SS0 Sequencer

ADCDCISC Las interrupciones de corriente continua

15.2 Descripción de la señal

Tabla 15-1. Las señales de ADC (128TQFP)

AIN0 12 PE3 yo Conversión analógica-digital de entrada 0. Analog

AIN1 13 PE2 yo Conversión analógica-digital de entrada analógica 1.

AIN2 14 PE1 yo Conversión analógica-digital de entrada analógica 2.

AIn3 15 PE0 yo Conversión analógica-digital de entrada 3. analógico

AIN4 128 PD7 yo Conversión analógica-digital de entrada 4. analógico

AIN5 127 PD6 yo Conversión analógica-digital de entrada 5. analógico

AIN6 126 PD5 yo Conversión analógica-digital de entrada 6. Analog

AIN7 125 PD4 yo Conversión analógica-digital de entrada analógica 7.

18 de junio 2014 1055

Tabla 15-1. Las señales de ADC () (128TQFP continuado)

AIN8 124 PE5 yo Conversión analógica-digital de entrada 8. Analog

AIN9 123 PE4 yo Conversión analógica-digital de entrada 9. Analog

AIN10 121 PB4 yo Conversión analógica-digital de entrada 10. analógico

AIN11 120 PB5 yo Conversión analógica-digital de entrada 11. Analog

AIN12 4 PD3 yo Conversión analógica-digital de entrada 12. Analog

AIN13 3 PD2 yo Conversión analógica-digital de entrada 13. Analog

AIN14 2 PD1 yo Conversión analógica-digital de entrada 14. Analog

AIN15 1 PD0 yo Conversión analógica-digital de entrada 15. Analog

AIN16 18 PK0 yo Conversión analógica-digital de entrada 16. analógico

AIN17 19 PK1 yo Conversión analógica-digital de entrada 17. analógico

AIN18 20 PK2 yo Conversión analógica-digital de entrada 18. analógico

AIN19 21 PK3 yo Conversión analógica-digital de entrada 19. Analog

VREFA + 9 fijo - Un voltaje de referencia utilizado para especificar la tensión a la

15.3 descripcion funcional

15.3.1 Secuenciadores de ejemplo

Tabla 15-2. Las muestras y la profundidad de FIFO Secuenciadores

secuenciador Número de muestras La profundidad de FIFO

1056 18 de junio 2014

Módulo de control 15.3.2

■ configuración del disparador

■ referencia de tensión externa

■ control de fase de la muestra

18 de junio 2014 1057

15.3.2.2 Operación DMA

registrarse en el offset 0x000.