Estructura de un disefio VHDL Library ice; use icce.std logic 1164.a11; aren al a Dectaraciones det puerto : —_ Nombre de la entidad ‘Gnd mi_components; <— / Tipos de datos basicos + TIPGes|a defnicién de ts valores too posibles que puede tomar un objeto + Los tips predenidos son ie os = Escaiaes:mteper fang point srurerated [compuestos sca ~ Compuestos: aay ‘e001 = Puntos: secess wee rey = arenes fle Tisico oon See + INTEGER tipo entero ~ sade como valr indice enlzos, constantes o valores gendncos| *+ BOOLEAN: tipo loico USE ieee std Logic 1164-ALL; Puede tomar como aloes TRUE! @ FALSE? mrrTx mi_componente 15 PORT ( + ENUMERATED: Enumeracion as =e TH ste logic; ~ Conjunto de valores det por el usuario IE std Logie veotor(7 DOO 0); ~ Porelempo: TYPE extados 15 (inicio, lento, rapido) oor etd logic vector(7 DOWTO 0)) + et Tipos SIGNED y UNSIGNED ~ Las operaciones aritmeéticas estindares s6lo etn = Vamos a definir una senal de 6 bits para wabajar cow ella casters ay eel ipeed y(aeel poe Steams taps 7010016 vEcTOR? dows 8) — Son similares a std_logic_vector: ~ Asignacién de ua valor binario: sme <= "20200018" Estan definidos en Ia libveris IEEE. numeric_std ~~ Asignacién de un valor en hexadecimal: om = Asimuaei6n de un bit: eepen) <= 32 Ejemplo de use: ~ Definimos una variable de tipo unsigned, para implementar wm contador: Asignacién de un rango de bits: eme(7 dowsee 4) <= ~1010"7 = Asignacién compacta: tape (0->:0", 1250 and b, otbes ‘vauiasus contador: netmed(7 domes 0); [FS | erConversiones de tipos Conversiones de tipos (III — Usaromos estos objetos como ojomplo: signal stav: std logic vector (7 dowmto 0); ee eee ee ae variable uns: unsigned(7 downto 0); Serer varlable alg: lgnod(7 downto 0); entero i= to_integer (ens); variable entero: Integer ~ Conversién de Integer a signed y unsigned: — Conversion de signed y unsigned a std_logic_vector vo_uneiqned (entero, 8) ; ~ te_signed{entero,8) ; sedrenstd_ logic vector (ana); a5 sedvenatd logic vector (sia) - Conversién de std_logic_vector a Integer y vice-verss ~ Conversién de std_logie_vector a signed y unsigned. eee eereet eter sty < std logic vector (to_uneigned(entero,8)) 7 Cr iT + Las defnicones depos se deben hacer en a prte decaratva dela arquiectura + Eemplo 1. Doficién de un po come una enumeracén para teri en un eulomaa + Lgieos 2 nai 5 aa T1PE eetados 1S (IHACTIVO, OFERANDO, FTHXLIZAR); Pow ae Siem ni moguins T estaases Sor oes oe + Mises Uso: mi_maquina: Ss origin _ a 1 aeate + Ejemplo 2 Dofricin de un tipo bicimensional para oe es implementar una memoria <= menor 0 igual od st aa tee eee > ayer + Sore arcs) std_logic_vector(7 downto 0); >= mayor o igual |_logie y ( » ee + Desplazamiento (signed y ‘abs valor absoluto unsigned) ae ‘st rot, sr Jen Us rot megacion (unaio) i memoria (0) '0"); eee Ejemplo: Un registro de desplazamiento process (ret,clk) Seu begin std togic_vector(7 dowto 0) Sf oo='1! then a Sf up'1" then elaie rleing edge (clk) then CES Sa Hale Sf cowrd" then mes sf load!” then = tee — — ond 48; os ——— 4 < std logic vector q temp) ond 187 end process; a Maquina de estados: FSM + VHDL. ‘93 vs, VHDL ‘87 operators Utiizacion de subtpos: Eo re, eum Vesa; RESTORE Fado a aoe or Dafniion de Estados Si Ss, Sa Pa ge fetitonatonersors Fe fe feeb ‘Tres Bloques Funcionales ==! eet = sn ents Fi ape itt jes — fo ms alien opera ie Loge combinaeona Ueceon ce cant de Fann openor i ado Fo Regis: Mantenen et [ee abe otf Cee minacna ae = VHDL toxt or language reference manual fer loss commonly emein de sans used operators and types uate 9uGate Structures - 6 DERG] 7 EI Clocked Processes 3 3 a) GB iP { 8) =e @4 JB) SSTesgtsucs 4a oP 1 <> conv std tegie Fe vy anceger(s)), 2) and ~ (rabmes => a)? cee ves Pe ZEYo nase 8 Exe) SER @ -p GEIS siete Sa) St HD sai 8 fo 3 3) VES TEx + Ea] OF YO) cna process XSq"Br08!" = Clocked Process Rules Clocked Process Rules ie: men using the 1£/thon construct, only the + alos the cuter 1f/then my tnotude an asynchronous "clock and ha sot or fonet should spear Se he Est or reset bt this sondlcion must appest before” sonsitivity ist. he clock eae condition. eg Proc: proseas (Rat, Ck) on EES LEG) 1 cn ee | Ge ond reeia Foi Fre “Memories/Register Files —— ‘Register File (Memory) Declarations + All memories and repstr files ae ays of words indexed using integers rays mst be declared witha fype eg giz Vector (i downto 917 5! dowato 9) + Then the object (simul or variable) is declared using that type Regseter Data width fotgat Bt a2r_eae ‘subtype Daca Tye te i= ° jects (15 downto 0): + Words are nommally St_ Logie Vector ora subtype cme w Reyieter array declares + Variables use les storage and simulate faster: type Bey sup ae array ey varaante fast sine: signal Regysle_s © neat Two Port Example Ini ization Examples type Reg Typ is array ReySize Typ) of Date ¥ Siee_to a signal RegPile =Tri-States + Use assignment to "2" Sagost <= Lecelpsta when Enb = [othere => 2"); + In simulation, a resolution function combines multiple drivers + Generally one input will be strong '0" or 'I’ and all others will be 'Z’ Tri-State with Two Data Inputs Eablet and Enable? ate mutsaly Cus tne Best pracie ccitee Wat Watate soul lb used ony at be top lvel ofa dosian fr Simple Signal Assignment tetF Ft ye 064 Seda sale Sot [Shana gay Tes a Loop Statements drt iia sin A gi ion endeny attaddee 122 |chmand slater sete ley While condition top ile index> 6 op 1355 {iota tayamer gay {Sequential statements} eats tee ts Codon Syaner pecs ‘end loop; “P ‘end architecture daraflov: {ex countin 127 oop Loy ne for identifier in range lop coment < conn =) wattor as: {sequential statements} mere end oop; fexkin 1 1000p ount = euat = 5 sad op; Conditional Signal Assignment ory EET: the FFTs lei 1164fh niyo i note ed ort Inn) Insta sn stdout ecto (7 downte i Sali sul Ingle vevtrt| dawate Dk Zot sg_logse sector (7 dow nt 0) end entity as architects behavior of me ie he 7 InQafer ns when Sel “(0 ese In after Sms when Sel "1 ese Evaluation oer nd after 5 us whew Sel=“10"ebe " ‘mpc Tn after S ne when Selle “OHIO ater Ss nd architetare behaves + First ue conditional expression determines the output vakie Selected ignment Statement AIP Hd fgks etal Fr ol 2 esl Joie vecor (do Allon mt be + Tho “when othe clause can be used lo ansurs thet all options ‘ate covered {The unaffected” clause may also be used here‘Transport Delays: Sse, [oo Concurrent Processes: Half Adder rary (EEE; ary: proeess use IEEE sid logic 1164 becin cnt altar when = Sim cary sont toch wan TY fend ely bal ake ir = hatter Sw ‘when others archiceturebhavir of half adders Tyre alter Sw Desi nd eam: Sts prawensh) fd process ary pre esta ‘end rehiteture Fs Process + CSAS mem_proo: process (clk) is bevin In(Tising_edge(clk)) then — waid unt next clock edge itreset—"I" then ~ inifalize values om reset sdmom0 =~ x"00 dmemt =»! dmem2 mem’ imomory locations are india some rtadom values elsir MemiViite ‘ease address (1 downto G) Is when “00” => dmemd = write_data: when “DI” > dmemt <= write data: when “10° => dmem2 = wrte_date: whon “II” => dmem3 <= write_data: when others => dmemd <= x cond ease: end it end if end precess read_proc: alto 1 then -i/nor reset then check for memory write Concurrent Processes: Full Adder HAZ: processislc_inyts begin suim <= (31 xerc in) after delays <2 S61 andl cin) ater delay’ ‘end process HA2: brary (EEE tase IEEE std log c64all, entity full_adder is port (In1, in, In2:im std sum, cout out sider cond entity Tull_adder ORE: process (2,63) process describing the two-inpat OR gate begin cout ‘arehitecture behavior! oF full cher & signal s1, 2,23: atd_logic: (2 oF $3) attor delay constant delay ‘Time ~ ns ‘end process OR I: bean ‘end architecture bea ioral: HAL: process (In, [n2) is begin SL (lal xor In2) atter delay 83 (nl and In2) after delay: lend process HAT Processes + CS, Library |EEE. use IEEE std logic. 1164.0 tse IEEE ste logie arta ontity memory i port taddrass, wrle_data:in sté_logie_vector (7 downte Oy ‘Meme, MemRead, elk reset: im stc_toge read_data- out std logic_vecior (7 devnate 0) tnd entiey Premory architecture behavioral of memory Is Sznal dmomo,cmom1,drmeme,dmam3: st losle_vector 7 downto 0}: be mem _proe: process clk s pnicers bo nd process mem_proe: J operation CSA nd architecture behavioral Process + CSAs ‘ad dat dem when ates “ur and MerRead 1° ehe inom hun dso (downto 1-01 anl MemRond=" Tae + processes appear as CSA statements (or vie versa) + capture the same external behavior as CSA statemonts + processes describe mare complex event generation behaviorProcess Behavior + All processes executed once at startup + Thereafter dalaflows determine process initiation + Use of signals vs, variables, + view processes as components wit an interfacesfunctor ® * Forms of the Wail Statement brary IEEE: use IEEE id logic_1 164 at Liar st oxanay U2: var-s2:= var st wor + wait or ny si vat Birest var st mand var a 1 crates nultor gee. delay, wait or 20 ns Pret 2 st ogi. nd process ple: walt for gate_detay, wait for 20: Test. st log + wait on «signa oa cont) ar 022 poe. 23 Pree? wvatten Ro, lke architacture behawot of tg vary L1:8ig. $1 —xcamdy + weit unt eral ig 91,34) eZ std egies 281 32-— 319 8 sora + ait until (ising_edge(c Beast mee sitees 5nd agi mn i 52 und (ising_edge(ch) root :pracess (X92) 8 Process 7 «4 proce + Both sensitivity ists and wait statements cannot be used! Sovialevor-s1 var_22:atd loge, end architecare behavior: Wait Statement: Asynchronous Inputs ibrar IEEE; we IEEE ad fope_1164 alt 28) ch as port iR3, GK: mst opie; ‘2. Qbar eat st ogy cd emtty async sretectne Denavoral of asyrch_f The Wait Statement; Waveform Generation Morary IEEE: clock_procese: pres is tee IEEE std ose N6tal ves a 10 after 10 ms Stee 12 m0 ater sare behviral af wo_phave is ond process clock proces ‘ash Rs cle ‘end architecture behavioral: ‘output: process (F dis: eweute on event on any signal time rset 1,0 afer 10 WRe-0) ten i to septs Q after Sas; * ‘te rose “ LI L ber ee cae rs . ‘VHDL Model of Counter in ALCORTELSED CORTE = ‘ihe PRESENT. SISTE-BIT_VECTERC domo) “BT: Algorithmic Modeling of State Machines * Until now, we showed state machines being modeled by data flow (using concurrent statements) + We will describe using algorithmic or procedural form using conventional programming language semantics process eiaterente ~ waitsttements ~ vasable and signl assignments ~ if end case statements dbop statements Binary Counter State DiagramPiveacy rte; au CASE pe atere 16 sostey POM 2 a TE (Sm = "0") TEEN Boot ( CGE = an 39D coorcs 3 aaptace < 50y SIN : in STD_LOGIC; 37 mnx_state < Slr S00 z our 70 s950¢ VECTOR (2 DomiTo 0))s = ewe ts sochivecouce Behavioral of BM S6 a Se (Sun = "0") TEEN 2 taste Sas ape encedo is (80,51,92,59)7 pe_ette co 897 ‘begin ~ a “ 46 580: PROCESS (RSE, CEE)--Io unkco que ne hace en cambiar al pron dd Te (sm “tor ) tune IP (RST="1") THEN 30. ELSE “ ESTE (CERTEVENT AND CURTIS) THEN 2 ENO PROCESS sea: 3s DRC_PROK ROT: FROSESS (SIR, pe_state)=~ procenon conbinacionales,§7 & | TaN OES nx_state 50; iD casts BID PROCESS DEC_PROX_EST: [DECOD_SALIDAS: PROCESS (SIM, p=_state) peor : ‘CASE pr_state 13 a END TE; ~ 62 ies 90 => 93 WHEN 53 => Tr (sm = ‘0% THR 34 Tr (SIN ~0" ) THEN mote 95 SOUT <= "00"; an 96 ELSE ° 37 SOUT <= "01": se END IF; 33 oy) ae 100 —WHEN OTHERS => no" 101 SOUT <= "90"; us a 103. END CASE; 103 wary $2 —> 105 END PROCESS DECOD_SALIDAS: Tr (SIN =!0" ) Tae Fae = SOUR <= "al"; ELSE 207 : 108 end Behavioral: soul