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4c27e3dbc90c8variador Velocidad Motor CC PDF
4c27e3dbc90c8variador Velocidad Motor CC PDF
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DISEO DE UN SISTEMA DE
CONTROL DE VELOCIDAD DE UN
MOTOR DE CORRIENTE CONTINUA
BASADO EN ACELERMETROS
RESUMEN
El diseo y construccin del hardware del sistema: etapa de potencia (que contendr el driver
El diseo del sistema de control, y su adecuacin al tiempo discreto para su posterior desarrollo
DESARROLLO
1. Estimacin de parmetros fsicos y modelado del sistema
Antes de realizar el diseo del control, es necesario conocer y modelar los distintos parmetros
fsicos que intervienen en el sistema a controlar. Esos parmetros son los siguientes:
Friccin viscosa
Velocidad mxima
Una vez obtenidos dichos parmetros, se ha obtenido un modelo del sistema, a partir de cual
trabajar en el diseo del control, ya que, sin una modelizacin del sistema fsico, habra sido
imposible realizar dicho diseo o las simulaciones pertinentes para comprobar la validez del mismo.
Una primera aproximacin del modelo del sistema podra ser la que se observa en la figura
siguiente:
RESUMEN
La segunda parte del control se basa en dos reguladores PI discretos en cascada, cuyos parmetros
RESUMEN
se fijaron a partir de distintos diseos, que se describen brevemente a continuacin: en una primera
aproximacin se dise aproximando los parmetros por simulacin, para comprobar
posteriormente que este mtodo de diseo no es el ms acertado, y se procedi a disear aplicando
tcnicas de respuesta en frecuencia: diseo por margen de fase y diseo por margen de ganancia.
Ante el comportamiento de la salida con los controles anteriores, se pens que se poda mejorar
filtrando la corriente medida que va al microprocesador. Para ello se disearon dos filtros digitales:
un filtro paso bajo de primer orden, y un filtro FIR paso bajo. Despus de haber rediseado el
control para el sistema incluyendo esos filtros, se comprob mediante simulacin que no
mejoraban, sino que empeoraban la respuesta del sistema.
Una vez claro el regulador que se iba a utilizar (el diseado por tcnicas de respuesta en frecuencia,
sin filtro de corriente), se procedi a realizar un escalado del sistema, para adecuar las variables del
sistema para que pudiesen ser tratadas con registros de 8, 16 32 bits; con el fin de aumentar el
rendimiento del microprocesador.
Por ltimo, una vez escalado el problema con variables de 16 bits, que se vio que resultaban ser las
ms adecuadas, se desarroll el programa que fue implantado en el microprocesador y que gestiona
todos los aspectos del control: toma de medidas mediante conversor A/D, algoritmos de control,
gestin de salidas mediante onda PWM, etc., sobre el sistema operativo en tiempo real FreeRTOS.
RESULTADOS Y CONCLUSIONES
Se muestra a continuacin la respuesta que se obtuvo con el control, ante dos escalones a la entrada
de 0.5 y 0.1 m/s, el primero de los cuales se utiliza para llevar al sistema al rgimen permanente:
Se puede observar una respuesta que se adapta con bastante precisin a la referencia, lo que induce
a pensar que el control ha sido diseado de forma satisfactoria, tal y como demostraron los ensayos.
ABSTRACT
ABSTRACT
OBJECTIVE
The main objective of this project is to design a control system to control the speed of an electric
model railroad, operated by a DC motor, depending on the normal acceleration that it experiments
in every moment. The control will be embedded in a microprocessor. The steps for the design will
be:
Design and construction of the systems hardware: power stage (which contains the motor
driver), and measure signals conditioning circuits (acceleration, current through the motor)
Control system design, and translation to discreet time for its software development and
microprocessor implementation.
DEVELOPMENT
1. Physical parameters estimation
Before the control system is designed, it is necessary to know and model the different physical
parameter values that interfere in the system that is going to be controlled. These parameters are:
Systems mass
Motors inductance
Viscous friction
Maximum speed
Once these parameters have been measured, a systems model can be obtained, which will be the
base to work on in order to design the control. Without a model of the physical system it would
have been impossible to accomplish the mentioned design or the simulations that were performed to
verify its adequacy. A first approximation of the model is shown in the following figure:
ABSTRACT
2. Hardware
The control system needs to interact with the hardware to be useful. The hardware of the system is
composed of a power stage, which links the control and the DC motor, and different conditioning
circuits for the measure signals and the microprocessor.
The power stage is in charge of adequate the output signal of the microprocessor to make it able to
move the DC motor. The main component of this stage is an H bridge.
The signal conditioning circuits adequate the signals that are needed to be measured to feedback the
control with the most sensibility and accuracy possible, and without disturbing the original signal.
In these circuits have been basically used stages based on operational amplifiers, and sensors.
3. Design and implementation of the control system
The control system design can be divided into 2 different parts: a system to generate the speed
reference, depending on the acceleration values measured, and another system that will make the
train follow that reference. These 2 parts have been implemented in a Motorola ColdFire MCF5282
microprocessor.
The reference generations simplified flowchart is shown in the following image:
The second part of the control is bsed on two PI reculators in cascade, whose parameters have been
fixed according to different designs: in the first place, the design was made approximating the
ABSTRACT
parameters by different simulations. This method didnt give very good results, and aftger realizing
that, some techniques of frequency response were applied to the design.
When the behaviour of the output signal of the control system was analyzed, it could be thought
that it could be improved by filtering the measured current that goes into the microprocessor. In
order to do so, 2 digital filters were designed: a first-order low-pass filter, and a los-pass FIR filter.
Afer redesigning the system control including those filters, and after simulating the system, it was
shown that, instead of improving the output, the filters worsed it.
Once the control was selected, a systems escalating was performed, so the microprocessor could
work with 8, 16 or 32 bit variables, in order to increase its performing.
In the last place, once the system and the control was escalated with 16 bit variables (which were
considered the best variable type according to the simulations), the program for the microprocessor
was developed, and it was implanted using the real time operatie system FreeRTOS.
RESULTS AND CONCLUSIONS
The following figure shows the control response with two step-functions in the reference (the first
step, of 0.5m/s was used to take the system into the steady state):
It can be observed that the systems response adapts to the reference with a considerable adequacy,
which induces to think that the control has been designed in a satisfactory way. This premise was
corroborated with the experiments performed.
I.- MEMORIA
MEMORIA
ndice
NDICE
Motivacin ................................................................................................ 10
1.2.
1.3.
Introduccin ............................................................................................. 17
2.2.
2.3.
Introduccin ............................................................................................. 27
3.2.
3.3.
3.4.
3.5.
Conclusiones ............................................................................................ 46
MEMORIA
ndice
Introduccin ............................................................................................. 47
4.2.
4.3.
4.4.
Circuito de acondicionamiento de medida de la intensidad que atraviesa
el motor ................................................................................................................. 63
4.5.
4.6.
4.7.
Conclusiones ............................................................................................ 77
Introduccin ............................................................................................. 79
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
6.2.
MEMORIA
ndice
7.2.
7.3.
MEMORIA
ndice
NCIDE DE FIGURAS
MEMORIA
ndice
MEMORIA
ndice
MEMORIA
ndice
MEMORIA
ndice
MEMORIA
ndice
NDICE DE TABLAS
Tabla 4.1: caractersticas elctricas del circuito ILQ74 ..................................... 54
Tabla 4.2: funciones de cada uno de los pines del L298N ................................. 59
Tabla 4.3: caractersticas elctricas ms relevantes del L298N ......................... 60
Tabla 4.4: Caractersticas del acelermetro ADXL320 ...................................... 68
Tabla 6.1: caractersticas elctricas mximas del MCF5282 ........................... 132
Tabla 6.2: caractersticas elctricas DC del MCF5282 .................................... 132
Tabla 6.3: caractersticas elctricas DC del MCF5282 (continuacin) ........... 133
Tabla 6.4: funciones asociadas a cada mdulo ................................................ 136
MEMORIA
Introduccin
Captulo 1: Introduccin
1.1. Motivacin
Los sistemas automticos de control han desempeado, y desempean, un
papel muy importante dentro y fuera de la industria. Se pueden encontrar
ejemplos de ello ya en el siglo III antes de Cristo, en la Antigua Grecia, con el
diseo del reloj de agua, tambin conocido como Clepsydra, por parte de
Ktesibios. El primer uso del control automtico en la industria parece haber sido
el regulador centrfugo de la mquina de vapor de Watt, en el ao 1775, pero no
fue hasta 1868 cuando se comienza a estudiar la teora del control por
realimentacin, gracias a la explicacin matemtica del regulador centrfugo por
James Clerk Maxwell.
Adems, son muy amplias las aplicaciones que tiene el control de sistemas,
por lo cual el presente proyecto adquiere gran valor didctico de cara a la
incorporacin del alumno al mercado laboral.
10
MEMORIA
Introduccin
11
MEMORIA
Introduccin
12
MEMORIA
Introduccin
13
MEMORIA
Introduccin
SEPT
OCT
NOV
DIC
ENE
FEB
MAR
ABR
MAY
JUN
1
2
3
4
5
6
7
8
14
MEMORIA
Introduccin
15
MEMORIA
Introduccin
o Escalado del problema a 16 bits.
16
MEMORIA
2.1. Introduccin
En el presente captulo se tratarn distintos aspectos del desarrollo
tecnolgico aplicado hoy en da tanto a sistemas de control de trenes como a
control de velocidad de motores. Tambin se expondr brevemente la evolucin
tecnolgica a largo de la historia de dichas disciplinas.
17
MEMORIA
Estado del arte
largo, pues todava est en operacin en las redes francesa y belga. El trmino
"Crocodile" deriva de la forma del dispositivo de la rampa colocada entre los
carriles, que se utiliza para establecer un contacto galvnico (electromecnico) y
transmitir informacin a la locomotora.
A partir de ese momento, la introduccin del primer verdadero sistema de
control del tren estaba slo a un paso. Alrededor de 1870, Axel Vogt, el jefe de
mecnicos del ferrocarril de Pennsylvania coloc un tubo de vidrio en la cabina,
conectado con el tubo del freno neumtico. Si un tren sobrepasaba una seal de
parada, una palanca de la seal golpeaba y rompa el tubo de vidrio y se
aplicaban los frenos.
El primer sistema de control del tren utilizado a gran escala fue el ATC
(control automtico del tren) de la compaa britnica GWR, que fue introducido
en 1906. El ATC se bas en el sistema francs "Crocodile" pero, adems de la
seal acstica, el ATC tambin tuvo desde el principio mtodos de visualizacin
mecnica en la cabina y de accionamiento automtico del freno de emergencia.
Aunque el ATC y los sistemas similares han experimentado varias
modificaciones, el principio de base es el mismo, y todava se utiliza hoy.
En 1920, el ferrocarril de Pennsylvania introdujo el sistema de CCS
(Continuous Cab Signals), que a menudo est considerado como un hito en la
historia del control del tren. El CCS es el antepasado de muchos sistemas
existentes, incluyendo el BACC italiano y el ATB holands. En vez de contactos
electromecnicos (y sus partes mviles posibles fuentes de averas), el CCS se
basa en un contacto inductivo entre circuitos cifrados en la va y un receptor en
la locomotora. Desde el principio fueron utilizadas luces de colores para
anunciar en la cabina el aspecto de la prxima seal. El sistema original tena
dispositivo de intervencin automtica del freno, pero fue desactivado ms
adelante por algunas compaas. El CCS anunciaba las seales en la cabina tan
correctamente que algunas compaas ferroviarias americanas quitaron las
seales laterales para reducir gastos de explotacin. Despus de la primera
guerra mundial, CCS fue transferido a la Unin Sovitica. En lo que se refiere a
longitud de lneas equipadas, CCS es el sistema mayoritario en el mundo.
18
MEMORIA
Estado del arte
Mientras, en Alemania, Siemens comenzaba el desarrollo de Indusi, el primer
sistema de control aplicado a gran escala que incorpor la supervisin de la
curva de frenado. De una forma semejante al CCS americano, tambin utiliza
induccin para transmitir la informacin, pero la transmisin tiene lugar
solamente en puntos discretos, mediante circuitos magnticos en la locomotora y
en las seales. Debido a su confiabilidad, a la simplicidad y a la capacidad de
parar el tren antes del punto de peligro, Indusi y sus derivados se convirti en el
sistema de control ms popular en buena parte de Europa (Alemania, Austria,
Polonia, la antigua Yugoeslavia, Rumania, Turqua).
La transmisin de informacin mediante transponders es ms reciente y en
ella se basan los sistemas espaoles ASFA y el sueco EBICAB (en Espaa se
utiliza la versin EBICAB 900). Mas reciente an es la transmisin sin hilos que
es el sistema utilizado por el europeo ERTMS y sus antecesores FFB
(FunkFahrBetrieb) y FZB (FunkZugBeeinflussung) de la Deutsche Bahn.
Basados en los "antepasados" comunes (el Crocodile francs, el CCS
americano y el Indusi alemn, los tres sistemas de control han evolucionado
histricamente de maneras muy diferentes en las distintas compaas
ferroviarias. Los sistemas modernos incluyen el clculo dinmico en tiempo real
del perfil de la velocidad. En 1990, haba por lo menos 30 diversos sistemas de
control del tren en operacin en la red europea de va ancha. A pesar de los
antepasados comunes, casi todos los sistemas existentes son completamente
incompatibles. La creacin de las eurobalizas y sobre todo de ERTMS, debe
terminar con esta "torre de Babel de estndares".
Sistemas
"auxiliares"
(sealizacin
lateral
prominente,
la
MEMORIA
Estado del arte
en lneas de cercanas y metro con mucha densidad de trfico. Los
sistemas mensajes que son evaluados en el computador central del
vehculo. El sistema supervisa continuamente la velocidad del tren, y
gobierna su marcha por medio de sistemas que controlan la traccin y el
frenado del vehculo (como por ejemplo el sistema ATF, Automatismo
de Traccin y Frenado, de las locomotoras de la serie 252 de Renfe. El
equipo del vehculo emite la posicin del tren, velocidad, caractersticas
de frenado y otras informaciones al sistema central para su posterior
tratamiento y realimentacin del sistema.
20
MEMORIA
Estado del arte
intervalos tericos de entre 2 min 20 seg y 2 min 50 seg dependiendo de
las configuraciones de la va.
21
MEMORIA
Estado del arte
ATO (Conduccin Automtica de Tren, del ingls Automatic Train
Operation)
El sistema de conduccin automtica se compone de un conjunto de
equipos, que situados en va y tren sustituyen la funcin del conductor,
excepto la apertura y cierre de puertas y la orden de arranque.
Este modo de conduccin est bajo la supervisin del ATP que
indica al sistema las velocidades mximas para cada tramo, y
proporciona un menor tiempo de recorrido y un mejor confort de
marcha respecto a la conduccin en Manual con ATP.
El tren puede recibir diferentes tipos de rdenes y en especial la de
velocidad de marcha por regulacin de trfico que se realiza desde el
Puesto Central a travs del SIRAT.
Tambin permite la maniobra de vuelta en terminales (autoshunt),
sin conductor en una de las cabinas (la de entrada al saco), siempre que
existan cdigos de ATP.
Para la correcta parada de los trenes en las estaciones existen en la
va una serie de balizas denominadas X1, X2 y X3. Por medio de ellas
es posible transmitir datos de geometra de va al tren y desde el Puesto
Central rdenes como por ejemplo; el paso sin parada en la estacin,
situacin del punto de parada, velocidad en la interestacin, perfil de
va, autoshunt, etc.
22
MEMORIA
Estado del arte
El Sistema Integrado de Regulacin Automtica de Trenes est
plenamente integrado en las lneas con circulacin en ATO, este
sistema permite, por medio de una simulacin predictiva, un ajuste
preciso en la regularidad de los trenes, utilizando las diferentes
velocidades que las balizas de ATO pueden transmitir al tren en las
interestaciones. As mismo en las lneas no dotadas de ATO realiza la
regulacin mediante el uso de las seales.
Como resultado de estos ajustes en la regulacin se mejora la
capacidad de transporte de las lneas y se consiguen unos elevados
ahorros de energa derivados de la aplicacin de marchas con menor
consumo de los trenes y evitando paradas por regulacin en las
estaciones.
Otra de las prestaciones del sistema son los informes en tiempo real
en forma de grficos de los ndices de calidad de la regularidad.
Distancia Objetivo
En este sistema el tren recibe de la instalacin de va no slo la
velocidad mxima a la que el tren puede circular en el cantn por el que
circula, sino tambin que cantn precedente se encuentra ocupado por
otro tren. De esta forma, cada tren tiene informacin de la distancia que
le queda por recorrer hasta el cantn realmente ocupado por delante.
Con ello se posibilita un mayor acercamiento de cada tren a su
precedente, reducindose el intervalo entre trenes en la lnea y
aumentando la capacidad de transporte de la misma.
Cantn mvil
En este sistema el tren va informando va radio permanentemente a
un sistema de control ubicado en la instalacin fija de su situacin. A su
vez, cada tren recibe informacin va radio acerca de la situacin del
23
MEMORIA
Estado del arte
tren anterior, de esta forma un tren puede aproximarse al mximo al
tren precedente segn lo que su parbola o distancia de frenado le exija
(en funcin de su velocidad, el perfil de va, tiempos de respuesta y
seguridad, etc.)
La diferencia fundamental con el sistema anterior es que su
proximidad es relativa al tren anterior y no a un cantn ocupado, ya que
ste en funcin de su longitud provoca unas distancias mayores entre
trenes, esto es, un mayor intervalo.
MEMORIA
Estado del arte
Un motor primo trifsico que mueve al rotor del generador de cc el cual se usa
para alimentar un voltaje de cc a un motor de cc; a ste sistema se le llama
Ward-Leonard y es extremadamente verstil. El voltaje de armaura se puede
variar mediante cambios en la corriente de campo en el generador de cc, ste
voltaje de armadura permite que la velocidad del motor pueda variarse
suavemente entre un valor muy pequeo y la velocidad base. La velocidad del
motor puede ajustarse por encima de la velocidad base reduciendo la corriente de
campo del motor, por eso es que este sistema es tan flexible que permite control
total de la velocidad del motor. Adems permite tambin el cambio del sentido
de rotacin, solamente cambiando la polaridad del voltaje de armadura, as es
posible obtener un rango muy amplio de variacin de la velocidad en cualquier
sentido de rotacin. Otra funcin es la de regenerar o retornar a las lneas de
alimentacin la energa de movimiento de las mquinas. Si una carga pesada se
eleva y luego se baja mediante el motor de cc de un sistema Ward-Leonard,
cuando la carga esta cayendo, el motor de cc actua como generador,
suministrando potencia hacia el sistema de ca. En esta forma, mucha de la
energa requerida en el primer momento para alzar la carga puede recuperarse
reduciendo el costo total de operacin de la mquina. La desventaja del sistemna
Ward-Leonard, es la de tener que comprar tres mquinas completas de valores
nominales esencialmente iguales, lo cual es muy costoso. Otra es que tres
mquinas son mucho menos eficientes que una, por ello han sido reemplazado
por circuitos controladores basados en SCRs , que resultan definitivamente ms
barato que dos mquinas extra.
MEMORIA
Estado del arte
como motor al convertir la potencia que se le suministra a travs del
autotransformador en potencia mecnica disponible en el eje. Las mayores
aplicaciones de los sistemas de Leblanc y Kramer son para grandes motores de
rotor bobinado de 500 CV hasta unos 3000 CV. Las ventajas de devolver la
energa al sistema, adems de las bajas prdidas en lnea del convertidor y el
autotransformador (el aparato elctrico de mayor rendimiento desarrollado hasta
el momento), combinado con la ventaja de correccin del factor de potencia,
hace que el sistema de Kramer sea particularmente til en aplicaciones de
control de velocidad de elevada potencia. Su mayor inconveniente reside en su
elevado costo inicial.
26
MEMORIA
3.1. Introduccin
Se define sistema como un elemento o conjunto de elementos que da una
respuesta o salida ante una determinada excitacin o entrada. Existen diversos
tipos de sistemas, clasificados atendiendo a distintas caractersticas o
propiedades de los mismos, pudindose clasificar el sistema que se va a tratar a
continuacin como un sistema cuantitativo (se puede tratar siguiendo modelos
matemticos), dinmico (su respuesta en un instante depende de valores
anteriores de la entrada, y no slo del valor de la entrada para ese instante),
lineal (se cumple el principio de superposicin para las ecuaciones del modelo),
e invariante en el tiempo (el sistema va a ser el mismo en cualquier instante de
tiempo). Aquellos sistemas lineales e invariantes en el tiempo suelen
denominarse comnmente LTI, del ingls linear time-invariant.
27
MEMORIA
d n y(t )
d n1 y(t )
dy(t )
a
+
+ ... + a1
+ a0 y(t ) =
n 1
n
n 1
dt
dt
dt
d m y(t )
d m1 y(t )
dy(t )
b
= bm
+
+ ... + b1
+ b0 y(t )
m1
m
m1
dt
dt
dt
an
[3.1]
X (s ) = L{x(t )} = x( )e s d
[3.2]
28
MEMORIA
Modelado del sistema
ms adelante, se puede consultar cualquier texto sobre ecuaciones diferenciales,
como por ejemplo las referencias bibliogrficas nmero 6, 7 y 8.
CONTROL
CONVERTIDOR
DE POTENCIA
SISTEMA A Salida
CONTROLAR
SENSOR
Figura 3.1: diagrama funcional de bloques de un sistema de control
continuo tipo.
El bloque de control consistir en dos lazos de control proporcional integral
discretos, implantados en un microprocesador. Como se puede apreciar en la
figura 3.2, el primero de esos bloques de control, compara la referencia de
velocidad con la medida de la misma mediante un sensor, que en este caso est
representado por la ganancia Ks. Despus de aplicar su accin proporcionalintegral, que se ver con ms detalle en el captulo de Software y sistema de
control, obtiene como salida un valor de corriente (el cual oscilar entre dos
valores, mnimo y mximo, que sern los valores de saturacin, por encima de
los cuales, en valor absoluto, el motor podra sufrir daos), que ser denominada
corriente de referencia de ahora en adelante, y que se introduce como entrada en
otro bloque de control. Este segundo bloque de control comparar dicha
corriente de referencia con la corriente real que circula por el motor en cada
instante, para, posteriormente, aplicar su accin proporcional-integral, y generar
una seal (mando), que, debidamente acondicionada, tras pasar por la etapa de
29
MEMORIA
Modelado del sistema
potencia, representa la tensin de alimentacin del motor en un instante
determinado.
30
MEMORIA
control
es
el
que
muestra
la
figura
3.2:
31
MEMORIA
Figura 3.2: Primera aproximacin del diagrama funcional de bloques del sistema completo
32
MEMORIA
l
S
[3.3]
R( a ,b ) =
1
dl
S
[3.4]
Rab =
L
1 Lab
= ab
S
S
[3.5]
Una vez demostrado, queda comprobar lo enunciado con anterioridad, esto es,
que la resistencia elctrica que ofrecen las vas es despreciable respecto a la
resistencia interna del motor. Para ello se realiz un ensayo experimental, viendo
cmo cambiaba la resistencia del conjunto motor-vas conforme se desplazaba el
tren por las mismas de forma manual (esto es, sin aplicarle ninguna tensin al
motor). De este ensayo se sac la conclusin de que la resistencia de las vas es
33
MEMORIA
Modelado del sistema
despreciable, ya que, a lo largo de todo el circuito, la resistencia del conjunto
variaba como mximo 1 sobre 35 .
Para obtener dicha variable con la mayor precisin posible, se almacenan los
datos del osciloscopio en un fichero .txt, llamado corriente.txt, y desde
Matlab se efectan las operaciones pertinentes mediante un fichero .m, llamado
leer_datos.m (ver anexo 2 para ms informacin) con el fin de representar
dicha corriente, dando como resultado:
34
MEMORIA
I (t ) = I () + ( I (0 ) I ()) e
[3.6]
t
I (t ) I ()
Ln
+
(
I
(
0
)
I
(
[3.7]
35
MEMORIA
Modelado del sistema
leer_datos.m, se obtiene un valor para la constante de tiempo de la exponencial
de:
= 5.6662 10-5 s
U em
U em t L
I ( s) =
i (t ) =
e
R + Ls
L
[3.8]
Por lo tanto,
L
R
[3.9]
L = 2 mH
36
MEMORIA
asociada
la
fuerza
A partir del circuito elctrico del actuador (motor DC), se concluye que:
Fm = i K m =
u em
K m
R + Ls
[3.10]
Fm(0) = i(0) K m =
u em
K m
R
[3.11]
i=
u em
em = u R i
R
[3.12]
em = K e v
[3.13]
Para el clculo de la friccin viscosa por rozamiento del tren con las vas, as
como para el clculo de la constante del par motor (Km) y de la constante asociada
a la fuerza electromotriz del motor (Ke) se realiz el siguiente experimento: sobre
un circuito circular, se le hizo al tren completar N vueltas a dicho circuito,
midiendo el tiempo que tardaba en completar las N vueltas. Este proceso se repiti
varias veces, aplicando distintas tensiones al motor del tren cada vez. A su vez,
tambin se midi el valor medio de la corriente que suministraba la fuente con la
que se aliment el motor a este. Todas las medidas mencionadas, representan las
magnitudes medidas en rgimen permanente.
37
MEMORIA
Km = 5.8347 Nm/A
38
MEMORIA
3.2.5. Clculo de la friccin viscosa
Debido al rozamiento que se produce entre las ruedas del tren y las vas, y a
posibles holguras en los engranajes del motor, se produce un efecto de friccin
que se puede modelar como una friccin viscosa.
v=
1
D
1
(Fm Ff ) =
(Fm Ff )
M
Ms + D
s +1
D
[3.14]
v(0) = vs= j , =0 =
1
D
(Fm Ff ) Dv + Ff = Fm [3.15]
M
j + 1
D
Fm = i K m =
u em
K m
R + Ls
[3.16]
Fm() = i() K m =
u ( ) em ( )
K m
R
[3.17]
39
MEMORIA
figura 3.6: fuerza del par motor en funcin de la velocidad del tren
desarrollada en el experimento.
Como la fuerza del par motor si no hay perturbaciones se puede expresar como
el producto entre la friccin viscosa y la velocidad, se puede afirmar que la
friccin viscosa asociada al rozamiento del tren con las vas ser la pendiente de la
recta anteriormente representada.
Por tanto: D = 0.6703
Nms/rad
= 0.7kg
40
MEMORIA
3.2.7. Estimacin de la velocidad mxima
41
MEMORIA
v
Ff
m
Fm
M
D
x
d 2 x(t )
dx(t )
dv(t )
Fm Ff = M
+
D
Fm
Ff
=
M
+ Dv(t ) [3.18]
dt
dt
dt 2
Aplicando la transformada de Laplace, se obtiene:
Fm(s ) Ff (s ) = (M s + D ) V (s )
[3.19]
V (s ) =
Fm(s ) Ff (s )
M s + D
[3.20]
42
MEMORIA
Modelado del sistema
Como el sistema es lineal, si se supone nula la perturbacin (Ff(s)), la ecuacin
anterior queda:
V (s ) =
Fm(s )
V (s )
1
=
M s + D Fm(s ) M s + D
[3.21]
MEMORIA
[3.22]
em = K e
[3.23]
di
L + R i = V K e
dt
[3.24]
Donde:
di
V L = L
dt
[3.25]
(Ls + R )I (s ) = V K e I (s ) = V K e
Ls + R
[3.26]
[3.27]
d
+ Dm = Tm TR = K m i TR
dt
[3.28]
Donde:
J: es el momento de inercia del motor.
Dm: es la constante de friccin viscosa del motor.
44
MEMORIA
Modelado del sistema
Como se puede observar, el modelo del motor trabaja con parmetros propios
de un sistema mecnico de rotacin, sin embargo, en la planta se ha utilizado un
modelo de sistema mecnico de traslacin. Tanto el momento de inercia como la
constante de friccin viscosa del motor estn tenidos en cuenta en la masa y la
constante de friccin viscosa de la planta. La velocidad angular del eje del motor,
multiplicada por el radio de las ruedas y por la constante obtenida de las
reductoras a las que aplica su par el motor, se transforma en la velocidad lineal
que adquiere la planta al ser aplicado el par del motor. Por ltimo, el par de carga
del motor ya viene dado como la fuerza de carga Ff, que se aplica sobre la planta.
45
MEMORIA
3.5. Conclusiones
A lo largo del captulo se ha expuesto la metodologa seguida para obtener los
distintos parmetros necesarios a la hora de disear el control, as como la base
terica sobre la que se sustentan los clculos realizados para dicha obtencin de
los mencionados parmetros.
46
MEMORIA
Hardware
47
MEMORIA
Hardware
se
detallar
ms
adelante
el
proceso
de
MEMORIA
Hardware
de transistores activados, la corriente fluye en uno u otro sentido, lo que permite
controlar el sentido de giro del motor.
49
MEMORIA
Hardware
Cuando una fuerza externa mueve el eje de un motor, este produce electricidad,
es decir, se comporta como un generador de corriente elctrica. Si se conecta una
carga a los terminales del motor, entonces presentara una resistencia al giro
proporcional al valor de la carga que tiene conectada. De este modo, a medida que
la carga aumenta el motor presenta una mayor resistencia a girar. Pero si se
conectan los dos terminales de motor entre s, se produce el mismo efecto que si el
motor estuviese conectado a una carga infinita. El resultado final es que el motor
se para porque no puede vencer esa resistencia.
50
MEMORIA
Hardware
por la cada de tensin de los transistores. En este caso, los transistores actan
como un cable que une los dos terminales del mismo motor, producindose el
efecto comentado anteriormente de que el motor debe hacer frente a una carga
infinita. Como no puede, se para prcticamente en seco en el momento en que se
activa esta configuracin.
[4.1]
Donde:
DC es el ciclo de trabajo (o duty cycle)
es el ancho de pulso (o pulse width), esto es, el tiempo en que la funcin es
positiva
T es el perodo de la funcin.
51
MEMORIA
Hardware
el valor de tensin continua que tiene la entrada (esta afirmacin slo es cierta si
se est en rgimen permanente).
1
< x(t ) > = x(t ) dt
T0
[4.2]
Para seales con forma sencilla, como la onda cuadrada que se ha empleado en
el presente PWM, se puede calcular su valor medio como:
1
< x(t )cuadrada > = (DT (1 D )T )x(t ) = (2 D 1)x(t )
T
[4.3]
52
MEMORIA
Hardware
Puente en H
Optoacoplador
Salida PWM
43
Inversor
Puente de diodos de
libre circulacin
Figura 4.4: Esquema del circuito de la etapa de potencia
53
MEMORIA
Hardware
54
MEMORIA
Hardware
55
MEMORIA
Hardware
56
MEMORIA
R1 =
Hardware
3 V 1 .2 V
= 45 normalizad a
40 mA
R1 = 43
3 V 1 .2 V
= 41.86mA potencia de R1 PR1 = 41.86mA 1.8V = 75mW
43
5V
= 200 para ese valor de R2, el fototransistor estar
25 mA
57
MEMORIA
Hardware
alcance una tensin lo ms cercana posible a 5V en ese instante, de tal
forma, que entonces Q1 est saturado:
5V 0.7V
= 0.741mA
0 .2 + R 3
iC
VCEsat + ic R 4 = 5V ic =
4.8V
= 4.8mA < 37.05mA R 4 = 1k
R4
58
MEMORIA
Hardware
Para obtener como salida del circuito una onda PWM entre -14V y 14V,
as como por motivos de suministro de corriente, como se ha comentado con
anterioridad, se ha utilizado un puente en H L298N, cuyo funcionamiento se
ha descrito con anterioridad, conectando su entrada Vs a 14V. Se especifican
a continuacin las caractersticas ms relevantes del L298N:
59
MEMORIA
Hardware
60
MEMORIA
Hardware
61
MEMORIA
Hardware
62
MEMORIA
Hardware
MEMORIA
Hardware
Estimador del
mdulo de corriente
Diodo de proteccin
del micro
Estimador analgico
de la velocidad
Diodo de proteccin
del micro
Figura 4.12: circuito de acondicionamiento de medida de la intensidad que atraviesa el motor
64
MEMORIA
Hardware
1+
R7 0.4 A R8 = 13 k
R7
Donde:
v o = Rs i
Km i
1
R11
0 .6
R11 )
1 +
1 +
= Rs i
; v =
R9 C 3 s + 1 R10
0.6R9 C 3 s + 0.6 R10
M s + D
65
MEMORIA
Hardware
R11 = 6.8 k
R11 vo MAX
3
R11
K m =
5.8347
25
= )
0.6Rs 1 +
1 .2
R10
R10 v MAX
R10 = 270
C = 10 F
0.6 R9 C 3 = M = 0.7
R9 = 150 k
0.6 D = 0.67
Donde:
66
MEMORIA
Hardware
mismo. De este modo, el microprocesador queda protegido ante eventuales picos
de tensin en sus entradas.
Sensor N: Normal
Sensor T:
Tangencial
Direccin del movimiento
Figura 4.13A: situacin del acelermetro sobre la maqueta del tren
El circuito de acondicionamiento de la seal del acelermetro tiene por objeto
adecuar la seal que proporciona dicho componente, para poder ser medida con la
mayor precisin y sensibilidad posibles por el microprocesador, utilizando su
conversor analgico/digital.
67
MEMORIA
Hardware
68
MEMORIA
Hardware
69
MEMORIA
Hardware
Etapa de ganancia
Filtro paso alto
Salida ADXL320
Rectificador de precisin
70
MEMORIA
Hardware
La primera etapa es un filtro paso alto a 0.5 Hz para eliminar la continua. Los
clculos para el mismo han sido los siguientes:
R1 = 100k fijada
C1 =
1
= 3.18uF
2 R f c
R 7 = 5 .6 k
R7 + R8
= 4.74
R8
R8 = 1.5k
71
MEMORIA
Hardware
Vout
1
Vin
-1
Typ Wavelength:740nm
Sensibilidad:0.5
Half Angle:20
Dark Current:0.2nA
rea activa:0.13mm
72
MEMORIA
Hardware
Negador
Inversor
Resistencia
de entrada
al sumador
Diodo LED
Acondicionamiento del
fotodiodo
Figura 4.16: Circuito de una baliza
73
MEMORIA
Hardware
Se quiere conseguir que cuando el tren cruce el haz de luz que emite el LED
hacia el fotodiodo, se enve una seal de 3.3V al microprocesador, y que en caso
contrario, la seal permanezca por debajo de los 1.15V, que es el umbral para que
una seal se considere a nivel bajo. Para ello se ha diseado el circuito de la figura
4.16, que se explica a continuacin.
En primer lugar se ha diseado el circuito que alimenta al diodo LED para que
est siempre encendido. Segn la hora de caractersticas del mismo, la corriente
que atraviesa el diodo cuando est polarizado directamente es de 7mA, y la cada
de tensin es de 1.8V. Segn esto, y sabiendo que la tensin de alimentacin es de
5V, se puede calcular R14:
R14 =
5V 1.8V
= 0.46k R14 = 0.47k
7 mA
74
MEMORIA
Hardware
De forma emprica se determin que, para que cuando el haz de luz estuviese
interrumpido por el tren se obtuviese una salida aproximada de -0.5V, y cuando
no estuviese interrumpido se obtuviese una salida aproximada de -2V, la
resistencia R1 deba ser de 0.33k.
Saturacin :
VC = 5
R 4 = 4 .7 k
2 0 .7
1 .3
R4
R 4 0 .2 R 4 4 .8
0.037
R3
R3
R3
R3 = 100k
75
MEMORIA
Hardware
Al ser 0.5 menor que 0.7, el corte se produce automticamente cuando el haz
de luz que incide en el fotodiodo se corta. Para que la cada de tensin en R4 sea
la menor posible cuando se produce el corte, R11 tendr que ser grande en
comparacin con sta, por ello se ha elegido un valor de 100k para ella, lo que
produce una cada en R4 cuando Q1 est en corte de 0.22V, obteniendo los
siguientes valores en el colector de Q1:
76
MEMORIA
Hardware
Proteccin
Sumador
Inversor
4.7. Conclusiones
Se ha expuesto en el presente captulo todo lo relacionado con el hardware del
sistema: desde la etapa de potencia, que servir de nexo entre el control y el
actuador, hasta los reguladores de tensin que han sido utilizados, pasando por los
diferentes circuitos de acondicionamiento de seal.
77
MEMORIA
Hardware
En las siguientes tres secciones se han abordado los distintos circuitos de
acondicionamiento de seal: la medida de la corriente que atraviesa el motor, el
acondicionamiento de la seal del acelermetro, y el diseo de las balizas. Como
ya se ha expuesto, estos circuitos cumplen la funcin de acondicionar las seales
que se desean medir para realimentar el control de manera que dicha medicin se
efecte con la mayor precisin y sensibilidad posibles, y sin perturbar a la seal
original. Para ello se han utilizado bsicamente etapas basadas en amplificadores
operacionales, tanto en realimentacin negativa como en bucle abierto, diodos
zener para la proteccin del microprocesador, y los propios elementos cuya seal
se haba de acondicionar.
78
MEMORIA
Sistema de Control
5.1. Introduccin
Se utiliza como sistema de control un regulador con accin proporcionaldiferencial (PI) discreto, que va programado en un microprocesador
MC9S08QG4/8. Para realizar el ajuste de los distintos parmetros del control se
han utilizado diferentes herramientas informticas (Matlab y Simulink) para
simular la respuesta del sistema ante distintas entradas o hallar su respuesta en
frecuencia.
79
MEMORIA
Sistema de Control
su nmero de muestra k. En la figura 5.1(b) se observa una secuencia yk = {y0, y1,
y2, . . .}, que proviene de una seal analgica y(t) (figura 5.1(a)), con la relacin
entre muestra k e instante de tiempo kT. La eleccin del periodo de muestreo es
muy importante puesto que un valor demasiado grande hace que se pierda
informacin cuando se muestrean seales rpidas (figuras 5.1(c) y 5.1(d)), que en
el caso de tratarse de un problema de control provendrn de sistemas rpidos. Es
lo que se conoce como efecto aliasing.
80
MEMORIA
Sistema de Control
Perturbacin
-
Ref.
CONTROL
POT
SISTEMA A Salida
CONTROLAR
Retenedor
(Hold)
T
Muestreador
(Sampler)
SENSOR
Sistema Digital
[5.1]
Para obtener:
[5.2]
81
MEMORIA
Sistema de Control
[5.4]
82
MEMORIA
Sistema de Control
[5.5]
[5.6]
Por lo tanto para obtener el regulador discreto a partir del continuo basta
sustituir en la funcin de transferencia las s
por
z[ 5.7]
1 K (1 + Ti s )
=
C ( s ) = K 1 +
T
s
Ti s
i
[5.8]
83
MEMORIA
Sistema de Control
20log(K)
1/Ti
84
MEMORIA
Sistema de Control
una seal discreta, se puede demostrar que el valor de la funcin y en un instante
u[k 1] integral inferior de Riemann
1
[5.9]
85
MEMORIA
Sistema de Control
86
MEMORIA
Sistema de Control
Figura 3.2: Primera aproximacin del diagrama funcional de bloques del sistema completo
87
MEMORIA
Sistema de Control
Los parmetros del control han sido diseados varias veces, atendiendo a
distintos criterios, y utilizando distintas tcnicas de diseo. Una vez obtenidos
todos los resultados, se ha elegido aqul que mejor satisface las necesidades del
sistema.
Todos los diseos se han realizado en base a una aproximacin lineal del
sistema equivalente continuo, obtenida a partir de la herramienta Linear
Analisys, contenida dentro de la toolbox de control de Matlab y Simulink. En
cuanto a las distintas simulaciones del sistema, realizadas para comprobar la
eficacia del regulador diseado, en una primera aproximacin, se supuso el
sistema como continuo, a excepcin de los bloques de control, sin tener en cuenta
el efecto de la onda PWM sobre el resto del sistema (se supuso que la frecuencia
de dicha seal era lo suficientemente alta como para que los valores medios del
resto de las seales del sistema slo se viesen afectados en un ligero rizado
alrededor de dicho valor medio). Ms adelante, y ante respuestas del sistema
inesperadas, debidas al desprecio de efectos fsicos no modelados, se fueron
aadiendo al modelo del sistema elementos que simulaban dichos efectos fsicos,
tales como retrasos en la actualizacin de los valores, distintos tiempos de
muestreo para los distintos bloques de control, efectos de la seal de PWM, etc.
Todo ello se explica con detenimiento a continuacin.
88
MEMORIA
Sistema de Control
1
tensin, sino como dicha tensin directamente ). Adems, se trabaj con el mismo
tiempo de muestreo para los dos bloques de control, resultando ste demasiado
rpido para lo que el microprocesador puede ofrecer. El diagrama de bloques del
sistema completo se puede observar en la figura 3.2.
Al incluir el control y aplicar las propiedades del lgebra de bloques para cerrar
el lazo de corriente, se obtiene una funcin de transferencia de segundo orden
entre su entrada y su salida. Se pueden modelar pues sus parmetros de forma
analtica, de modo que adquieran los valores que se desee.
G( s ) =
(1 + Ti s )
K (1 + Ti s )
=
Ti s (R + Ls ) + K(1 + Ti s ) Ti L s 2 (R + K )Ti s + 1
K
K
[5.10]
1
, se puede apreciar que tiene el
M s + D
aspecto de un filtro paso bajo, de frecuencia de corte: f c D = 0.152 Hz , por tanto, es de
2 M
esperar que filtre las fluctuaciones de velocidad que pudieran surgir debido a las conmutaciones de
la onda PWM.
1
89
MEMORIA
Sistema de Control
Se observa que G(s) es un sistema de segundo orden con un cero adicional. Por
tanto, su respuesta ser la suma de la respuesta del sistema de segundo orden ms
la derivada de dicha respuesta. En lo que concierne al diseo, slo se tendr en
cuenta la respuesta del sistema de segundo orden:
K
n =
Ti L
1
R + K Ti
G ( s) =
=
Ti L 2 (R + K )Ti
2
K L
s
s + 1
G (0) = 1
K
K
[5.11]
Ti =
0.00392
625
+ 50 + K
K
[5.12]
90
MEMORIA
Sistema de Control
Teniendo en cuenta la relacin anterior, se ensay la respuesta del lazo de
corriente linealizado frente a un escaln de 0 a 0.2A con distintos valores de K y
Ti:
-Ensayo 1: K = 9.5;
Ti = 3.1288e-005; wn = 1.2321e+004
91
MEMORIA
Sistema de Control
92
MEMORIA
Sistema de Control
- Ensayo 1: Ti = inf; K = 5
- Ensayo 2: Ti = inf; K = 10
- Ensayo 3: Ti = inf; K = 15
- Ensayo 4: Ti = inf; K = 25
- Ensayo 5: Ti = inf; K = 50
93
MEMORIA
Sistema de Control
- Ensayo 1:
K = 25; Ti = 100
- Ensayo 2:
K = 25; Ti = 1
- Ensayo 3:
K = 25; Ti = 0.1
- Ensayo 4:
K = 25; Ti = 0.01
- Ensayo 5:
K = 25; Ti = 0.001
94
MEMORIA
Sistema de Control
valor de Ti. Las figuras 5.13 y 5.14 son distintas respuestas del mando de corriente
y del mando de tensin en funcin de los distintos valores de Ti. Los valores de
los parmetros utilizados en cada ensayo se detallan a continuacin de las
grficas. En la figura 5.10 se observa el diagrama de bloques del sistema
simulado:
95
MEMORIA
Sistema de Control
96
MEMORIA
Sistema de Control
97
MEMORIA
Sistema de Control
98
MEMORIA
Sistema de Control
Valores utilizados en la figura 5.12:
- Ensayo 1:
K = 5;
Ti = 0.01
- Ensayo 2:
K = 10;
Ti = 0.01
- Ensayo 3:
K = 15;
Ti = 0.01
- Ensayo 4:
K = 25;
Ti = 0.01
- Ensayo 5:
K = 50;
Ti = 0.01
- Ensayo 1:
K = 25;
Ti = 0.001
- Ensayo 2:
K = 25;
Ti = 0.005
- Ensayo 3:
K = 25;
Ti = 0.01
- Ensayo 4:
K = 25;
Ti = 0.02
- Ensayo 5:
K = 25;
Ti = 0.05
Una vez concluidos todos los ensayos, los valores escogidos fueron los
siguientes:
K=25, Ti = 0.005
99
MEMORIA
Sistema de Control
Al realizar la simulacin del sistema con los parmetros del control
seleccionados anteriormente, se obtuvo la siguiente respuesta:
100
MEMORIA
Sistema de Control
Retardo en la
actualizacin
del mando
Modulacin
PWM
Figura 5.17: diagrama de bloques del sistema, incluyendo retardos de actualizacin de salidas y efecto del PWM
101
MEMORIA
Sistema de Control
PI 2
PI 1
Retardo en la
actualizacin del mando
y retardo por el
retenedor de orden cero
Figura 5.18: diagrama de bloques del lazo de control completo abierto, en tiempo continuo
102
MEMORIA
Sistema de Control
PI 2
Retardo en la
actualizacin del mando
y retardo por el
retenedor de orden cero
Figura 5.19: diagrama de bloques del lazo de control de corriente abierto,
en tiempo continuo
e 1.5t s s
[5.13]
[5.14]
G ( j 0 ) dB = 17.7 dB
c = 10
103
MEMORIA
Sistema de Control
Figura 5.20: diagrama de Black del lazo de corriente abierto, antes de aplicar
el control
C ( j 0 ) dB = 17.7 dB C ( j 0 ) = 10
c = 90 + arctg (Ti 0 ) = 10 Ti =
C ( j 0 ) = K
17.7
20
= 7.6736
tan 80
= 1.6 10 3
1 + (Ti 0 )
= 7.6736 K = 7.56
Ti 0
2
[5.15]
Donde:
m = margen de fase
Am = margen de ganancia
0 = pulsacin de cruce
u = pulsacin de oscilacin
104
MEMORIA
Sistema de Control
G ( j 0 ) dB = 17.8dB
c = 10
9.8
c = 90 + arctg (Ti 0 ) = 10 Ti =
C ( j 0 ) = K
1 + (Ti 0 )
Ti 0
tan 80
= 1.134 10 3 10 3
= 3.1 K = 3.05 3
[5.16]
105
MEMORIA
Sistema de Control
Figura 5.23: diagrama de Black del lazo completo abierto, antes de aplicar el
el control
Una vez observado el diagrama de Black del lazo completo abierto, se decide
disear el regulador que lo controle por margen de fase:
106
MEMORIA
Sistema de Control
G ( j 0 ) dB = 33.8 dB
c = 10
Una vez obtenidos los puntos caractersticos del sistema en lazo abierto, se
procede a disear el control:
C ( j 0 ) dB = 33.8 dB C ( j 0 ) = 10
c = 90 + arctg (Ti 0 ) = 10 Ti =
C ( j 0 ) = K
1 + (Ti 0 )
Ti 0
33.8
20
tan 80
= 48.978
= 1.89 10 2 2 10 2
= 78.978 K = 48.234 50
[5.17]
Figura 5.24: diagrama de Black del lazo completo abierto, despus de aplicar
diseo del control
Una vez implantado el control con los valores diseados, se simula el sistema
tomando como referencia dos escalones: el primero, de 0 a 0.5m/s, para estabilizar
el sistema en rgimen permanente, y el segundo de 0.1m/s de amplitud, para
107
MEMORIA
Sistema de Control
observar la reaccin del sistema ante pequeas variaciones, una vez est
estabilizado en rgimen permanente. Se obtiene como respuesta:
108
MEMORIA
Sistema de Control
1
1
es la frecuencia de corte..
, donde
1 + s
2
Ts
1 z 1
, quedando pues: F ( z ) =
. Por tanto, su ecuacin en
Ts
Ts + z 1
diferencias ser:
y[k ] =
Ts u[k ] + y[k 1]
Ts +
[5.18]
109
MEMORIA
Sistema de Control
110
MEMORIA
Sistema de Control
Si se hace = 1, se obtendr una frecuencia de corte de 0.16 Hz, la cual
satisface la premisa de eliminar las posibles fluctuaciones en altas frecuencias que
pudiera tener la corriente medida
G ( j 0 ) dB = 82 dB
c = 10
c = 90 + arctg (Ti 0 ) = 10 Ti =
C ( j 0 ) = K
1 + (Ti 0 )
Ti 0
tan 80
72
20
= 3981
= 3.38 10 3
= 3981 K = 3920.5
[5.19]
111
MEMORIA
Sistema de Control
Figura 5.29: diagrama de Black del lazo de corriente abierto, antes de aplicar
el control
Figura 5.30: diagrama de Black del lazo de corriente abierto, una vez
aplicado el control
112
MEMORIA
Sistema de Control
A la hora de disear el control del lazo completo, se tiene en cuenta el
siguiente diagrama de Black:
Figura 5.31: diagrama de Black del lazo completo abierto, antes de aplicar el
control
A partir de l, se decide que se va a disear por margen de fase. Se especifican
los clculos a continuacin:
m = 45
G ( j 0 ) = 180 +50 = 130 0 = 2.1rad / s
G ( j 0 ) dB = 3.87 dB
c = 5
C ( j 0 ) dB = 3.87dB C ( j 0 ) = 10
c = 90 + arctg (Ti 0 ) = 5 Ti =
C ( j 0 ) = K
1 + (Ti 0 )
Ti 0
3.87
20
= 0.65
tan 85
= 5 .4
= 0.65 K = 0.65
[5.20]
113
MEMORIA
Sistema de Control
Figura 5.30: diagrama de Black del lazo completo, con control aplicado
Sin embargo, se observa una respuesta del sistema ms lenta y fluctuante que
con controles anteriores:
114
MEMORIA
5.5.2. Filtro paso bajo FIR
Sistema de Control
Ante la mala respuesta del sistema con el filtro paso bajo de primer orden, se
decide disear un filtro FIR, que tiene la ventaja de ofrecer una gran atenuacin e
incluso completa eliminacin de determinadas frecuencias con una fase lineal,
para sustituir al filtro de primer orden, y observar si la respuesta del sistema
mejora.
Se define un filtro FIR como aquel en el que cada muestra de salida es una
suma ponderada de un nmero finito de muestras de la secuencia de entrada ya
recibida, lo que significa que su respuesta es causal. Esta funcionalidad se puede
expresar como:
Para obtener ms informacin sobre la teora que rodea a los filtros FIR
(aspecto en el cual no se va a ahondar ms en el presente texto) se puede consultar
cualquier libro de tratamiento de seales discretas, como por ejemplo los
enunciados en las referencias bibliogrficas 1, 2 y 3.
Los filtros FIR se disean en funcin de las frecuencias que se desean eliminar.
A partir de la transformada z del filtro, se hallan los ceros de la funcin. stos
sern complejos, que, en forma mdulo-argumental tendrn por mdulo la unidad,
y por argumento la pulsacin normalizada (pulsacin / pulsacin de muestreo) que
elimine ese cero. Si se disea dicha transformada para que tenga ceros en ciertas
frecuencias normalizadas (pulsacin normalizada / 2), que, multiplicadas por la
frecuencia de muestreo dan como resultado las frecuencias que se quieren
eliminar, stas resultarn eliminadas (se vuelve a hacer hincapi en que el presente
texto no pretende ahondar en los aspectos tericos de los filtros FIR y los
teoremas de muestreo. Se puede consultar las referencias bibliogrficas 1, 2 y 3
para ms informacin). Como se quiere disear un filtro paso bajo, se har de tal
115
MEMORIA
Sistema de Control
forma que elimine frecuencias equidistantes a partir de una pulsacin normalizada
de /2 hasta una pulsacin normalizada de 3/2.
Idealmente, se querran tener tantos ceros entre esas dos frecuencias como
fuese posible, para eliminar el mayor nmero posible de altas frecuencias, pero
cuantos ms ceros se introduzcan en la funcin, ms carga de trabajo tendr que
soportar el microprocesador, y ms altos (y, por consiguiente, difciles de escalar
en 8 bits, que es el tamao de los registros del microprocesador utilizado)
resultarn los coeficientes que acompaan a las z-n en la transformada z del
filtro, los cuales son los mismos coeficientes que acompaan a las x[n-k] en la
ecuacin en diferencias del filtro.
Se decidi que cinco ceros, en ej/2, ej3/4 y ej , conforman un filtro que
cumple las caractersticas necesarias para la funcin que ha de desempear en el
diseo. Una vez redondeados los coeficientes, para su posterior implantacin en el
microprocesador con enteros de 8 bits, queda la siguiente ecuacin en diferencias
del filtro:
y[n] =
2 z 6 + 7 z 5 + 12 z 4 + 14 z 3 + 12 z 2 + 7 z + 2
z6
[5.21]
116
MEMORIA
Sistema de Control
117
MEMORIA
Sistema de Control
Como en el filtro de primer orden, una vez diseado el filtro FIR, se procede a
disear el control mediante tcnicas de respuesta en frecuencia en lazo abierto.
Se comienza, como en anteriores diseos, por el diseo del regulador del lazo
de control de corriente:
3
Am = 8 dB G ( j 0 ) = 180 +10 = 190 0 = 4.24 10 rad / s
G ( j 0 ) dB = 16.8 dB
c = 10
c = 90 + arctg (Ti 0 ) = 10 Ti =
C ( j 0 ) = K
1 + (Ti 0 )
Ti 0
tan 80
24.8
20
= 0.058
= 1.34 10 3
= 0.058 K = 0.057
[5.22]
118
MEMORIA
Sistema de Control
Figura 5.35: diagrama de Black del lazo de corriente abierto, antes de aplicar
el control
119
MEMORIA
Sistema de Control
Despus de disear el regulador del lazo de control de corriente, se realiza el
diseo del regulador del lazo de control completo:
G ( j 0 ) dB = 33.6 dB
c = 10
C ( j 0 ) dB = 33.6dB C ( j 0 ) = 10
c = 90 + arctg (Ti 0 ) = 10 Ti =
C ( j 0 ) = K
1 + (Ti 0 )
Ti 0
33.6
20
= 0.02
tan 80
= 0.81
= 0.02 K = 0.02
[5.23]
Figura 5.37: diagrama de Black del lazo completo abierto, antes de aplicar el
control
120
MEMORIA
Sistema de Control
Figura 5.38: diagrama de Black del lazo completo abierto, una vez aplicado el
control
Una vez diseados los dos reguladores en tiempo continuo, se procede a
efectuar la simulacin de la respuesta del sistema en tiempo discreto ante un
escaln, dando como resultado la grfica de la figura 5.39.
121
MEMORIA
Sistema de Control
122
MEMORIA
Sistema de Control
El escalado se efecta multiplicando las variables del sistema que estn dentro
de los bloques de control por potencias de 2. Esto es as ya que para que el
microprocesador multiplique o divida por 2 nicamente tiene que hacer un
desplazamiento (shift left o shift right, respectivamente) al registro que contenga
el nmero a multiplicar, y dicha operacin de desplazamiento se efecta de forma
muy rpida. Mediante estas operaciones se consigue que las variables estn dentro
del rango de valores deseado, que en este caso es de -128 a 127 en el caso de 8
bits, de -32768 a 32767 en el caso de 16 bits, y de -2147483648 a 2147483647 en
el caso de 32 bits.
Se puede observar en las figuras 5.40, 5.41 y 5.42 los diferentes diagramas de
bloques del sistema escalado. Se representan tambin los diferentes tiempos de
muestreo del sistema mediante distintos colores, as como el tipo de dato de todas
las seales del sistema.
123
MEMORIA
Sistema de Control
Figura 5.40: sistema en coma flotante y sistema escalado, con los distintos tiempos de muestreo del sistema representados
124
MEMORIA
Sistema de Control
125
MEMORIA
Sistema de Control
126
MEMORIA
Sistema de Control
Figura 5.43: respuesta del sistema en coma flotante y del sistema escalado a
enteros de 8,16 y 32 bits ante un escaln de amplitud 0.1 m/s.
Existe en el ensayo realizado con las variables escaladas a enteros de 8 bits un
pequeo error en rgimen permanente, producido por dos causas: la primera de
ellas es el error que se introduce con la perdida de sensibilidad al realizar la
conversin A/D, en la cual, se pasa de valores continuos a valores discretos con
una sensibilidad igual al cociente entre el valor de tensin mximo de entrada al
conversor, y la n-sima potencia de dos, siendo n el nmero de bits del conversor
A/D; la segunda causa es la prdida de precisin al utilizar variables de 8 bits,
bien sea por la inexactitud de algunas operaciones (desprecio de decimales,
overflows, etc.), o por el escalado de las constantes a 8 bits, con la consiguiente
prdida de informacin debida al desprecio de cifras decimales. En el escalado a
constantes de 16 y 32 bits no se aprecia prcticamente diferencia con las variables
en coma flotante y doble precisin. Se elige pues trabajar con el escalado a 16
bits.
127
MEMORIA
Sistema de Control
5.7. Conclusiones
Se presenta en este captulo toda la informacin relativa al diseo del control
del sistema, desde los fundamentos tericos bsicos para comprender el
funcionamiento de los sistemas de control discreto y sus posibles mtodos de
diseo, hasta el programa que se implantar en el microprocesador para realizar el
control del sistema.
Una vez claro el regulador que se va a utilizar (el diseado por tcnicas de
respuesta en frecuencia, sin filtro de corriente), se procede con el escalado del
problema, para adecuar las variables del sistema para que puedan ser tratadas con
registros de 32, 16 u 8bits, en lugar de utilizar variables en doble precisin, que
disminuiran notablemente el rendimiento del microprocesador. Despus de haber
realizado el escalado con los tres tipos de variables, se elige trabajar con enteros
de 16 bits, ya que son la variable ms pequea que ofrece una calidad aceptable en
las simulaciones.
128
MEMORIA
Implantacin
129
MEMORIA
Implantacin
130
MEMORIA
Implantacin
131
MEMORIA
Implantacin
132
MEMORIA
Implantacin
133
MEMORIA
Implantacin
4. El control del micro disminuye duty cycle del PWM para igualar velocidad a
la referencia, y a partir de ah, empieza a gestionar la referencia de velocidad
134
MEMORIA
Implantacin
en funcin de la aceleracin normal que se mida en cada instante, pasando de
nuevo al punto 1.
Adems,
se
han
creado
los
archivos
.h
control.h,
configuracin.h y constantes.h.
135
MEMORIA
Implantacin
MDULO
FUNCIN
Main.c
Main
InitM5282Lite_ES
Configuracin
.c
TAREA
Inicializacin, creacin de tareas y arranque
del planificador.
Inicializacin
InitPWM
Inicializacin PWM.
SetPWM
InitControl
Inicializacin.
ADCTask
(TAREA)
A/D.
Tarea que realiza las gestiones para modificar
Control (TAREA)
CopiaRef
CopiaEnRef
Control.c
PI1 y PI2
QadcInit
LeeAN0, 1, 2 y 3
IntGPTA0
Interrupts
(en Control.c)
IntPIT0
136
MEMORIA
6.2.1. Main
Implantacin
137
MEMORIA
6.2.2. Control
Implantacin
La tarea de control se ejecuta cada 20 ms, y realiza los clculos necesarios para
la gestin de la referencia de velocidad del tren, en funcin de la aceleracin
normal medida. La figura 6.5 muestra su diagrama de flujo.
138
MEMORIA
6.2.3. ADCTask
Implantacin
139
MEMORIA
Implantacin
6.2.4. IntGPTA0
IntGPTA0 es la interrupcin que salta cuando hay un flanco de subida en el pin
GPTA0, que es el asociado a detectar los pasos por las balizas del tren. Su
funcionamiento viene descrito por su diagrama de flujo, que se puede observar en
la figura 6.7.
MEMORIA
La figura 6.8 presenta su diagrama de bloques:
Implantacin
141
MEMORIA
6.2.6. Programacin del regulador PI discreto
Implantacin
[5.24]
Donde:
[5.25]
1
m[k ] = K e[k ] + Ie[k ]
Ti
[5.26]
Y el mando en un instante k:
m[k ] = m[k ] + m[k 1]
[5.27]
142
MEMORIA
Implantacin
Luego, si se programa una subrutina llamada PI que efecte el control
proporcional-integral a partir de las mediciones pertinentes y de la referencia,
quedar algo como:
e_act = referencia-salida;
Ie_act = *pIe_ant + (e_act + *pe_ant) * Ts/2;
inc_mando
(e_act-(*pe_ant)
((Ie_act-
(*pIe_ant))/Ti) );
mando= *pmando_ant+inc_mando;
if(mando>=man_sat){
mando=man_sat;
}else if(mando<=(-man_sat)){
mando=-man_sat;
}
*pmando_ant = mando_act
*pe_ant = e_act;
*pIe_ant = Ie_act;
return (mando);
}
Si se observa de nuevo el diagrama de flujo del sistema entero (figura 6.9), se
ve con claridad que todas las tareas que deba realizar el microprocesador han sido
implementadas
con
xito.
143
MEMORIA
Implantacin
144
MEMORIA
Implantacin
6.3. Conclusiones
El presente captulo comienza con una recopilacin de datos tiles sobre el
microprocesador Motorola ColdFire MCF5282, tales como sus caractersticas
elctricas y mecnicas, o aquellas de sus funcionalidades que van a ser tiles en el
proyecto.
145
MEMORIA
Resultados
146
MEMORIA
Resultados
147
MEMORIA
Resultados
148
MEMORIA
Resultados
149
MEMORIA
Conclusiones
MEMORIA
Conclusiones
efecte con la mayor precisin y sensibilidad posibles, y sin perturbar a la seal
original. Para ello se han utilizado bsicamente etapas basadas en amplificadores
operacionales, tanto en realimentacin negativa como en bucle abierto, diodos
zener para la proteccin del microprocesador, y los propios elementos cuya seal
se haba de acondicionar.
La ltima etapa de diseo es la relativa al diseo del control del sistema. Se han
presentado pues en el captulo quinto, desde los fundamentos tericos bsicos para
comprender el funcionamiento de los sistemas de control discreto y sus posibles
mtodos de diseo, hasta el programa que se ha implantado en el microprocesador
para realizar el control del sistema.
Una vez claro el regulador que se va a utilizar (el diseado por tcnicas de
respuesta en frecuencia, sin filtro de corriente), se ha procedido con el escalado
del problema, para adecuar las variables del sistema para que puedan ser tratadas
con variables enteras de 8, 16 32 bits (lo cual supondr una mejora del
rendimiento del microprocesador, al no tener que trabajar con variables en coma
flotante de doble precisin, tal y como se trabaja en las simulaciones). Despus de
realizar el escalado pertinente en variables enteras de 8, 16 y 32 bits, y de realizar
la simulaciones necesarias para comprobar la efectividad del mismo, se determina
151
MEMORIA
Conclusiones
que el tipo de variable ms conveniente para realizar el escalado son los enteros
de 16 bits.
Cabe destacar que, a medida que se fueron realizando los diversos avances en
el diseo, stos se fueron acompaando de la documentacin necesaria para la
elaboracin de la presente memoria. Adems, tambin se fueron diseando las
placas de circuito impreso necesarias para construir el sistema de forma definitiva,
y no como un prototipo, las cuales se pueden encontrar en la seccin de planos, a
continuacin de la presente memoria. Para este fin se utilizaron los programas
OrCAD Capture y OrCAD LayOut.
MEMORIA
Conclusiones
pulsos elctricos transmitidos por medio de las vas del tren, y en el presente
proyecto se utiliza una seal PWM que se transmite tambin por las mismas vas
para llegar al motor del tren, sera complicado distinguir entre los pulsos de la
seal de comunicacin y los pulsos generados por el ruido de la onda PWM, o la
propia onda PWM. ste problema se podra solucionar por medio de filtrado, pues
la frecuencia de la onda PWM es conocida, y la frecuencia de las ondas de pulsos
de comunicacin tambin lo sera, el problema radica en que el ruido generado
por el PWM podra distorsionar distintas frecuencias, incluida aqulla en la que se
transmite la onda de pulsos de comunicacin.
153
MEMORIA
Agradecimientos
Agradecimientos
Una vez terminado el proyecto, slo queda mirar atrs con una expresin de
satisfaccin en el rostro, y agradecer a todas esas personas que han hecho
posible la realizacin del mismo:
En primer lugar, he de darles las gracias a mis padres, por toda la paciencia
que a lo largo de todos estos aos han tenido conmigo, y porque sin su ayuda y
apoyo, nada habra sido posible.
Por ltimo, y aunque prcticamente no han tenido nada que ver de una forma
directa con este proyecto, por ser ste el punto final de mis cincos ltimos aos de
estudios, me gustara mencionar a D. Flix Alonso y a D. Santiago Canales, por
haberme sabido inculcar all en primer curso valores tan importantes como el
trabajo y el esfuerzo.
154
MEMORIA
Bibliografa
Bibliografa
1. [MCCL98] MCCLELLAN, SCHAFER, YODER. DSP First.Ed. Prentice
Hall, 1998.
2. [OPPE00] OPPENHEIM, SCHAFER, BUCK. Discrete-Time Signal
Processing Ed. Prentice-Hall., 2000.
3. [VIJA02] VIJAY K. MADISETTI, DOUGLAS B. WILLIAMS. Digital
Signal Processing Handbook. Ed. Chapman & Hall, 2002.
4. [SEDR98] SEDRA / SMITH.Microelectronic Circuits Ed. Oxford UP, 1998
5. [COUG01] COUGHLIN/ DRISCOLL. Operational Amplifiers and Linear
InegratedCircuits Ed. Prentice Hall, 2001
6. [BORE02] BORELLI, R. Y COURTNEY, S. Ecuaciones diferenciales.
Una perspectiva de modelacin. Ed. Oxford University Press, 2002
7. [MARC90] MARCELLN, F.-CASASUS, L.-ZARZO, A. Ecuaciones
diferenciales Ed. McGraw-Hill, 1990
8. [GARC06] GARCA, A.-GARCA, F.- LPEZ, A.- RODRGUEZ, G.ROMERO, S.- VILLA, A de la. Ecuaciones diferenciales ordinarias.
Teora y problemas. Mtodos exactos. Mtodos numricos. Estudio
cualitativo Ed. CLAGSA, 2006
9. [PAGO06] PAGOLA, LUIS. Regulacin Automtica Ed. Universidad
Pontificia Comillas, 2006
10. [NISE04] NISE. Control Systems Engineering Ed. Wiley, 2004
11. [MUO09] MUOZ FRAS, JOS DANIEL. Sistemas Empotrados en
Tiempo Real Creative Commons. Febrero 2009
155
MEMORIA
Bibliografa
http://www.cooperativa.cl/p4_noticias/site/artic/20060208/pags/20060208
200104.html
http://www.lukor.com/not-soc/sucesos/0902/27143852.htm
http://www.elcomerciodigital.com/gijon/20090225/asturias/maquinistatren-descarrilado-parres-20090225.html
http://www.tribuna.net/noticia/27502/CASTILLA-Y-LEN/seis-muertosheridos-descarrilar-tren-palencia.html
http://infotobarra.en.eresmas.com/descarrilamiento.htm
http://edant.clarin.com/diario/2005/04/26/elmundo/i-02401.htm
http://www.cadenaser.com/espana/articulo/muertos-descarrilar-trenprovincia-palencia/sernotnac/20060821csrcsrnac_10/Tes
http://xeneize.wordpress.com/2007/07/11/fuerzas-g-por-albert-illera/
CONTROL DE TRENES:
http://www.elmundo.es/papel/2006/07/05/espana/1992349.html
http://www.madrid.org/metrosur/instalaciones/senalizacion.htm
http://ferrocarriles.wikia.com/wiki/Sistemas_de_control_de_trenes
CONTROL DE MOTORES:
http://webdelprofesor.ula.ve/ingenieria/gjaime/materias/control_de_motor
es/semA2004/clase1.pdf
SISTEMAS DE CONTROL:
http://isa.uniovi.es/~cuadrado/dsac.html
http://www.seattlerobotics.org/encoder/200205/PIDmc.html
156
MEMORIA
Anexos
Anexos
Anexo1. Programa completo en lenguaje C
- Anexo 1.1. Main.c
- Anexo 1.2. Control.c
- Anexo 1.3. Control.h
- Anexo 1.4. Configuracion.c
- Anexo 1.5. Configuracion.h
- Anexo 1.6. Constantes.h
Anexo 2. Archivos .m utilizados en MATLAB
Anexo 3. Manual del microprocesador
- Anexo 3.1. Captulo 10: Interrupt Controller Modules
- Anexo 3.2. Captulo19: Programmable Interrupt Timer Modules
(PIT0-PIT3)
- Anexo 3.3. Captulo 20: General Purpose Timer Modules (GPTA and
GPTB)
- Anexo 3.4. Captulo 28: Queued Analog-to-Digital Converter (QADC)
- Anexo 3.5.Captulo 33: Caractersticas Elctricas
Anexo 4. NMRA Electrical Standards for Digital Command Control, July
2004.
Anexo 5. NMRA Communications Standards for Digital Command
Control, July 2004.
Anexo 6. Hojas de caractersticas (Datasheets)
157
ANEXO 1
MEMORIA
/*Main.c
* Autor: Fernando Moreno
* ltima modificacin: 6/Jun/2010
*/
Anexo I
#include "Constantes.h"
int main()
{
InitM5282Lite_ES();
//Inicializa
los
perifericos del M5282
InitPWM();
//Inicializa el PWM con una
resolucin de PWM_RESOLUTION unidades.
QadcInit();
//Inicializa el
conversor AD
InitControl();
//Inicializa
registros
y
variables utilizadas por el control
//Creacin de tareas
xTaskCreate(Control,(const
signed
portCHAR
const)"Control",TAM_PILA,NULL,PRIO_CONTROL,NULL);
xTaskCreate(ADCTask,(const
signed
portCHAR
const)"ADCTask",TAM_PILA,NULL,PRIO_ADCTASK,NULL);
*
*
vTaskStartScheduler();
(scheduler)
}
//Arranca
el
planificador
MEMORIA
/*Control.c
* Autor: Fernando Moreno
* ltima modificacin: 6/Jun/2010
*/
Anexo I
#include Control.h
MEMORIA
Anexo I
MEMORIA
ref_vel = ref_vel - INC_REF;
}
CopiaEnRef(ref_vel);
}
}
Anexo I
MEMORIA
Anexo I
Ie_act = *pIe_ant + (e_act + *pe_ant) * 3;
inc_mando = 3 * (((e_act-(*pe_ant))*16) + (((Ie_act(*pIe_ant))*3)/4)) * 3;
mando= *pmando_ant+inc_mando;
if(mando>=man_sat){
mando=man_sat;
}else if(mando<=(-man_sat)){
mando=-man_sat;
}
*pmando_ant = mando;
*pe_ant = e_act;
*pIe_ant = Ie_act;
return (mando);
}
int PI2(int referencia,int salida, int man_sat, int*
pe_ant, int* pIe_ant, int* pmando_ant)
{
int e_act, Ie_act;
int inc_mando, mando;
e_act = referencia - salida;
Ie_act = *pIe_ant + (e_act + *pe_ant);
inc_mando = ((3 * ((e_act-(*pe_ant) + ((Ie_act(*pIe_ant)))))) / 13) * 2;
mando= *pmando_ant+inc_mando;
if(mando>=man_sat){
mando=man_sat;
}else if(mando<=(-man_sat)){
mando=-man_sat;
}
*pmando_ant = mando;
*pe_ant = e_act;
*pIe_ant = Ie_act;
return (mando);
}
/* Funciones para el manejo del Conversor A/D.
*
* El conversor A/D es bastante complejo. Dispone de
dos colas en las
MEMORIA
Anexo I
* que se pueden programar la realizacin de una serie
de conversiones
* automticas de una serie de canales, de forma que se
interrumpa al
* micro (o se active el bit de final de conversin si
usamos
* encuesta) cuando finalice la secuencia de
conversiones.
*
* En esta librera simple se usa una sola cola para
convertir los
* canales 0, 1, 2 y 3 (entradas AN0, AN1, AN2 y AN3).
La conversin se dispara por
* software escribiendo un 1 en el bit SSE (Single Scan
Enable) de la
* cola 1 (SSE1), que est en el registro QACR1. De
esto se encarga la
* funcin ArrancaConversion(). Por ltimo, el bit 15
del registro de
* estado de la cola QASR0 se pone a 1 cuando finaliza
la secuencia de
* conversiones. La funcin Convirtiendo() comprueba
este bit y
* devuelve un 1 si la conversin an est en marcha o
un cero si ha
* terminado.
*/
void QadcInit(void)
{
MCF_QADC_QADCMCR = 0; /* Arranca el mdulo del
conversor AD. Accesible
en modo usuario */
MCF_QADC_DDRQA = 0; /* los pines se definen como
entrada pues si por algo
estn configurados como
*/
MCF_QADC_DDRQB = 0; /* salida digital el conversor no
funcionar */
MCF_QADC_QACR0 = 7; /* Mux interno, divisin del
reloj por 16 para generar
ADCclk de 4 MHz
(suponiendo que el
micro funciona a 64 MHz
*/
MCF_QADC_QACR1 = 0x0100; /* Sin interrupciones,
disparado por software,
single scan*/
MEMORIA
Anexo I
MCF_QADC_QACR2 = 0x7f; /* No se usa la cola 2. BQ2 =
7f (>64) para
indicarlo) */
MCF_QADC_CCW(0) = 0; /* Primera conversin: AN0 */
MCF_QADC_CCW(1) = 1; /* Segunda conversin: AN1 */
MCF_QADC_CCW(2) = 2; /* Tercera conversin: AN2 */
MCF_QADC_CCW(3) = 3; /* Cuarta conversin: AN3 */
MCF_QADC_CCW(4) = 63; /* Fin de la cola */
vSemaphoreCreateBinary(sem_AD); //Crea el semforo
}
void ArrancaConversion(void)
{
MCF_QADC_QACR1 = 0x2100; /* Sin interrupciones,
disparado por software,
single scan. SSE =
1 para disparar la cola 1*/
}
int Convirtiendo()
{
if((MCF_QADC_QASR0&0x8000) == 0){
return 1; /* Est convirtiendo an */
}else{
return 0;
}
}
uint16 LeeAN0(void)
{
return MCF_QADC_RJURR(0);
}
uint16 LeeAN1(void)
{
return MCF_QADC_RJURR(1);
}
uint16 LeeAN2(void)
{
return MCF_QADC_RJURR(2);
}
uint16 LeeAN3(void)
{
return MCF_QADC_RJURR(3);
}
MEMORIA
__declspec(interrupt) IntGPTA0(void)
//Interrupcin: Deteccin baliza
{
MCF_GPTA_GPTFLG1|=(0x1<<0);//Baja el flag
Anexo I
MEMORIA
/*Control.h
* Autor: Fernando Moreno
* ltima modificacin: 1/Jun/2010
*/
Anexo I
#ifndef Control_h
#define Control_h
#include "Constantes.h"
/* Funcin: InitControl
*
* Inicializa las interrupciones en el puerto GPTA,
para
* que salte una interrupcin con la deteccin de una
baliza.
* y configura el PIT0 y el GPIO.
* Versin: 0.0
*/
void InitControl(void);
/* Funcin: ADCTask
*
* Tarea que realiza las conversiones A/D,
* controlada por el planificador.
*
* Versin: 0.0
*/
void ADCTask(void *pvParameters)
/* Funcin: Control
*
* Tarea que realiza el control de la referencia de
velocidad cada 20ms
*
* Versin: 0.0
*/
void Control(void *pvParameters);
/* Funcin: CopiaRef
*
* Copia la referencia de velocidad
*
* Versin: 0.0
*/
uint16 CopiaRef(void);
/* Funcin: CopiaEnRef
*
MEMORIA
Anexo I
* Copia la referencia de velocidad calculada en la
tarea de Control.
*
* Versin: 0.0
*/
uint16 CopiaEnRef(void);
/* Funcin: PI1
*
* Realiza un control PI incremental en tiempo discreto
a partir
* de los parmetros de entrada
*
* Versin: 0.0
*/
int PI1(int referencia,int salida, int* pe_ant, int*
pIe_ant, int K, int Ti);
/* Funcin: PI2
*
* Realiza un control PI incremental en tiempo discreto
a partir
* de los parmetros de entrada
*
* Versin: 0.0
*/
int PI2(int referencia,int salida, int* pe_ant, int*
pIe_ant, int K, int Ti);
/*Funciones para el manejo del conversor AD*/
/* Funcin: QadcInit
*
* Inicializa en conversor AD para medir las entradas
AN0, AN1, AN2 y AN3. El final de
* la conversin se realizar por encuesta mediante la
funcin Convirtiendo().
*
* Versin: 0.0
*/
void QadcInit(void);
/* Funcin: ArrancaConversion
*
* Arranca una conversin. Se convertirn los canales
* AN0, AN1, AN2 y AN3.
*
* Versin: 0.0
*/
MEMORIA
void ArrancaConversion(void);
Anexo I
/* Funcin: Convirtiendo
*
* Consulta el registro de estado del conversor A/D y
devuelve un 1 si se est
* realizando la conversin o un cero si sta ha
terminado.
*
* Versin: 0.0
*/
int Convirtiendo();
/* Funcin: LeeAN0
*
* Devuelve el resultado de la conversin A/D del canal
AN0
* El valor es de 10 bits, de forma que 0V se traducen
en el valor 0 y 3.3 V
* en 1023. Los bits 10 a 15 estarn siempre a 0.
*
* Versin: 0.0
*/
uint16 LeeAN0(void);
/* Funcin: LeeAN1
*
* Idem LeeAN0 pero para el canal AN1
*
* Versin: 0.0
*/
uint16 LeeAN1(void);
/* Funcin: LeeAN2
*
* Idem LeeAN0 pero para el canal AN2
*
* Versin: 0.0
*/
uint16 LeeAN2(void);
/* Funcin: LeeAN3
*
* Idem LeeAN0 pero para el canal AN3
*
* Versin: 0.0
*/
uint16 LeeAN3(void);
MEMORIA
/*Interrupciones*/
Anexo I
/* Interrupcin: IntGPTA0
*
* Interrupcin de deteccin de baliza
*
* Versin: 0.0
*/
__declspec(interrupt) IntGPTA0(void)
/* Interrupcin: IntPIT0
*
* Interrupcin para realizar el control cada tiempo de
muestreo.
*
* Versin: 0.0
*/
__declspec(interrupt) IntPIT0(void)
#endif
MEMORIA
Anexo I
/* Funciones para el manejo del conversor AD y el PWM
*/
#include "Configuracion.h"
/*Puerto salida PWM*/
MEMORIA
Anexo I
sim.gpt[GPT_NUM].ddr=0x0F; /* Set all four channel pins
as outputs. */
sim.gpt[GPT_NUM].scr1=0x90; /* Enable the timer */
}
MEMORIA
Anexo I
/* Funciones para el manejo del conversor A/D y el
* modulador de ancho de pulso.
*
* Autor: Modificado: Fernando Moreno Prez
*
* Versin: 0.1
*/
#ifndef Configuracion_h
#define Configuracion_h
#include "Constantes.h"
/* Funcin: InitM5282Lite_ES
*
* Inicializa el generador de Chip Select del ColdFire
para direccionar la
* CPLD de la tarjeta M5282Lite-ES.
* Es necesario llamar a esta funcin antes de usar los
interruptores/LEDS
* o el teclado.
*
* Versin: 0.0
*/
void InitM5282Lite_ES(void);
/* Funciones para el manejo del generador PWM*/
/* Funcin: InitPWM
*
* Inicializa la seal PWM en el pin GPTA0 del
microprocesador, con
*un DUTY_CYCLE del 50%, y una resolucin igual al
parmetro
*definido como PWM_RESOLUTION (ha de ser 1000 para que
la
*frecuencia del PWM sea de 32kHz).
*
* Versin: 0.0
*/
void InitPWM(void)
/* Funcin: SetPWM
*
* Cambia el valor de comparacin del PWM por el
* valor del parmetro p0.
*
* Versin: 0.0
*/
void SetPWM(int p0)
MEMORIA
#endif
Anexo I
MEMORIA
/*Constantes.h
* Autor: Fernando Moreno
* ltima modificacin: 6/Jun/2010
*/
//Archivo .h que engloba todos
includes utilizados.
Anexo I
los
defines
los
#ifndef CONSTANTES_H
#define CONSTANTES_H
#include "mcf5282.h"
#include "M5282Lite-ES.h"
//Includes del kernel
#include
#include
#include
#include
#include
"FreeRTOS.h"
"semphr.h"
"task.h"
"queue.h"
"semphr.h"
//defines
#define
bits
#define
#define
#define
#define
#define
SAT
SAT_AD
MAN_SAT1
MAN_SAT2
MEDIR_VEL
INC_REF
32768
//16
->
8 //Para que el
ANEXO 2
Inicializacion_PWM_con_filtro.m
%Inicializacion Parametros Proyecto Control de Velocidad por
Microprocesador
s=tf('s');
% ----- SIN SIMULACION ----- %
%PARAMETROS NUMERICOS
Ke=5.8347;
Km=5.8347;
Kpot=14/3;
Ks=1;
Ki=1;
R=35;
%[ohm]
L=5.6662e-5 * R
%[H]
M=0.7;
%[kg]
D=0.6703;
tiempo_muestreo=550e-6; %dado por el micro
ts=tiempo_muestreo;
%PARAMETROS DE CONTROL
%PI1
K_pi1 = 0.65;
Ti_pi1 = 5.4;
b_pi1 = 1;
ts_pi1 = 10*tiempo_muestreo; %0.5e-3;
sat_sup_man_pi1 = 0.4; %0.4;
sat_inf_man_pi1 = -0.4; %-0.4;
%PI2
K_pi2 = 3920.5;
%OK
Ti_pi2 = 3.38e-3;
%OK
b_pi2 = 1;
%OK
ts_pi2 = tiempo_muestreo;
sat_sup_man_pi2 = 3; %1;
sat_inf_man_pi2 = -3; %-1;
OK=1
Page 1
ANEXO 3
Chapter 10
Interrupt Controller Modules
This section details the functionality for the MCF5282 interrupt controllers (INTC0, INTC1). The general
features of each of the interrupt controller include:
63 interrupt sources, organized as:
56 fully-programmable interrupt sources
7 fixed-level interrupt sources
Each of the 63 sources has a unique interrupt control register (ICRnx) to define the
software-assigned levels and priorities within the level
Unique vector number for each interrupt source
Ability to mask any individual interrupt source, plus global mask-all capability
Supports both hardware and software interrupt acknowledge cycles
Wake-up signal from low-power stop modes
The 56 fully-programmable and seven fixed-level interrupt sources for each of the two interrupt controllers
on the MCF5282 handle the complete set of interrupt sources from all of the modules on the device. This
section describes how the interrupt sources are mapped to the interrupt controller logic and how interrupts
are serviced.
10.1
Before continuing with the specifics of the MCF5282 interrupt controllers, a brief review of the interrupt
architecture of the 68K/ColdFire family is appropriate.
The interrupt architecture of ColdFire is exactly the same as the M68000 family, where there is a 3-bit
encoded interrupt priority level sent from the interrupt controller to the core, providing 7 levels of interrupt
requests. Level 7 represents the highest priority interrupt level, while level 1 is the lowest priority. The
processor samples for active interrupt requests once per instruction by comparing the encoded priority
level against a 3-bit interrupt mask value (I) contained in bits 10:8 of the machines status register (SR). If
the priority level is greater than the SR[I] field at the sample point, the processor suspends normal
instruction execution and initiates interrupt exception processing. Level 7 interrupts are treated as
non-maskable and edge-sensitive within the processor, while levels 1-6 are treated as level-sensitive and
may be masked depending on the value of the SR[I] field. For correct operation, the ColdFire requires that,
once asserted, the interrupt source remain asserted until explicitly disabled by the interrupt service routine.
During the interrupt exception processing, the CPU enters supervisor mode, disables trace mode and then
fetches an 8-bit vector from the interrupt controller. This byte-sized operand fetch is known as the interrupt
acknowledge (IACK) cycle with the ColdFire implementation using a special encoding of the transfer type
and transfer modifier attributes to distinguish this data fetch from a normal memory access. The fetched
data provides an index into the exception vector table which contains 256 addresses, each pointing to the
beginning of a specific exception service routine. In particular, vectors 64 - 255 of the exception vector
table are reserved for user interrupt service routines. The first 64 exception vectors are reserved for the
processor to handle reset, error conditions (access, address), arithmetic faults, system calls, etc. Once the
interrupt vector number has been retrieved, the processor continues by creating a stack frame in memory.
For ColdFire, all exception stack frames are 2 longwords in length, and contain 32 bits of vector and status
register data, along with the 32-bit program counter value of the instruction that was interrupted (see
Section 2.6, Exception Stack Frame Definition for more information on the stack frame format). After
the exception stack frame is stored in memory, the processor accesses the 32-bit pointer from the exception
vector table using the vector number as the offset, and then jumps to that address to begin execution of the
MCF5282 Coldfire Microcontroller Users Manual, Rev. 2.3
Freescale Semiconductor
10-1
service routine. After the status register is stored in the exception stack frame, the SR[I] mask field is set
to the level of the interrupt being acknowledged, effectively masking that level and all lower values while
in the service routine. For many peripheral devices, the processing of the IACK cycle directly negates the
interrupt request, while other devices require that request to be explicitly negated during the processing of
the service routine.
For the MCF5282, the processing of the interrupt acknowledge cycle is fundamentally different than
previous 68K/ColdFire cores. In the new approach, all IACK cycles are directly handled by the interrupt
controller, so the requesting peripheral device is not accessed during the IACK. As a result, the interrupt
request must be explicitly cleared in the peripheral during the interrupt service routine. For more
information, see Section 10.1.1.3, Interrupt Vector Determination.
Unlike the M68000 family, all ColdFire processors guarantee that the first instruction of the service routine
is executed before sampling for interrupts is resumed. By making this initial instruction a load of the SR,
interrupts can be safely disabled, if required.
During the execution of the service routine, the appropriate actions must be performed on the peripheral
to negate the interrupt request.
For more information on exception processing, see the ColdFire Programmers Reference Manual at
http://www.freescale.com/coldfire.
10.1.1
To support the interrupt architecture of the 68K/ColdFire programming model, the combined 63 interrupt
sources are organized as 7 levels, with each level supporting up to 9 prioritized requests. Consider the
priority structure within a single interrupt level (from highest to lowest priority) as shown in Table 10-1.
Table 10-1. Interrupt Priority Within a Level
ICR[2:0]
Priority
Interrupt
Sources
111
7 (Highest)
8-63
110
8-63
101
8-63
100
8-63
1-7
011
8-63
010
8-63
001
8-63
000
0 (Lowest)
8-63
The level and priority is fully programmable for all sources except interrupt sources 17. Interrupt source
17 (from the Edgeport module) are fixed at the corresponding levels midpoint priority. Thus, a maximum
of 8 fully-programmable interrupt sources are mapped into a single interrupt level. The fixed interrupt
source is hardwired to the given level, and represents the mid-point of the priority within the level. For the
fully-programmable interrupt sources, the 3-bit level and the 3-bit priority within the level are defined in
the 8-bit interrupt control register (ICRnx).
The operation of the interrupt controller can be broadly partitioned into three activities:
MCF5282 Coldfire Microcontroller Users Manual, Rev. 2.3
10-2
Freescale Semiconductor
Recognition
Prioritization
Vector Determination during IACK
10.1.1.1
Interrupt Recognition
The interrupt controller continuously examines the request sources and the interrupt mask register to
determine if there are active requests. This is the recognition phase.
10.1.1.2
Interrupt Prioritization
As an active request is detected, it is translated into the programmed interrupt level, and the resulting 7-bit
decoded priority level (IRQ[7:1]) is driven out of the interrupt controller. The decoded priority levels from
all the interrupt controllers are logically summed together and the highest enabled interrupt request is then
encoded into a 3-bit priority level that is sent to the processor core during this prioritization phase.
10.1.1.3
Once the core has sampled for pending interrupts and begun interrupt exception processing, it generates
an interrupt acknowledge cycle (IACK). The IACK transfer is treated as a memory-mapped byte read by
the processor, and routed to the appropriate interrupt controller. Next, the interrupt controller extracts the
level being acknowledged from address bits[4:2], and then determines the highest priority interrupt request
active for that level, and returns the 8-bit interrupt vector for that request to complete the cycle. The 8-bit
interrupt vector is formed using the following algorithm:
For INTC0,
For INTC1,
Recall vector_numbers 0 - 63 are reserved for the ColdFire processor and its internal exceptions. Thus, the
following mapping of bit positions to vector numbers applies for the INTC0:
if interrupt source 1 is active and acknowledged,
then vector_number =
65
then vector_number =
66
then vector_number =
72
then vector_number =
73
...
...
if interrupt source 62 is active and acknowledged,
The net effect is a fixed mapping between the bit position within the source to the actual interrupt vector
number.
If there is no active interrupt source for the given level, a special spurious interrupt vector
(vector_number = 24) is returned and it is the responsibility of the service routine to handle this error
situation.
Note this protocol implies the interrupting peripheral is not accessed during the acknowledge cycle since
the interrupt controller completely services the acknowledge. This means the interrupt source must be
explicitly disabled in the interrupt service routine. This design provides unique vector capability for all
interrupt requests, regardless of the complexity of the peripheral device.
MCF5282 Coldfire Microcontroller Users Manual, Rev. 2.3
Freescale Semiconductor
10-3
10.2
Memory Map
The register programming model for the interrupt controllers is memory-mapped to a 256-byte space. In
the following discussion, there are a number of program-visible registers greater than 32 bits in size. For
these control fields, the physical register is partitioned into two 32-bit values: a register high (the upper
longword) and a register low (the lower longword). The nomenclature <reg_name>H and <reg_name>L
is used to reference these values.
The registers and their locations are defined in Table 10-3. The offsets listed start from the base address
for each interrupt controller. The base addresses for the interrupt controllers are listed below:
Table 10-2. Interrupt Controller Base Addresses
Interrupt Controller Number
Base Address
INTC0
IPSBAR + 0xC00
INTC1
Global IACK Registers
1
IPSBAR + 0xD00
Space1
IPSBAR + 0xF00
This address space only contains the SWIACK and L1ACK-L7IACK registers. See Section 10.3.7, Software
and Level n IACK Registers (SWIACKR, L1IACKL7IACK)" for more information
Bits[31:24]
Bits[23:16]
Bits[15:8]
Bits[7:0]
0x00
0x04
0x08
0x0c
0x10
0x14
0x18
IRLR[7:1]
IACKLPR[7:0]
0x1c - 0x3c
Reserved
Reserved
0x40
Reserved
ICR01
ICR02
ICR03
0x44
ICR04
ICR05
ICR06
ICR07
0x48
ICR08
ICR09
ICR10
ICR11
0x4c
ICR12
ICR13
ICR14
ICR15
0x50
ICR16
ICR17
ICR18
ICR19
0x54
ICR20
ICR21
ICR22
ICR23
0x58
ICR24
ICR25
ICR26
ICR27
0x5C
ICR28
ICR29
ICR30
ICR31
0x60
ICR32
ICR33
ICR34
ICR35
Freescale Semiconductor
Register Descriptions
Bits[31:24]
Bits[23:16]
Bits[15:8]
Bits[7:0]
0x64
ICR36
ICR37
ICR38
ICR39
0x68
ICR40
ICR41
ICR42
ICR43
0x6C
ICR44
ICR45
ICR46
ICR47
0x70
ICR48
ICR49
ICR50
ICR51
0x74
ICR52
ICR53
ICR54
ICR55
0x78
ICR56
ICR57
ICR58
ICR59
0x7C
ICR60
ICR61
ICR62
ICR63
0x80-0xDC
10.3
10.3.1
Reserved
0xE0
SWIACK
Reserved
0xE4
L1IACK
Reserved
0xE8
L2IACK
Reserved
0xEC
L3IACK
Reserved
0xF0
L4IACK
Reserved
0xF4
L5IACK
Reserved
0xF8
L6IACK
Reserved
0xFC
L7IACK
Reserved
Register Descriptions
Interrupt Pending Registers (IPRHn, IPRLn)
The IPRHn and IPRLn registers, Figure 10-1 and Figure 10-2, are each 32 bits in size, and provide a bit
map for each interrupt request to indicate if there is an active request (1 = active request, 0 = no request)
for the given source. The state of the interrupt mask register does not affect the IPRn. The IPRn is cleared
by reset. The IPRn is a read-only register, so any attempted write to this register is ignored. Bit 0 is not
implemented and reads as a zero.
10-5
Chapter 19
Programmable Interrupt Timer Modules (PIT0PIT3)
19.1
Overview
The programmable interrupt timer (PIT) is a 16-bit timer that provides precise interrupts at regular
intervals with minimal processor intervention. The timer can either count down from the value written in
the modulus register, or it can be a free-running down-counter. This device has four programmable
interrupt timers, PIT0PIT3.
19.2
Block Diagram
IPBUS
System
Clock
Divide
by 2
16-bit PCNTR
Prescaler
COUNT = 0
PIF
Load
Counter
EN
PRE[3:0]
To Interrupt
Controller
PIE
OVW
RLD
DOZE
HALTED
16-bit PMR
IPBUS
19-1
19.3
This subsection describes the operation of the PIT modules in low-power modes and halted mode of
operation. Low-power modes are described in the Power Management Module. Table 19-1 shows the PIT
module operation in low-power modes, and how it can exit from each mode.
NOTE
The low-power interrupt control register (LPICR) in the System Control
Module specifies the interrupt level at or above which the device can be
brought out of a low-power mode.
Table 19-1. PIT Module Operation in Low-power Modes
Low-power Mode
PIT Operation
Mode Exit
Wait
Doze
Stop
Stopped
Halted
No
No. Any IRQx Interrupt will be serviced upon
normal exit from halted mode
In wait mode, the PIT module continues to operate as in run mode and can be configured to exit the
low-power mode by generating an interrupt request. In doze mode with the PCSR[DOZE] bit set, PIT
module operation stops. In doze mode with the PCSR[DOZE] bit cleared, doze mode does not affect PIT
operation. When doze mode is exited, the PIT continues to operate in the state it was in prior to doze mode.
In stop mode, the system clock is absent, and PIT module operation stops.
In halted mode with the PCSR[HALTED] bit set, PIT module operation stops. In halted mode with the
PCSR[HALTED] bit cleared, halted mode does not affect PIT operation. When halted mode is exited, the
PIT continues to operate in its pre-halted mode state, but any updates made in halted mode remain.
19.4
Signals
Freescale Semiconductor
19.5
This subsection describes the memory map and register structure for PIT0PIT3.
19.5.1
Memory Map
Bits 158
Bits 70
Access1
0x001x_0000
0x001x_0002
0x001x_0004
S/U
0x001x_0006
Unimplemented2
S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses
to supervisor only addresses have no effect and result in a cycle termination transfer error.
2 Accesses to unimplemented address locations have no effect and result in a cycle termination transfer error.
19.5.2
Registers
19-3
19.5.2.1
12
Field
Reset
Address
PRE3
PRE2
PRE1
PRE0
R/W
DOZE
HALTED
OVW
PIE
PIF
RLD
EN
Reset
R/W
10
0000_0000
R/W
Field
11
0000_0000
R
R/W
Name
1512
118
PRE
Description
Reserved, should be cleared.
Prescaler. The read/write prescaler bits select the system clock divisor to generate the
PIT clock. To accurately predict the timing of the next count, change the PRE[3:0] bits
only when the enable bit (EN) is clear. Changing the PRE[3:0] resets the prescaler
counter. System reset and the loading of a new value into the counter also reset the
prescaler counter. Setting the EN bit and writing to PRE[3:0] can be done in this same
write cycle. Clearing the EN bit stops the prescaler counter.
PRE
PRE
0000
1000
512
0001
1001
1,024
0010
1010
2,048
0011
16
1011
4,096
0100
32
1100
8,192
0101
64
1101
16,384
0110
128
1110
32,768
0111
256
1111
65,536
Reserved.
Freescale Semiconductor
Name
Description
DOZE
Doze mode bit. The read/write DOZE bit controls the function of the PIT in doze mode.
Reset clears DOZE.
0 PIT function not affected in doze mode
1 PIT function stopped in doze mode
When doze mode is exited, timer operation continues from the state it was in before
entering doze mode.
HALTED
Halted mode bit. Controls the function of the PIT in halted mode. Reset clears
HALTED. During halted mode, register read and write accesses function normally.
When halted mode is exited, timer operation continues from the state it was in before
entering halted mode, but any updates made in halted mode remain.
0 PIT function not affected in halted mode
1 PIT function stopped in halted mode
Note: Changing the HALTED bit from 1 to 0 during halted mode starts the PIT timer.
Likewise, changing the HALTED bit from 0 to 1 during halted mode stops the PIT timer.
OVW
Overwrite. Enables writing to PMR to immediately overwrite the value in the PIT
counter.
0 Value in PMR replaces value in PIT counter when count reaches 0x0000.
1 Writing PMR immediately replaces value in PIT counter.
PIE
PIT interrupt enable. This read/write bit enables the PIF flag to generate interrupt
requests.
0 PIF interrupt requests disabled
1 PIF interrupt requests enabled
PIF
PIT interrupt flag. This read/write bit is set when the PIT counter reaches 0x0000.
Clear PIF by writing a 1 to it or by writing to PMR. Writing 0 has no effect. Reset clears
PIF.
0 PIT count has not reached 0x0000.
1 PIT count has reached 0x0000.
RLD
Reload bit. The read/write reload bit enables loading the value of PMR into the PIT
counter when the count reaches 0x0000.
0 Counter rolls over to 0xFFFF on count of 0x0000
1 Counter reloaded from PMR on count of 0x0000
EN
19.5.2.2
PIT enable bit. Enables PIT operation. When the PIT is disabled, the counter and
prescaler are held in a stopped state. This bit is read anytime, write anytime.
0 PIT disabled
1 PIT enabled
The 16-bit read/write PMR contains the timer modulus value that is loaded into the PIT counter when the
count reaches 0x0000 and the PCSR[RLD] bit is set.
When the PCSR[OVW] bit is set, PMR is transparent, and the value written to PMR is immediately loaded
into the PIT counter. The prescaler counter is reset anytime a new value is loaded into the PIT counter and
also during reset. Reading the PMR returns the value written in the modulus latch. Reset initializes PMR
to 0xFFFF.
19-5
Field
15
14
13
12
11
10
PM15
PM14
PM13
PM12
PM11
PM10
PM9
PM8
Reset
1111_1111
R/W
Field
R/W
7
PM7
PM6
PM5
PM4
PM3
PM2
PM1
PM0
Reset
1111_1111
R/W
R/W
Address IPSBAR + 0x0015_0002 and 0x0015_0003 (PIT0); 0x0016_0002 and 0x0016_0003 (PIT1);
0x0017_0002 and 0x0017_0003 (PIT2); 0x0018_0002 and 0x0018_0003 (PIT3)
19.5.2.3
The 16-bit, read-only PCNTR contains the counter value. Reading the 16-bit counter with two 8-bit reads
is not guaranteed to be coherent. Writing to PCNTR has no effect, and write cycles are terminated
normally.
Field
15
14
13
12
11
10
PC15
PC14
PC13
PC12
PC11
PC10
PC9
PC8
Reset
1111_1111
R/W
Field
R
7
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Reset
1111_1111
R/W
Address
R
IPSBAR + 0x0015_0004 and 0x0015_0005 (PIT0), 0x0016_0004 and 0x0016_0005 (PIT1),
0x0017_0004 and 0x0017_0005 (PIT2), 0x0018_0004 and 0x0018_0005 (PIT3)
19.6
Functional Description
19.6.1
This mode of operation is selected when the RLD bit in the PCSR register is set.
When the PIT counter reaches a count of 0x0000, the PIF flag is set in PCSR. The value in the modulus
register is loaded into the counter, and the counter begins decrementing toward 0x0000. If the PIE bit is
set in PCSR, the PIF flag issues an interrupt request to the CPU.
Freescale Semiconductor
Interrupt Operation
When the OVW bit is set in PCSR, the counter can be directly initialized by writing to PMR without
having to wait for the count to reach 0x0000.
PIT CLOCK
COUNTER
0x0002
0x0001
MODULUS
0x0000
0x0005
0x0005
PIF
19.6.2
This mode of operation is selected when the RLD bit in PCSR is clear. In this mode, the counter rolls over
from 0x0000 to 0xFFFF without reloading from the modulus latch and continues to decrement.
When the counter reaches a count of 0x0000, the PIF flag is set in PCSR. If the PIE bit is set in PCSR, the
PIF flag issues an interrupt request to the CPU.
When the OVW bit is set in PCSR, the counter can be directly initialized by writing to PMR without
having to wait for the count to reach 0x0000.
PIT CLOCK
COUNTER
0x0002
0x0001
MODULUS
0x0000
0xFFFF
0x0005
PIF
19.6.3
Timeout Specifications
The 16-bit PIT counter and prescaler supports different timeout periods. The prescaler divides the system
clock as selected by the PRE[3:0] bits in PCSR. The PM[15:0] bits in PMR select the timeout period.
PRE[3:0] (PM[15:0] + 1) 2
Timeout period = --------------------------------------------------------------------------system clock
19.7
Interrupt Operation
19-7
Flag
Enable Bit
Timeout
PIF
PIE
The PIF flag is set when the PIT counter reaches 0x0000. The PIE bit enables the PIF flag to generate
interrupt requests. Clear PIF by writing a 1 to it or by writing to the PMR.
Freescale Semiconductor
Chapter 20
General Purpose Timer Modules
(GPTA and GPTB)
The MCF5282 has two 4-channel general purpose timer modules (GPTA and GPTB). Each consists of a
16-bit counter driven by a 7-stage programmable prescaler.
A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit
range of the counter. Each of the four timer channels can be configured for input capture, which can
capture the time of a selected transition edge, or for output compare, which can generate output waveforms
and timer software delays. These functions allow simultaneous input waveform measurements and output
waveform generation.
Additionally, one of the channels, channel 3, can be configured as a 16-bit pulse accumulator that can
operate as a simple event counter or as a gated time accumulator. The pulse accumulator uses the GPT
channel 3 input/output pin in either event mode or gated time accumulation mode.
20.1
Features
20-1
20.2
Block Diagram
CLK[1:0]
System
Clock
SYNCx
Pin
PR[2:0]
PACLK
PACLK/256
PACLK/65536
Divide
by 2
MUX
Prescaler
TCRE
CxI
GPTCNTH:GPTCNTL
CxF
Clear Counter
16-Bit Counter
TOF
Interrupt
Logic
TOI
TE
Interrupt
Request
Channel 0
16-Bit Comparator
Edge
Detect
C0F
IOS0
CH. 0 Capture
PT0
LOGIC
GPTC0H:GPTC0L
16-Bit Latch
EDG0A
OM:OL0
EDG0B
TOV0
CH. 0 Compare
GPTx0
Pin
CHANNEL 1
16-Bit Comparator
Edge
Detect
C1F
IOS1
CH. 1 Capture
GPTC1H:GPTC1L
16-Bit Latch
EDG1A
OM:OL1
EDG1B
TOV1
PT1
LOGIC
CH. 1 Compare
GPTx1
Pin
Channel 2
Channel3
16-Bit Comparator
Edge
Detect
C3F
IOS3
PT3
LOGIC
GPTC3H:GPTC3L
16-Bit Latch
EDG3A
OM:OL3
EDG3B
TOV3
PEDGE
PAOVF
GPTPACNTH:GPTPACNTL
PACLK/256
Interrupt
Request
Interrupt
Logic
GPTx3
Pin
PAIF
MUX
PACLK
CH. 3 Compare
EDGE
DETECT
PAE
16-Bit Counter
PACLK/65536
CH.3 Capture
PA Input
Divide-by-64
Divide
by 2
System
Clock
PAMOD
PAOVI
PAI
PAOVF
PAIF
Freescale Semiconductor
20.3
This subsection describes the operation of the general purpose time module in low-power modes and
halted mode of operation. Low-power modes are described in the Power Management Module. Table 3-1
shows the general purpose timer module operation in the low-power modes, and shows how this module
may facilitate exit from each mode.
Table 20-1. Watchdog Module Operation in Low-power Modes
Low-power Mode
Watchdog Operation
Mode Exit
Wait
Normal
No
Doze
Normal
No
Stop
Stopped
No
Halted
Normal
No
General purpose timer operation stops in stop mode. When stop mode is exited, the general purpose timer
continues to operate in its pre-stop mode state.
20.4
Signal Description
20.4.1
Pin
Name
GPTPORT
Register Bit
GPTn0
PORTTn0
GPTn1
Function
Reset State
Pull-up
Input
Active
PORTTn1
Input
Active
GPTn2
PORTTn2
Input
Active
GPTn3
PORTTn3
Input
Active
SYNCn
PORTE[3:0]1
Input
Active
GPTn[2:0]
The GPTn[2:0] pins are for channel 20 input capture and output compare functions. These pins are
available for general-purpose input/output (I/O) when not configured for timer functions.
20.4.2
GPTn3
The GPTn3 pin is for channel 3 input capture and output compare functions or for the pulse accumulator
input. This pin is available for general-purpose I/O when not configured for timer functions.
MCF5282 Coldfire Microcontroller Users Manual, Rev. 2.3
Freescale Semiconductor
20-3
20.4.3
SYNCn
The SYNCn pin is for synchronization of the timer counter. It can be used to synchronize the counter with
externally-timed or clocked events. A high signal on this pin clears the counter.
20.5
See Table 20-3 for a memory map of the two GPT modules. GPTA has a base address of IPSBAR +
0x1A_0000. GPTB has a base address of IPSBAR + 0x1B_0000.
NOTE
Reading reserved or unimplemented locations returns zeroes. Writing to
reserved or unimplemented locations has no effect.
Table 20-3. GPT Modules Memory Map
IPSBAR Offset
Bits 70
Access1
GPTA
GPTB
0x1A_0000
0x1B_0000
0x1A_0001
0x1B_0001
0x1A_0002
0x1B_0002
0x1A_0003
0x1B_0003
0x1A_0004
0x1B_0004
0x1A_0006
0x1B_0006
0x1A_0007
0x1B_0007
Reserved2
0x1A_0008
0x1B_0008
0x1A_0009
0x1B_0009
0x1A_000A
0x1B_000a
Reserved(2)
0x1A_000B
0x1B_000b
0x1A_000C
0x1B_000c
0x1A_000D
0x1B_000d
0x1A_000E
0x1B_000e
0x1A_000F
0x1B_000f
0x1A_0010
0x1B_0010
0x1A_0011
0x1Bb_0011
0x1A_0012
0x1B_0012
0x1A_0013
0x1B_0013
0x1A_0014
0x1B_0014
0x1A_0015
0x1B_0015
0x1A_0016
0x1B_0016
Freescale Semiconductor
1
2
Bits 70
Access1
GPTA
GPTB
0x1A_0017
0x1B_0017
0x1A_0018
0x1B_0018
0x1A_0019
0x1B_0019
0x1A_001A
0x1B_001A
0x1A_001B
0x1B_001B
(2)
0x1A_001C
0x1B_001C
Reserved
0x1A_001D
0x1B_001D
0x1A_001E
0x1B_001E
0x1A_001F
0x1B_001F
20.5.1
Field
Reset
IOS
0000_0000
R/W
Address
R/W
IPSBAR + 0x401A_0000, 0x401B_0000
Name
74
30
IOS
Description
Reserved, should be cleared.
I/O select. The IOS[3:0] bits enable input capture or output compare operation for the
corresponding timer channels. These bits are read anytime (always read 0x00), write
anytime.
1 Output compare enabled
0 Input capture enabled
20-5
20.5.2
Field
Reset
FOC
0000_0000
R/W
R/W
Address
Name
74
30
FOC
Description
Reserved, should be cleared.
Force output compare.Setting an FOC bit causes an immediate output compare on
the corresponding channel. Forcing an output compare does not set the output
compare flag. These bits are read anytime, write anytime.
1 Force output compare
0 No effect
NOTE
A successful channel 3 output compare overrides any compare on channels
2:0. For each OC3M bit that is set, the output compare action reflects the
corresponding OC3D bit.
20.5.3
Field
Reset
R/W
Address
OC3M
0000_0000
R/W
IPSBAR + 0x1A_0002, 0x1B_0002
Freescale Semiconductor
Name
74
30
OC3M
20.5.4
Description
Reserved, should be cleared.
Output compare 3 mask. Setting an OC3M bit configures the corresponding PORTTn
pin to be an output. OC3Mn makes the GPT port pin an output regardless of the data
direction bit when the pin is configured for output compare (IOSx = 1). The OC3Mn
bits do not change the state of the PORTTnDDR bits. These bits are read anytime,
write anytime.
1 Corresponding PORTTn pin configured as output
0 No effect
Field
Reset
OC3D
0000_0000
R/W
R/W
Address
Name
74
30
OC3D
Description
Reserved, should be cleared.
Output compare 3 data. When a successful channel 3 output compare occurs, these
bits transfer to the PORTTn data register if the corresponding OC3Mn bits are set.
These bits are read anytime, write anytime.
NOTE
A successful channel 3 output compare overrides any channel 2:0 compares.
For each OC3M bit that is set, the output compare action reflects the
corresponding OC3D bit.
20.5.5
Field
CNTR
Reset
0000_0000_0000_0000
R/W
Address
Read only
IPSBAR + 0x1A_0004, 0x1B_0004
20-7
Name
Description
150
CNTR
Read-only field that provides the current count of the timer counter. To ensure
coherent reading of the timer counter, such that a timer rollover does not occur
between two back-to-back 8-bit reads, it is recommended that only word (16-bit)
accesses be used.
A write to GPTCNT may have an extra cycle on the first count because the write is not
synchronized with the prescaler clock. The write occurs at least one cycle before the
synchronization of the prescaler clock.
These bits are read anytime. They should be written to only in test (special) mode;
writing to them has no effect in normal modes.
20.5.6
Field
GPTEN
Reset
TFFCA
0000_0000
R/W
Address
R/W
IPSBAR + 0x1A_0006, 0x1B_0006
Name
Description
GPTEN
Enables the general purpose timer. When the timer is disabled, only the registers are
accessible. Clearing GPTEN reduces power consumption. These bits are read
anytime, write anytime.
1 GPT enabled
0 GPT and GPT counter disabled
65
TFFCA
30
Freescale Semiconductor
TFFCA
20.5.7
Field
TOV
Reset
0000_0000
R/W
R/W
Address
Name
74
30
TOV
20.5.8
Description
Reserved, should be cleared.
Toggles the output compare pin on overflow for each channel. This feature only takes
effect when in output compare mode. When set, it takes precedence over forced
output compare but not channel 3 override events. These bits are read anytime, write
anytime.
1 Toggle output compare pin on overflow feature enabled
0 Toggle output compare pin on overflow feature disabled
Field
Reset
R/W
Address
OM3
OL3
OM2
OL2
OM1
OL1
OM0
OL0
0000_0000
R/W
IPSBAR + 0x1A_0009, 0x1B_0009
20-9
Name
Description
70
OMx/OLx
20.5.9
Field
EDG3B
Reset
EDG0A
0000_0000
R/W
R/W
Address
Name
70
EDGn[B:A]
Description
Input capture edge control. Configures the input capture edge detector circuits for
each channel. These bits are read anytime, write anytime.
00 Input capture disabled
01 Input capture on rising edges only
10 Input capture on falling edges only
11 Input capture on any edge (rising or falling)
Field
Reset
R/W
Address
CI
0000_0000
R/W
IPSBAR + 0x1A_000C, 0x1B_000C
Freescale Semiconductor
Name
Description
74
30
CnI
Channel interrupt enable. Enables the C[3:0]F flags in GPT flag register 1 to generate
interrupt requests for each channel. These bits are read anytime, write anytime.
1 Corresponding channel interrupt requests enabled
0 Corresponding channel interrupt requests disabled
Field
Reset
TOI
PUPT
RDPT
TCRE
PR
0000_0000
R/W
Address
R/W
IPSBAR + 0x1A_000D, 0x1B_000D
Name
Description
TOI
PUPT
Enables pull-up resistors on the GPT ports when the ports are configured as inputs.
1 Pull-up resistors enabled
0 Pull-up resistors disabled
RDPT
TCRE
20-11
Name
Description
20
PRn
Prescaler bits. Select the prescaler divisor for the GPT counter.
000 Prescaler divisor 1
001 Prescaler divisor 2
010 Prescaler divisor 4
011 Prescaler divisor 8
100 Prescaler divisor 16
101 Prescaler divisor 32
110 Prescaler divisor 64
111 Prescaler divisor 128
Note: The newly selected prescaled clock does not take effect until the next
synchronized edge of the prescaled clock when the clock count transitions to 0x0000.)
Field
CF
Reset
0000_0000
R/W
R/W
Address
Name
74
30
CnF
Description
Reserved, should be cleared.
Channel flags. A channel flag is set when an input capture or output compare event
occurs. These bits are read anytime, write anytime (writing 1 clears the flag, writing 0
has no effect).
Note: When the fast flag clear all bit, GPTSCR1[TFFCA], is set, an input capture read
or an output compare write clears the corresponding channel flag. When a channel
flag is set, it does not inhibit subsequent output compares or input captures.
Field
Reset
R/W
Address
TOF
CF
0000_0000
R/W
Freescale Semiconductor
Name
Description
TOF
Timer overflow flag. Set when the GPT counter rolls over from 0xFFFF to 0x0000. If
the TOI bit in GPTSCR2 is also set, TOF generates an interrupt request. This bit is
read anytime, write anytime (writing 1 clears the flag, and writing 0 has no effect).
1 Timer overflow
0 No timer overflow
Note: When the GPT channel 3 registers contain 0xFFFF and TCRE is set, TOF does
not get set even though the GPT counter registers go from 0xFFFF to 0x0000. When
TOF is set, it does not inhibit subsequent overflow events.
64
30
CnF
Note: When the fast flag clear all bit, GPTSCR1[TFFCA], is set, any access to the GPT counter registers clears GPT flag register
2.
Field
CCNT
Reset
0000_0000_0000_0000
R/W
R/W
Address
Name
Description
150
CCNT
When a channel is configured for input capture (IOSn = 0), the GPT channel registers
latch the value of the free-running counter when a defined transition occurs on the
corresponding input capture pin.
When a channel is configured for output compare (IOSn = 1), the GPT channel
registers contain the output compare value.
To ensure coherent reading of the GPT counter, such that a timer rollover does not
occur between back-to-back 8-bit reads, it is recommended that only word (16-bit)
accesses be used. These bits are read anytime, write anytime (for the output compare
channel); writing to the input capture channel has no effect.
20-13
Field
Reset
PAE
PAMOD PEDGE
CLK
PAOVI
PAI
0000_0000
R/W
R/W
Address
Name
Description
PAE
PAMOD
Pulse accumulator mode. Selects event counter mode or gated time accumulation
mode.
1 Gated time accumulation mode
0 Event counter mode
PEDGE
Pulse accumulator edge. Selects falling or rising edges on the PAI pin to increment the
counter.
In event counter mode (PAMOD = 0):
1 Rising PAI edge increments counter
0 Falling PAI edge increments counter
In gated time accumulation mode (PAMOD = 1):
1 Low PAI input enables divide-by-64 clock to pulse accumulator and trailing rising
edge on PAI sets PAIF flag.
0 High PAI input enables divide-by-64 clock to pulse accumulator and trailing falling
edge on PAI sets PAIF flag.
Note: The timer prescaler generates the divide-by-64 clock. If the timer is not active,
there is no divide-by-64 clock.
To operate in gated time accumulation mode:
1. Apply logic 0 to RSTI pin.
2. Initialize registers for pulse accumulator mode test.
3. Apply appropriate level to PAI pin.
4. Enable GPT.
32
CLK
Select the GPT counter input clock. Changing the CLK bits causes an immediate
change in the GPT counter clock input.
00 GPT prescaler clock (When PAE = 0, the GPT prescaler clock is always the GPT
counter clock.)
01 PACLK
10 PACLK/256
11 PACLK/65536
Freescale Semiconductor
Chapter 28
Queued Analog-to-Digital Converter (QADC)
The queued analog-to-digital converter (QADC) is a 10-bit, unipolar, successive approximation converter.
Up to eight analog input channels can be supported using internal multiplexing. A maximum of 18 input
channels can be supported in the expanded, externally multiplexed mode.
The QADC consists of an analog front-end and a digital control subsystem. The analog section includes
input pins, an analog multiplexer, and sample and hold analog circuits.
The digital control section contains queue control logic to sequence the conversion process and interrupt
generation logic. Also included are the periodic/interval timer, control and status registers, the conversion
command word (CCW) table, random-access memory (RAM), and the result table RAM.
The bus interface unit (BIU) provides access to registers that configure the QADC, control the
analog-to-digital converter and queue mechanism, and present formatted conversion results.
28.1
Features
28-1
28.2
Block Diagram
External
MUX Address
Analog Power
Inputs
8 Analog Channels
(18 with External MUXing)
Reference
Inputs
External
Triggers
Analog Input MUX
and Digital
Signal Functions
10-bit
Analog-to-Digital
Converter
Digital
Control
64-Entry Queue
of 10-bit
Conversion
Command Words
(CCWs)
64-Entry Table
of 10-bit
Results
10-bit to 16-bit
Result Alignment
IPBUS
Interface
28.3
Modes of Operation
This subsection describes the two modes of operation in which the QADC does not perform conversions
in a regular fashion:
Debug mode
Stop mode
28.3.1
Debug Mode
The QDBG bit in the module configuration register (QADCMCR) governs behavior of the QADC when
the CPU enters background debug mode. When QDBG is clear, the QADC operates normally and is
unaffected by CPU background debug mode. See Section 28.6.1, QADC Module Configuration Register
(QADCMCR).
When QDBG is set and the CPU enters background debug mode, the QADC finishes any conversion in
progress and then freezes. This is QADC debug mode. Depending on when debug mode is entered, the
three possible queue freeze scenarios are:
When a queue is not executing, the QADC freezes immediately.
When a queue is executing, the QADC completes the current conversion and then freezes.
MCF5282 Coldfire Microcontroller Users Manual, Rev. 2.3
28-2
Freescale Semiconductor
Signals
If during the execution of the current conversion, the queue operating mode for the active queue is
changed, or a queue 2 abort occurs, the QADC freezes immediately.
When the QADC enters debug mode while a queue is active, the current CCW location of the queue
pointer is saved.
Debug mode:
Stops the analog clock
Holds the periodic/interval timer in reset
Prevents external trigger events from being captured
Keeps all QADC registers and RAM accessible
Although the QADC saves a pointer to the next CCW in the current queue, software can force the QADC
to execute a different CCW by reconfiguring the QADC. When the QADC exits debug mode, it looks at
the queue operating modes, the current queue pointer, and any pending trigger events to decide which
CCW to execute.
28.3.2
Stop Mode
The QADC enters a low-power idle state whenever the QSTOP bit is set or the CPU enters low-power stop
mode.
QADC stop:
Disables the analog-to-digital converter, effectively turning off the analog circuit
Aborts the conversion sequence in progress
Makes the data direction register (DDRQA), port data registers (PORTQA and PORTQB), control
registers (QACR2, QACR1, and QACR0) and the status registers (QASR1 and QASR0) read-only.
Only the module configuration register (QADCMCR) remains writable.
Makes the RAM inaccessible, so that valid data cannot be read from RAM (result word table and
CCW) or written to RAM (result word table and CCW)
Resets QACR1, QACR2, QASR0, and QASR1
Holds the QADC periodic/interval timer in reset
Because the bias currents to the analog circuit are turned off in stop mode, the QADC requires some
recovery time (tSR) to stabilize the analog circuits.
28.4
Signals
The QADC uses the external signals shown in Figure 28-2. There are eight channel/port signals that can
support up to 18 channels when external multiplexing is used (including internal channels). All of the
channel signals also have some general-purpose input or input/output (GPIO) functionality. In addition,
there are also two analog reference signals and two analog submodule power signals.
The QADC has external trigger inputs and multiplexer outputs that are shared with some of the analog
input signals.
28.4.1
The four port QA signals can be used as analog inputs or as a bidirectional 4-bit digital input/output port.
28-3
28.4.1.1
When used as analog inputs, the four port QA signals are referred to as AN[56:55, 53:52].
Internal Digital Power
Shared with Other Modules
VSSI
VDDI
VSSA
Analog Power and Ground V
DDA
AN0/ANW/PQB0
AN1/ANX/PQB1
AN2/ANY/PQB2
AN3/ANZ/PQB3
Analog
Mux and
Port Logic
AN52/MA0/PQA0
AN53/MA1/PQA1
AN55/ETRIG1/PQA3
AN56/ETRIG2/PQA4
Analog
Converter
Digital
Results
and
Control
PORT QA
VRH
VRL
PORT QB
Analog References
28.4.1.2
Port QA signals are referred to as PQA[4:3, 1:0] when used as a bidirectional 4-bit digital input/output
port. These four signals may be used for general-purpose digital input or digital output.
Port QA signals are connected to a digital input synchronizer during reads and may be used as
general-purpose digital inputs when the applied voltages meet high-voltage input (VIH) and low-voltage
input (VIL) requirements.
Each port QA signal is configured as an input or output by programming the port data direction register
(DDRQA). The digital input signal states are read from the port QA data register (PORTQA) when
DDRQA specifies that the signals are inputs. The digital data in PORTQA is driven onto the port QA
signals when the corresponding bits in DDRQA specify output. See Section 28.6.4, Port QA and QB Data
Direction Register (DDRQA & DDRQB).
28.4.2
The four port QB signals can be used as analog inputs or as a 4-bit digital I/O port.
28.4.2.1
When used as analog inputs, the four port QB signals are referred to as AN[3:0].
Freescale Semiconductor
Signals
28.4.2.2
Port QB signals are referred to as PQB[3:0] when used as a 4-bit digital input/output port. In addition to
functioning as analog input signals, the port QB signals are also connected to the input of a synchronizer
during reads and may be used as general-purpose digital inputs when the applied voltages meet VIH and
VIL requirements.
Each port QB signal is configured as an input or output by programming the port data direction register
(DDRQB). The digital input signal states are read from the port QB data register (PORTQB) when
DDRQB specifies that the signals are inputs. The digital data in PORTQB is driven onto the port QB
signals when the corresponding bits in DDRQB specify output. See Section 28.6.4, Port QA and QB Data
Direction Register (DDRQA & DDRQB).
28.4.3
The QADC has two external trigger signals, ETRIG2 and ETRIG1. Each external trigger input is
associated with one of the scan queues, queue 1 or queue 2. The assignment of ETRIG[2:1] to a queue is
made by the TRG bit in QADC control register 0 (QACR0). When TRG = 0, ETRIG1 triggers queue 1 and
ETRIG2 triggers queue 2. When TRG = 1, ETRIG1 triggers queue 2 and ETRIG2 triggers queue 1. See
Section 28.6.5, Control Registers Control Registers.
28.4.4
In non-multiplexed mode, the QADC analog input signals are connected to an internal multiplexer which
routes the analog signals into the internal A/D converter.
In externally multiplexed mode, the QADC allows automatic channel selection through up to four external
4-to-1 multiplexer chips. The QADC provides a 2-bit multiplexed address output to the external
multiplexer chips to allow selection of one of four inputs. The multiplexed address output signals, MA1
and MA0, can be used as multiplexed address output bits or as general-purpose I/O when external
multiplexed mode is not being used.
MA[1:0] are used as the address inputs for up to four 4-channel multiplexer chips. Because the MA[1:0]
signals are digital outputs in multiplexed mode, the state of their corresponding data direction bits in
DDRQA is ignored.
28.4.5
In external multiplexed mode, four of the port QB signals are redefined so that each represent four analog
input channels. See Table 28-1.
Table 28-1. Multiplexed Analog Input Channels
Multiplexed
Analog Input
Channels
ANW
ANX
ANY
ANZ
28-5
28.4.6
VRH and VRL are the dedicated input signals for the high and low reference voltages. Separating the
reference inputs from the power supply signals allows for additional external filtering, which increases
reference voltage precision and stability, and subsequently contributes to a higher degree of conversion
accuracy.
NOTE
VRH and VRL must be set to VDDA and VSSA potential, respectively. For
more information, refer to Section 28.9, Signal Connection
Considerations.
28.4.7
The VDDA and VSSA signals supply power to the analog subsystems of the QADC module. Dedicated
power is required to isolate the sensitive analog circuitry from the normal levels of noise present on the
digital power supply.
28.4.8
VDDH provides 5-V power to the digital I/O functions of QADC port QA and port QB. This allows those
signals to tolerate 5 volts when configured as inputs and drive 5 volts when configured as outputs.
28.5
Memory Map
The QADC occupies 1 Kbyte, or 512 half-word (16-bit) entries, of address space. Ten half-word registers
are control, port, and status registers, 64 half-word entries are the CCW table, and 64 half-word entries are
the result table which occupies 192 half-word address locations because the result data is readable in three
data alignment formats. Table 28-2 is the QADC memory map.
Table 28-2. QADC Memory Map
IPSBAR +
Offset
MSB
Access1
LSB
0x19_0000
0x19_0002
0x19_0004
Reserved3
0x19_0006
S/U
0x19_0008
S/U
0x19_000a
S/U
0x19_000c
S/U
0x19_000e
S/U
0x19_0010
S/U
0x19_0012
S/U
Freescale Semiconductor
Register Descriptions
MSB
LSB
Access1
0x19_0014
0x19_01fe
Reserved(3)
0x19_0200
0x19_027e
S/U
0x19_0280
0x19_02fe
S/U
0x19_0300
0x19_037e
S/U
0x19_0380
0x19_03fe
S/U
S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to
supervisor only addresses have no effect and result in a cycle termination transfer error.
2 Access results in the module generating an access termination transfer error if not in test mode.
3 Read/writes have no effect and the access terminates with a transfer error exception.
28.6
Register Descriptions
28.6.1
The QADCMCR contains bits that control QADC debug and stop modes and determine the privilege level
required to access most registers.
Field
15
14
QSTOP
QDBG
Reset
R/W
SUPV
Reset
R/W:
0000_0000
R/W:
Field
13
1000_0000
R/W
Address
R
IPSBAR + 0x19_0000, 0x19_0001
28-7
Name
15
QSTOP
Stop enable.
1 Force QADC to idle state.
0 QADC operates normally.
14
QDBG
Debug enable.
1 Finish any conversion in progress, then freeze in debug mode
0 QADC operates normally.
138
SUPV
60
28.6.2
Description
The QADCTEST is a reserved register. Attempts to access this register outside of factory test mode will
result in access privilege violation.
28.6.3
QADC ports QA and QB are accessed through the 8-bit PORTQA and PORTQB.
Port QA signals are referred to as PQA[4:3, 1:0] when used as a bidirectional, 4-bit, input/output port. Port
QA can also be used for analog inputs (AN[56:55, 53:52]), external trigger inputs (ETRIG[2:1]), and
external multiplexer address outputs (MA[1:0]).
Port QB signals are referred to as PQB[3:0] when used as a 4-bit, digital input-only port. Port QB can also
be used for non-multiplexed (AN[3:0]) and multiplexed (ANZ, ANY, ANX, ANW) analog inputs.
PORTQA and PORTQB are not initialized by reset.
7
PQA4
(AN56)
(ETRIG2)
PQA3
(AN55)
(ETRIG1)
PQA1
(AN53)
(MA1)
PQA0
(AN52)
(MA0)
Field
Reset
000
See Note
See Note
R/W:
R/W
R/W
Address
IPSBAR + 0x19_0006
Freescale Semiconductor
Register Descriptions
PQB3
(AN3)
(ANZ)
PQB2
(AN2)
(ANY)
PQA1
(AN1)
(ANX)
PQA0
(AN0)
(ANW)
Field
Reset
0000
See Note
R/W:
R/W
Address
IPSBAR + 0x19_0007
28.6.4
DDRQA and DDRQB are associated with port QA and QB digital I/O signals. Setting a bit in these
registers configures the corresponding signal as an output. Clearing a bit in these registers configures the
corresponding signal as an input. During QADC initialization, port QA and QB signals that will be used
as direct or multiplexed analog inputs must have their corresponding data direction register bits cleared.
When a port QA or QB signal that is programmed as an output is selected for analog conversion, the
voltage sampled is that of the output digital driver as influenced by the load.
When the MUX (externally multiplexed) bit is set in QACR0, the data direction register settings are
ignored for the bits corresponding to PQA[1:0], and the two multiplexed address (MA[1:0]) output signals.
The MA[1:0] signals are forced to be digital outputs, regardless of their data direction setting, and the
multiplexed address outputs are driven. The data returned during a port data register read is the value of
the MA[1:0] signals, regardless of their data direction setting.
Similarly, when the external trigger signals are assigned to port signals and external trigger queue
operating mode is selected, the data direction setting for the corresponding signals, PQA3 and/or PQA4,
is ignored. The port signals are forced to be digital inputs for ETRIG1 and/or ETRIG2. The data returned
during a port data register read is the value of the ETRIG[2:1] signals, regardless of their data direction
setting.
NOTE
Use caution when mixing digital and analog inputs. They should be isolated
as much as possible. Rise and fall times should be as large as possible to
minimize ac coupling effects.
7
Field
Reset
R/W:
Address
DDQA4
DDQA3
DDQA1
DDQA0
0000_0000
R
R/W
R/W
IPSBAR + 0x19_0008
28-9
Field
Reset
DDQB3
DDQB2
DDQB1
DDQB0
0000_0000
R/W
Address
IPSBAR + 0x19_0009
28.6.5
Control Registers
28.6.5.1
QACR0 establishes the QADC sampling clock (QCLK) with prescaler parameter fields and defines
whether external multiplexing is enabled. Typically, these bits are written once when the QADC is
initialized and not changed thereafter. The bits in this register are read anytime, write anytime (except
during stop mode).
Freescale Semiconductor
Register Descriptions
15
Field
14
MUX
13
12
Field
0000_0000
R/W
R/W
QPR6
QPR5
QPR4
QPR3
QPR2
QPR1
QPR0
Reset
R/W:
TRG
Reset
R/W:
11
0001_0011
R
R/W
Address
Name
Description
15
MUX
1413
12
TRG
117
60
QPR
fSYS
2(QPR[6:0] + 1)
where:
1 QPR[6:0] 127.
If QPR[6:0] = 0, then the QPR register field value is read as a 1 and the prescaler
divisor is 2.
The prescaler should be selected so that the QADC clock rate is within the required
fQCLK range. See MCF5282 Electrical Characteristics.
28-11
fSYS
Divisor
QPR[6:0]
fSYS
Divisor
QPR[6:0]
fSYS
Divisor
QPR[6:0]
fSYS
Divisor
0000000
0100000
66
1000000
130
1100000
194
0000001
0100001
68
1000001
132
1100001
196
0000010
0100010
70
1000010
134
1100010
198
0000011
0100011
72
1000011
136
1100011
200
0000100
10
0100100
74
1000100
138
1100100
202
0000101
12
0100101
76
1000101
140
1100101
204
0000110
14
0100110
78
1000110
142
1100110
206
0000111
16
0100111
80
1000111
144
1100111
208
0001000
18
0101000
82
1001000
146
1101000
210
0001001
20
0101001
84
1001001
148
1101001
212
0001010
22
0101010
86
1001010
150
1101010
214
0001011
24
0101011
88
1001011
152
1101011
216
0001100
26
0101100
90
1001100
154
1101100
218
0001101
28
0101101
92
1001101
156
1101101
220
0001110
30
0101110
94
1001110
158
1101110
222
0001111
32
0101111
96
1001111
160
1101111
224
0010000
34
0110000
98
1010000
162
1110000
226
0010001
36
0110001
100
1010001
164
1110001
228
0010010
38
0110010
102
1010010
166
1110010
230
0010011
40
0110011
104
1010011
168
1110011
232
0010100
42
0110100
106
1010100
170
1110100
234
0010101
44
0110101
108
1010101
172
1110101
236
0010110
46
0110110
110
1010110
174
1110110
238
0010111
48
0110111
112
1010111
176
1110111
240
0011000
50
0111000
114
1011000
178
1111000
242
0011001
52
0111001
116
1011001
180
1111001
244
0011010
54
0111010
118
1011010
182
1111010
246
0011011
56
0111011
120
1011011
184
1111011
248
0011100
58
0111100
122
1011100
186
1111100
250
0011101
60
0111101
124
1011101
188
1111101
252
0011110
62
0111110
126
1011110
190
1111110
254
0011111
64
0111111
128
1011111
192
1111111
256
Freescale Semiconductor
Register Descriptions
28.6.5.2
QACR1 is the mode control register for queue 1. This register governs queue operating mode and the use
of completion and/or pause interrupts. Typically, these bits are written once when the QADC is initialized
and are not changed thereafter.
Stop mode resets this register.
Field
15
14
13
12
11
10
CIE1
PIE1
SSE1
MQ112
MQ111
MQ110
MQ19
MQ18
Reset
0000_0000
R/W:
R/W
Field
Reset
0000_0000
R/W:
Address
Name
Description
15
CIE1
14
PIE1
Queue 1 pause interrupt enable. Enables an interrupt request when queue 1 enters
the pause state. The interrupt request is initiated when conversion is complete for a
CCW that has the pause bit set.
1 Enable the queue 1 pause interrupt.
0 Disable the queue 1 pause interrupt.
13
SSE1
128
MQ1n
Selects the operating mode for queue 1. Table 28-7 shows the bits in the MQ1 field
which enable different queue 1 operating modes.
70
28-13
Operating Mode
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
Reserved mode
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Freescale Semiconductor
Register Descriptions
28.6.5.3
QACR2 is the mode control register for queue 2. This register governs queue operating mode and the use
of completion and/or pause interrupts. Typically, these bits are written once when the QADC is initialized
and not changed thereafter.
QACR2 also includes a resume feature that selects the resumption point for queue 2 after its operation is
suspended by a queue 1 trigger event. The primary reason for selecting re-execution of the entire queue or
subqueue is to guarantee that all samples are taken consecutively in one scan (coherency).
When subqueues are not used, queue 2 execution restarts after suspension with the first CCW in queue 2.
When a pause has previously occurred in queue 2 execution, queue execution restarts after suspension with
the first CCW in the current subqueue.
A subqueue is considered to be a stand-alone sequence of conversions. Once a pause flag has been set to
report subqueue completion, that subqueue is not repeated until all CCWs in queue 2 are executed.
For example, the RESUME bit can be used when the frequency of queue 1 trigger events prohibit queue
2 completion. If the rate of queue 1 execution is too high, it is best for queue 2 execution to continue with
the CCW that was being converted when queue 2 was suspended. This allows queue 2 to eventually
complete execution.
The beginning of queue 2 is defined by programming the BQ2 field in QACR2. BQ2 is usually set before
or at the same time as the queue operating mode for queue 2 is selected. If BQ2[6:0] 64, queue 2 has no
entries, the entire CCW table is dedicated to queue 1, and CCW63 is the end-of-queue 1. If BQ2[6:0] is 0,
the entire CCW table is dedicated to queue 2. A special case occurs when an operating mode is selected
for queue 1 and a trigger event occurs for queue 1 with BQ2 set to 0. Queue 1 execution starts momentarily,
but is terminated after CCW0 is read. No conversions occur.
The BQ2[6:0] pointer may be changed dynamically to alternate between queue 2 scan sequences. A
change in BQ2 after queue 2 has begun or when queue 2 has a trigger pending does not affect queue 2 until
it is started again. For example, two scan sequences could be defined as follows: The first sequence starts
at CCW10, with a pause after CCW11 and an end of queue (EOQ) programmed in CCW15; the second
sequence starts at CCW16, with a pause after CCW17 and an EOQ programmed in CCW39.
With BQ2[6:0] set to CCW10 and the continuous-scan mode selected, queue execution begins. When the
pause is encountered in CCW11, an interrupt service routine can retarget BQ2[6:0] to CCW16. When the
end-of-queue is recognized in CCW15, an internal retrigger event is generated and execution restarts at
CCW16. When the pause software interrupt occurs again, BQ2 can be changed back to CCW10. After the
end-of-queue is recognized in CCW39, an internal retrigger event is created and execution now restarts at
CCW10.
If BQ2[6:0] is changed while queue 1 is active, the effect of BQ2[6:0] as an end-of-queue indication for
queue 1 is immediate. However, beware of the risk of losing the end-of-queue 1 when changing BQ2[6:0].
Using EOQ (channel 63) to end queue 1 is recommended.
NOTE
If BQ2[6:0] was assigned to the CCW that queue 1 is currently working on,
then that conversion is completed before the change to BQ2[6:0] takes
effect.
Each time a CCW is read for queue 1, the CCW location is compared with the current value of the
BQ2[6:0] pointer to detect a possible end-of-queue condition. For example, if BQ2[6:0] is changed to
CCW3 while queue 1 is converting CCW2, queue 1 is terminated after the conversion is completed.
However, if BQ2[6:0] is changed to CCW1 while queue 1 is converting CCW2, the QADC would not
28-15
recognize a BQ2[6:0] end-of-queue condition until queue 1 execution reached CCW1 again, presumably
on the next pass through the queue.
Stop mode resets this register (0x007f)
Field
15
14
13
12
11
10
CIE2
PIE2
SSE2
MQ212
MQ211
MQ210
MQ29
MQ28
Reset
0000_0000
R/W:
R/W
Field RESUME
BQ26
BQ25
BQ24
BQ23
BQ22
BQ21
BQ20
Reset
0111_1111
R/W:
R/W
Address
Freescale Semiconductor
Register Descriptions
Name
Description
15
CIE2
14
PIE2
Queue 2 pause interrupt enable. Enables an interrupt request when queue 2 enters
the pause state. The interrupt request is initiated when conversion is complete for a
CCW that has the pause bit set.
1 Enable the queue 2 pause interrupt.
0 Disable the queue 2 pause interrupt.
13
SSE2
128
MQ2
Selects the operating mode for queue 2. Table 28-9 shows the bits in the MQ1 field
which enable different queue 2 operating modes.
RESUME
Selects the resumption point for queue 2 after its operation is suspended due to a
queue 1 trigger event. If RESUME is changed during the execution of queue 2, the
change is not recognized until an end-of-queue condition is reached or the operating
mode of queue 2 is changed.
1 After suspension, begin execution with the aborted CCW in queue 2.
0 After suspension, begin execution with the first CCW of queue 2 or the current
subqueue of queue 2.
60
BQ2
Beginning of queue 2. Denotes the CCW location where queue 2 begins. This allows
the length of queue 1 and queue 2 to vary. The BQ2 field also serves as an
end-of-queue condition for queue 1.
Operating Modes
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
28-17
28.6.6
Operating Modes
01010
01011
01100
01101
01110
01111
Reserved mode
10000
Reserved mode
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Reserved mode
Status Registers
28.6.6.1
QASR0 contains information about the state of each queue and the current A/D conversion. The bits in
this register are read anytime. For flag bits (CF1, PF1, CF2, PF2, TOR1, TOR2), writing a 1 has no effect;
writing a 0 clears the bit. For QS[9:6] and CWP, writes have no effect. Stop mode resets this register.
The end of a queue is identified in the following cases:
When execution is complete on the CCW in the location prior to the one
pointed to by BQ2
When the current CCW contains the end-of-queue code (channel 63) instead of a valid channel
number
MCF5282 Coldfire Microcontroller Users Manual, Rev. 2.3
28-18
Freescale Semiconductor
Register Descriptions
When the currently completed CCW is in the last location of the CCW RAM.
Once PFn is set, the queue enters the paused state and waits for a trigger event to allow queue execution
to continue. However, a special case occurs when the CCW with the pause bit set is the last CCW in a
queue; queue execution is complete. The queue status becomes idle, not paused, and both the pause and
completion flags are set.
Another special case occurs when the queue is operating in software-initiated single-scan or
continuous-scan mode and a CCW pause bit is set. The QADC will set PFn and will also automatically
generate a retrigger event that restarts execution after two QCLK cycles. Pause mode is never entered.
In externally gated single-scan and continuous-scan mode, the behavior of PFn has been redefined. When
the gate closes before the end of the queue is reached, PFn is set to indicate that an incomplete scan has
occurred. In single-scan mode, a resultant interrupt can be used to determine if the queue should be enabled
again. In either externally gated mode, setting PFn indicates that the results for the queue have not been
collected during one scan (coherently).
NOTE:
If a set CCW pause bit is encountered in either externally gated mode, the
pause flag will not set, and execution continues without pausing. This has
allowed for the modified behavior of PF1 in the externally gated modes.
PFn is maintained by the QADC regardless of whether the corresponding
interrupt is enabled. PFn may be polled to determine if the QADC has
reached a pause in scanning a queue.
A trigger event generated by a transition on the external trigger signal or by the periodic/interval timer may
be captured as a trigger overrun. TORn cannot be set when the software-initiated single-scan mode or the
software-initiated continuous-scan mode is selected.
TORn is set when a trigger event is received while a queue is executing and before the scan has completed
or paused. TORn has no effect on queue execution.
After a trigger event has occurred for queue 1, and before the scan has completed or paused, additional
queue 1 trigger events are not retained. Such trigger events are considered unexpected, and the QADC sets
the TORn error status bit. An unexpected trigger event may denote a system overrun situation.
In externally gated continuous-scan mode, the behavior of TORn has been redefined. In the case that the
queue reaches an end-of-queue condition for the second time during an open gate, TORn is set. This is
considered an overrun condition. In this case, CF1 has been set for the first end-of-queue condition and
TORn sets for the second end-of-queue condition. For TOR1 to set, CF2 must not be cleared before the
second end-of-queue.
The QS field indicates the status of queue 1 and queue 2. Following are the five queue status conditions:
Idle
Active
Paused
Suspended
Trigger pending
The idle state occurs when a queue is disabled, when a queue is in a reserved mode, or when a queue is in
a valid queue operating mode awaiting a trigger event to initiate queue execution. One or both queues may
be in the idle state. When a queue is idle, CCWs are not being executed for that queue, the queue is not in
the pause state, and no trigger is pending.
28-19
A queue is in the active state when a valid queue operating mode is selected, when the selected trigger
event has occurred, or when the QADC is performing a conversion specified by a CCW from that queue.
Only one queue can be active at a time.
One or both queues can be in the paused state. A queue is paused when the previous CCW executed from
that queue had the pause bit set. The QADC does not execute any CCWs from the paused queue until a
trigger event occurs. Consequently, the QADC can service queue 2 while queue 1 is paused.
Only queue 2 can be in the suspended state. When a trigger event occurs on queue 1 while queue 2 is
executing, the current queue 2 conversion is aborted and the queue 2 status is reported as suspended. Queue
2 transitions back to the active state when queue 1 becomes idle or paused.
A trigger pending state is required because both queues cannot be active at the same time. The status of
queue 2 is changed to trigger pending when a trigger event occurs for queue 2 while queue 1 is active. In
the opposite case, when a trigger event occurs for queue 1 while queue 2 is active, queue 2 is aborted and
the status is reported as queue 1 active, queue 2 suspended. So due to the priority scheme, only queue 2
can be in the trigger pending state.
Two transition cases cause the queue 2 status to be trigger pending before queue 2 is shown to be in the
active state. When queue 1 is active and there is a trigger pending on queue 2, after queue 1 completes or
pauses, queue 2 continues to be in the trigger pending state for a few clock cycles. The fleeting status
conditions are:
Queue 1 idle with queue 2 trigger pending
Queue 1 paused with queue 2 trigger pending
Figure 28-12 displays the status conditions of the QS field as the QADC goes through the transition from
queue 1 active to queue 2 active.
When a queue enters the paused state, CWP points to the CCW with the pause bit set. While in pause, the
CWP value is maintained until a trigger event occurs on either queue. Usually, the CWP is updated a few
clock cycles before the queue status field shows that the queue has become active. For example, a read of
CWP may point to a CCW in queue 2, while the queue status field shows queue 1 paused and queue 2
trigger pending.
When the QADC finishes a queue scan, the CWP points to the CCW where the end-of-queue condition
was detected. Therefore, when the end-of-queue condition is a CCW with the EOQ code (channel 63), the
CWP points to the CCW containing the EOQ.
When the last CCW in a queue is the last CCW table location (CCW63), and it does not contain the EOQ
code, the end-of-queue is detected when the following CCW is read, so the CWP points to word CCW0.
Finally, when queue 1 operation is terminated after a CCW is read that is pointed to by BQ2, the CWP
points to the same CCW as BQ2.
Field
15
14
13
12
11
10
CF1
PF1
CF2
PF2
TOR1
TOR2
QS9
QS8
Reset
R/W:
0000_0000
R/W
Freescale Semiconductor
Register Descriptions
Field
QS7
QS6
CWP5
CWP4
CWP3
CWP2
CWP1
CWP0
Reset
0000_0000
R/W:
Address
Name
Description
15, 13
CFn
Queue completion flag. Indicates that a queue scan has been completed. CF[1:2] is
set by the QADC when the input channel sample requested by the last CCW in the
queue is converted, and the result is stored in the result table.
When CFn is set and queue completion interrupts are enabled (QACRn[CIEn] = 1),
the QADC requests an interrupt. The interrupt request is cleared when a 0 is written
to the CF1 bit after it has been read as a 1. Once set, CF1 can be cleared only by a
reset or by writing a 0 to it.
CF[1:2] is updated by the QADC regardless of whether the corresponding interrupt is
enabled. This allows polled recognition of the queue scan completion.
14, 12
PFn
Queue pause flag. Indicates that a queue scan has reached a pause. PF[1:2] is set by
the QADC when the current queue 1 CCW has the pause bit set, the selected input
channel has been converted, and the result has been stored in the result table.
When PFn is set and interrupts are enabled (QACRn[PIEn] = 1), the QADC requests
an interrupt. The interrupt request is cleared when a 0 is written to PFn, after it has
been read as a 1. Once set, PFn can be cleared only by reset or by writing a 0 to it.
PF1:
1 Queue 1 has reached a pause or gate closed before end-of-queue in gated mode.
0 Queue 1 has not reached a pause or gate has not closed before end-of-queue in
gated mode.
PF2:
1 Queue 2 has reached a pause.
0 Queue 2 has not reached a pause.
See Table 28-11 for a summary of CCW pause bit response in all scan modes.
1110
TORn
Queue trigger overrun flag. Indicates that an unexpected trigger event has occurred
for queue 1. TOR[1:2] can be set only while the queue is in the active state.
Once set, TOR[1:2] is cleared only by a reset or by writing a 0 to it.
1 At least one unexpected queue 1 trigger event has occurred or queue 1 reaches an
end-of-queue condition for the second time in externally gated continuous scan.
0 No unexpected queue 1 trigger events have occurred.
28-21
Name
Description
96
QS
Queue status. Indicates the current condition of queue 1 and queue 2. The two most
significant bits are associated primarily with queue 1, and the remaining two bits are
associated with queue 2. Because the priority scheme between the two queues
causes the status to be interlinked, the status bits must be considered as one 4-bit
field. Table 28-12 shows the bits in the QS field and how they denote the status of
queue 1 and queue 2.
The queue status field is affected by QADC stop mode. Because all of the analog logic
and control registers are reset, the queue status field is reset to queue 1 idle, queue
2 idle.
During debug mode, the queue status field is not modified. The queue status field
retains the status it held prior to freezing. As a result, the queue status can show
queue 1 active, queue 2 idle, even though neither queue is being executed during
freeze.
50
CWP
Command word pointer. Denotes which CCW is executing at present or was last
completed. CWP is a read-only field with a valid range of 0 to 63; write operations have
no effect.
During stop mode, CWP is reset to 0 because the control registers and the analog
logic are reset. When debug mode is entered, CWP is not changed; it points to the last
executed CCW.
Queue Operation
PF Asserts?
Pauses
Yes
Pauses
Yes
Pauses
Yes
Pauses
Yes
Software-initiated single-scan
Continues
Yes
Software-initiated continuous-scan
Continues
Yes
Continues
No
Continues
No
0000
0001
0010
0011
0100
0101
0110
Freescale Semiconductor
Register Descriptions
0111
1000
1001
1010
1011
1100
Reserved
1101
Reserved
1110
Reserved
1111
Reserved
28-23
Q2 Trigger Event
Q1 Idle/
Q2 Active
Q1 Trigger Event
Q1 Idle/
Q2 Idle
Q2 Complete
Q1 Complete
Q1 Active/
Q2 Idle
Delayed Transition
Q2 Pause Bit Set
Q1 Idle/
Q2 Trigger
Pending
(Temporary)
Q2 Trigger Event
Q2 Trigger Event
Q1 Trigger Event
Q1 Trigger Event
Q1 Paused/
Q2 Idle
Q1 Complete
Q1 Complete
Q1 Idle/
Q2 Paused
Q1 Trigger Event
Q1 Active/
Q2 Trigger
Pending
Q1 Active/
Q2 Suspended
Q1 Complete
Q1 Paused/
Q2 Trigger
Pending
(Temporary)
Delayed Transition
Q1 Trigger Event
Q2 Complete
Q1 Trigger Event
Q2 Trigger Event
Q1 Paused/
Q2 Paused
Freescale Semiconductor
Register Descriptions
28.6.6.2
14
Field
13
12
11
10
CWPQ15
CWPQ14
CWPQ13
CWPQ12
CWPQ11
CWPQ10
Reset
0011_1111
R/W:
Field
CWPQ25
CWPQ24
CWPQ23
CWPQ22
CWPQ21
CWPQ20
Reset
0011_1111
R/W:
Address
Name
1514
138
CWPQ1
76
50
CWPQ
28.6.7
Description
Reserved, should be cleared.
Queue 1 command word pointer. Points to the last queue 1 CCW executed. This is a
read-only field with a valid range of 0 to 63; writes have no effect. CWPQ1 always
points to the last executed CCW in queue 1, regardless of which queue is active.
In contrast to CWP, CPWQ1 is updated when a conversion result is written. When the
QADC finishes a conversion in queue 1, both the result register is written and CWPQ1
is updated.
When queue 1 operation is terminated after a CCW is read that is pointed to by BQ2,
CWP points to BQ2 while CWPQ1 points to the last queue 1 CCW.
During stop mode, CWPQ1 is reset to 63, because the control registers and the
analog logic are reset. When debug mode is entered, CWPQ1 is not changed; it points
to the last executed CCW in queue 1.
Reserved, should be cleared.
Queue 2 command word pointer. Points to the last queue 2 CCW executed. This is a
read-only field with a valid range of 0 to 63; writes have no effect. CWPQ2 always
points to the last executed CCW in queue 2, regardless which queue is active.
In contrast to CWP, CPWQ2 is updated when a conversion result is written. When the
QADC finishes a conversion in queue 2, both the result register is written and CWPQ2
is updated.
During stop mode, CWPQ2 is reset to 63 because the control registers and the analog
logic are reset. When debug mode is entered, CWPQ2 is not changed; it points to the
last executed CCW in queue 2.
The CCW table is 64 half-word (128 byte) long RAM with 10 bits of each entry implemented. The CCW
table is written by the user and is not modified by the QADC. Each CCW requests the conversion of one
analog channel to a digital result. The CCW specifies the analog channel number, the input sample time,
MCF5282 Coldfire Microcontroller Users Manual, Rev. 2.3
Freescale Semiconductor
28-25
and whether the queue is to pause after the current CCW. The bits in this register are read anytime (except
during stop mode), write anytime (except during stop mode).
15
10
BYP
Field
Reset
0000_00
Unaffected
R/W:
R/W
Field
IST1
IST0
CHAN5
CHAN4
CHAN3
CHAN2
CHAN1
CHAN0
Reset
Undefined
R/W:
Address
Name
Description
1510
Pause. Allows subqueues to be created within queue 1 and queue 2. The QADC
performs the conversion specified by the CCW with the pause bit set and then the
queue enters the pause state. Another trigger event causes execution to continue from
the pause to the next CCW.
1 Enter pause state after execution of current CCW.
0 Do not enter pause state after execution of current CCW.
NOTE: The P bit does not cause the queue to pause in software-initiated modes or
externally gated modes.
BYP
Sample amplifier bypass. Enables the amplifier bypass mode for a conversion and
subsequently changes the timing. The initial sample time is eliminated, reducing the
potential conversion time by two QCLKs. However, due to internal RC effects, a
minimum final sample time of four QCLKs must be allowed. When using this mode,
the external circuit should be of low source impedance. Loading effects of the external
circuitry need to be considered because the benefits of the sample amplifier are not
present.
1 Amplifier bypass mode enabled
0 Amplifier bypass mode disabled
NOTE: BYP is maintained for software compatibility but has no functional benefit on
this version of the QADC.
Freescale Semiconductor
Register Descriptions
Name
Description
76
IST
Input sample time. Specifies the length of the sample window. The input sample time
can be varied, under software control, to accommodate various input channel source
impedances. Longer sample times permit more accurate A/D conversions of signals
with higher source impedances.
Table 28-15 shows the four selectable input sample times.
The programmable sample time can also be used to adjust queue execution time or
sampling rate by increasing the time interval between conversions.
50
CHAN
Selects the input channel number. The CCW channel field is programmed with the
channel number corresponding to the analog input signal to be sampled and
converted. The analog input signal channel number assignments and the signal
definitions vary depending on whether the QADC multiplexed or non-multiplexed
mode is used by the application. As far as queue scanning operations are concerned,
there is no distinction between an internally or externally multiplexed analog input.
Table 28-16 shows the channel number assignments for non-multiplexed mode.
Table 28-17 shows the channel number assignments for multiplexed mode.
Programming the channel field to channel 63 denotes the end of the queue. Channels
60 to 62 are special internal channels. When one of the special channels is selected,
the sampling amplifier is not used. The value of VRL, VRH, or (VRHVRL)/2 is converted
directly. Programming any input sample time other than two has no benefit for the
special internal channels except to lengthen the overall conversion time.
00
01
10
11
Other
Functions
Signal Type
Binary
Decimal
PQB0
PQB1
PQB2
PQB3
AN0
AN1
AN2
AN3
Input
Input
Input
Input
000000
000001
000010
000011
0
1
2
3
PQA0
PQA1
AN52
AN53
Input/Output
Input/Output
110100
110101
52
53
PQA3
PQA4
AN55
AN56
ETRIG1
ETRIG2
Input/Output
Input/Output
110111
111000
55
56
VRL
VRH
Low reference
High reference
(VRHVRL)/2
Input
Input
111100
111101
111110
60
61
62
End-of-Queue Code
111111
63
28-27
All channels not listed are reserved or unimplemented and return undefined results.
Port Signal
Name
Analog
Signal Name
Other
Functions
Signal Type
Binary
Decimal
PQB0
PQB1
PQB2
PQB3
ANW
ANX
ANY
ANZ
Input
Input
Input
Input
000XX0
000XX1
010XX0
010XX1
0, 2, 4, 6
1, 3, 5, 7
16, 18, 20, 22
17, 19, 21, 23
PQA0
PQA1
MA0
MA1
Output
Output
52
53
PQA3
PQA4
AN55
AN56
ETRIG1
ETRIG2
Input/Output
Input/Output
110111
111000
55
56
VRL
VRH
Low Reference
High Reference
(VRHVRL)/2
Input
Input
111100
111101
111110
60
61
62
End-of-Queue Code
111111
63
All channels not listed are reserved or unimplemented and return undefined results.
28.6.8
Result Registers
The result word table is a 64 half-word (128 byte) long by 10-bit wide RAM. An entry is written by the
QADC after completing an analog conversion specified by the corresponding CCW table entry.
28.6.8.1
10
Field
RESULT
Reset
0000_00
Undefined
R/W:
R/W
Field
RESULT
Reset
Undefined
R/W:
R/W
Address
Freescale Semiconductor
Register Descriptions
Name
1510
90
RESULT
28.6.8.2
Description
Reserved, should be cleared.
The conversion result is unsigned, right-justified data.
Field
14
RESULT
Reset
Undefined
R/W:
R/W
Field
RESULT
Reset
Undefined
R/W:
R/W
Address
Name
Description
15
The left justified, signed format corresponds to a half-scale, offset binary, twos
complement data format. Conversion values corresponding to 1/2 full scale, 0x0200,
or higher are interpreted as positive values and have a sign bit of 0. An unsigned, right
justified conversion of 0x0200 would be represented as 0x0000 in this signed register,
where the sign = 0 and the result = 0. For an unsigned, right justified conversion of
0x3FF (full range or VRH), the signed equivalent in this register would be 0x7FC0, sign
= 0 and result = 0x1FF. For an unsigned, right justified conversion of 0x0000 (VRL), the
signed equivalent in this register would be 0x8000, sign = 1 and result = 0x000, a twos
complement value representing 512.
146
RESULT
50
28.6.8.3
Field
RESULT
Reset
Undefined
R/W:
R/W
28-29
Field
RESULT
Reset
Undefined
R/W:
R/W
Address
Name
156
RESULT
50
28.7
Description
The conversion result is unsigned, left-justified data.
Reserved, should be cleared.
Functional Description
28.7.1
Result Coherency
The QADC supports byte and half-word reads and writes across a 16-bit data bus interface. All conversion
results are stored in half-word registers, and the QADC does not allow more than one result register to be
read at a time. For this reason, the QADC does not guarantee read coherency.
Specifically, this means that while the QADC is operating, the data in the result registers can change from
one read to the next. Simply initiating a read of one result register will not prevent another from being
updated with a new conversion result.
Thus, to read any given number of result registers coherently, the queue or queues capable of modifying
these registers must be inactive. This can be guaranteed by system operating conditions (such as, known
completion of a software-initiated queue single-scan or no possibility of an externally triggered/gated
queue scan) or by simply disabling the queues (writing MQ1 and/or MQ2 to 0).
28.7.2
External Multiplexing
External multiplexer chips concentrate a number of analog signals onto a few QADC inputs. This is useful
for applications that need to convert more analog signals than the QADC converter can normally support.
External multiplexing also puts the multiplexed chip closer to the signal source. This minimizes the
number of analog signals that need to be shielded due to the proximity of noisy high speed digital signals
at the microcontroller chip.
For example, four 4-input multiplexer chips can be put at the connector where the analog signals first
arrive on the printed circuit board. As a result, only four analog signals need to be shielded from noise as
they approach the microcontroller chip, rather than having to protect 16 analog signals. However, external
multiplexer chips may introduce additional noise and errors if not properly utilized. Therefore, it is
necessary to maintain low on resistance (the impedance of an analog switch when active within a
multiplexed chip) and insert a low pass filter (R/C) on the input side of the multiplexed chip.
Freescale Semiconductor
Functional Description
28.7.2.1
The QADC can use from one to four external multiplexer chips to expand the number of analog signals
that may be converted. Up to 16 analog channels can be converted through external multiplexer selection.
The externally multiplexed channels are automatically selected from the channel field of the CCW, the
same as internally multiplexed channels. The QADC is configured for the externally multiplexed mode by
setting the MUX bit in control register 0 (QACR0).
Figure 28-18 shows the maximum configuration of four external multiplexer chips connected to the
QADC. The external multiplexer chips select one of four analog inputs and connect it to one analog output,
which becomes an input to the QADC. The QADC provides two multiplexed address signals, MA[1:0], to
select one of four inputs. These inputs are connected to all four external multiplexer chips. The analog
output of the four multiplexer chips are each connected to separate QADC inputs (ANW, ANX, ANY, and
ANZ) as shown in Figure 28-18
28-31
AN1
AN3
AN5
AN7
MUX
MUX
AN0/ANW/PQB0
AN1/ANX/PQB1
AN2/ANY/PQB2
AN3/ANZ/PQB3
Port QB
AN0
AN2
AN4
AN6
AN55/ETRIG1PQA3
AN56/ETRIG2/PQA4
AN16
AN18
AN20
AN22
AN17
AN19
AN21
AN23
Port QA
AN52/MA0/PQA0
AN53/MA1/PQA1
MUX
MUX
When externally multiplexed mode is selected, the QADC automatically drives the MA output signals
from the channel number in each CCW. The QADC also converts the proper input channel (ANW, ANX,
ANY, and ANZ) by interpreting the CCW channel number. As a result, up to 16 externally multiplexed
channels appear to the conversion queues as directly connected signals. User software simply puts the
channel number of externally multiplexed channels into CCWs.
MCF5282 Coldfire Microcontroller Users Manual, Rev. 2.3
28-32
Freescale Semiconductor
Functional Description
Figure 28-18 shows that the two MA signals may also be analog input signals. When external multiplexing
is selected, none of the MA signals can be used for analog or digital inputs. They become multiplexed
address outputs and are unaffected by DDRQA[1:0].
28.7.2.2
The number of available analog channels varies, depending on whether external multiplexing is used. A
maximum of eight analog channels are supported by the internal multiplexing circuitry of the converter.
Table 28-21 shows the total number of analog input channels supported with 0 to 4 external multiplexer
chips.
Table 28-21. Analog Input Channels
Number of Analog Input Channels Available
Directly Connected + External Multiplexed = Total Channels1, 2
No External Mux
One External
Mux
Two External
Muxes
Three External
Muxes
Four External
Muxes
5+4=9
4 + 8 = 12
3 + 12 = 15
2 + 16 = 18
1
2
28.7.3
The external trigger inputs are not shared with two analog input signals.
When external multiplexing is used, two input channels are configured as multiplexed address
outputs, and for each external multiplexer chip, one input channel is a multiplexed analog input.
Analog Subsystem
This section describes the QADC analog subsystem, which includes the front-end analog multiplexer and
analog-to-digital converter.
28.7.3.1
The analog subsystem consists of the path from the input signals to the A/D converter block. Signals from
the queue control logic are fed to the multiplexer and state machine. The end-of-conversion (EOC) signal
and the successive approximation register (SAR) reflect the result of the conversion. Figure 28-19 shows
a block diagram of the QADC analog subsystem.
28-33
PQA4
4
Chan. Decode & MUX
16:1
CHAN[5:0]
6
PQA0
Input
Bias Circuit
Internal
Channel
Decode
Sample
Buffer
PQB0
PowerDown
VRH
VRL
VSSA
SAR Timing
10
Analog
Power
Comparator
QCLK
IST
Start Conv
End OF Conv
SAR[9:0]
10
VDDA
STOP
RST
10
PQB3
Successive
Approximation
Register
28.7.3.2
Total conversion time is made up of initial sample time, final sample time, and resolution time. Initial
sample time refers to the time during which the selected input channel is coupled through the sample buffer
amplifier to the sample capacitor. The sample buffer is used to quickly reproduce its input signal on the
sample capacitor and minimize charge sharing errors. During the final sampling period the amplifier is
bypassed, and the multiplexer input charges the sample capacitor array directly for improved accuracy.
During the resolution period, the voltage in the sample capacitor is converted to a digital value and stored
in the SAR as shown in Figure 28-20.
Initial sample time is fixed at two QCLK cycles. Final sample time can be 2, 4, 8, or 16 QCLK cycles,
depending on the value of the IST field in the CCW. Resolution time is 10 QCLK cycles.
A conversion requires a minimum of 14 QCLK cycles (7 s with a 2.0-MHz QCLK). If the maximum final
sample time period of 16 QCLKs is selected, the total conversion time is 28 QCLKs or 14 s (with a
2.0-MHz QCLK).
Freescale Semiconductor
Functional Description
Buffer
Sample
Time:
2 Cycles
Final
Sample
Time:
n Cycles
(2,4,8,16)
Resolution
Time:
10 Cycles
QCLK
Sample Time
If the amplifier bypass mode is enabled for a conversion by setting the amplifier bypass (BYP) field in the
CCW, the timing changes to that shown in Figure 28-21. See Section 28.6.7, Conversion Command Word
Table (CCW) for more information on the BYP field. The initial sample time is eliminated, reducing the
potential conversion time by two QCLKs. When using the bypass mode, the external circuit should be of
low source impedance (typically less than 10 k). Also, the loading effects on the external circuitry of the
QADC need to be considered, because the benefits of the sample amplifier are not present.
NOTE
Because of internal RC time constants, use of a two QCLK sample time in
bypass mode will cause serious errors when operating the QADC at high
frequencies.
Sample
Time:
n CYCLES
(2,4,8,16)
Resolution
Time:
10 Cycles
Sample Time
QCLK
28.7.3.3
The internal multiplexer selects one of the eight analog input signals for conversion. The selected input is
connected to the sample buffer amplifier or to the sample capacitor. The multiplexer also includes positive
and negative stress protection circuitry, which prevents deselected channels from affecting the selected
channel when current is injected into the deselected channels.
28.7.3.4
Sample Buffer
The sample buffer is used to raise the effective input impedance of the A/D converter, so that external
factors (higher bandwidth or higher impedance) are less critical to accuracy. The input voltage is buffered
onto the sample capacitor to reduce crosstalk between channels.
28.7.3.5
Comparator
The comparator output feeds into the SAR, which accumulates the A/D conversion result sequentially,
beginning with the MSB.
28-35
28.7.3.6
Bias
The bias circuit is controlled by the STOP signal to power-up and power-down all the analog circuits.
28.7.3.7
The input of the SAR is connected to the comparator output. The SAR sequentially receives the conversion
value one bit at a time, starting with the MSB. After accumulating the 10 bits of the conversion result, the
SAR data is transferred to the appropriate result location, where it may be read by user software.
28.7.3.8
State Machine
The state machine generates all timing to perform an A/D conversion. An internal start-conversion signal
indicates to the A/D converter that the desired channel has been sent to the MUX. CCW[IST[1:0]] denotes
the desired sample time. CCW[BYP] determines whether to bypass the sample amplifier. Once the end of
conversion has been reached a signal is sent to the queue control logic indicating that a result is available
for storage in the result RAM.
28.8
The digital control subsystem includes the control logic to sequence the conversion activity, the system
clock and periodic/interval timer, control and status registers, the conversion command word table RAM,
and the result word table RAM.
The central element for control of QADC conversions is the 64-entry conversion command word (CCW)
table. Each CCW specifies the conversion of one input channel. Depending on the application, one or two
queues can be established in the CCW table. A queue is a scan sequence of one or more input channels.
By using a pause mechanism, subqueues can be created in the two queues. Each queue can be operated
using one of several different scan modes. The scan modes for queue 1 and queue 2 are programmed in
control registers QACR1 and QACR2. Once a queue has been started by a trigger event (any of the ways
to cause the QADC to begin executing the CCWs in a queue or subqueue), the QADC performs a sequence
of conversions and places the results in the result word table.
28.8.1
This subsection describes the QADC priority scheme when trigger events on two queues overlap or
conflict.
28.8.1.1
Queue Priority
Queue 1 has priority over queue 2 execution. These cases show the conditions under which queue 1 asserts
its priority:
When a queue is not active, a trigger event for queue 1 or queue 2 causes the corresponding queue
execution to begin.
When queue 1 is active and a trigger event occurs for queue 2, queue 2 cannot begin execution until
queue 1 reaches completion or the paused state. The status register records the trigger event by
reporting the queue 2 status as trigger pending. Additional trigger events for queue 2, which occur
before execution can begin, are flagged as trigger overruns.
When queue 2 is active and a trigger event occurs for queue 1, the current queue 2 conversion is
aborted. The status register reports the queue 2 status as suspended. Any trigger events occurring
for queue 2 while it is suspended are flagged as trigger overruns. Once queue 1 reaches the
MCF5282 Coldfire Microcontroller Users Manual, Rev. 2.3
28-36
Freescale Semiconductor
completion or the paused state, queue 2 begins executing again. The programming of the RESUME
bit in QACR2 determines which CCW is executed in queue 2.
When simultaneous trigger events occur for queue 1 and queue 2, queue 1 begins execution and
the queue 2 status is changed to trigger pending.
When subqueues are paused
The pause feature can be used to divide queue 1 and/or queue 2 into multiple subqueues. A subqueue is
defined by setting the pause bit in the last CCW of the subqueue.
Figure 28-22 shows the CCW format and an example of using pause to create subqueues. Queue 1 is
shown with four CCWs in each subqueue and queue 2 has two CCWs in each subqueue.
The operating mode selected for queue 1 determines what type of trigger event causes the execution of
each of the subqueues within queue 1. Similarly, the operating mode for queue 2 determines the type of
trigger event required to execute each of the subqueues within queue 2.
For example, when the external trigger rising edge continuous-scan mode is selected for queue 1, and there
are six subqueues within queue 1, a separate rising edge is required on the external trigger signal after
every pause to begin the execution of each subqueue (refer to Figure 28-22).
The choice of single-scan or continuous-scan applies to the full queue, and is not applied to each subqueue.
Once a subqueue is initiated, each CCW is executed sequentially until the last CCW in the subqueue is
executed and the pause state is entered. Execution can only continue with the next CCW, which is the
beginning of the next subqueue. A subqueue cannot be executed a second time before the overall queue
execution has been completed.
28-37
Conversion Command
Word (CCW) Table
P
00
Beginning of Queue 1
00
0
0
1
Pause
0
0
0
1
Pause
0
0
BQ2 0
1
End of Queue 1
Channel Select,
Sample, Hold,
A/D Conversion
Beginning of Queue 2
Pause
0
1
Pause
0
1
Pause
63
Pause
End of Queue 2
63
Trigger events which occur during the execution of a subqueue are ignored, but the trigger overrun flag is
set. When a continuous-scan mode is selected, a trigger event occurring after the completion of the last
subqueue (after the queue completion flag is set), causes the execution to continue with the first subqueue,
starting with the first CCW in the queue.
When the QADC encounters a CCW with the pause bit set, the queue enters the paused state after
completing the conversion specified in the CCW with the pause bit. The pause flag is set in QASR0, and
a pause interrupt may be requested. The status of the queue is shown to be paused, indicating completion
of a subqueue. The QADC then waits for another trigger event to again begin execution of the next
subqueue.
28.8.1.2
Because there are two conversion command queues and only one A/D converter, a priority scheme
determines which conversion occurs. Each queue has a variety of trigger events that are intended to initiate
conversions, and they can occur asynchronously in relation to each other and other conversions in
progress. For example, a queue can be idle awaiting a trigger event; a trigger event can have occurred, but
the first conversion has not started; a conversion can be in progress; a pause condition can exist awaiting
another trigger event to continue the queue; and so on.
Freescale Semiconductor
The following paragraphs and figures outline the prioritizing criteria used to determine which conversion
occurs in each overlap situation.
NOTE
Each situation in Figure 28-23 through Figure 28-33 is labeled S1 through
S19. In each diagram, time is shown increasing from left to right. The
execution of queue 1 and queue 2 (Q1 and Q2) is shown as a string of
rectangles representing the execution time of each CCW in the queue. In
most of the situations, there are four CCWs (labeled C1 to C4) in both queue
1 and queue 2. In some of the situations, CCW C2 is presumed to have the
pause bit set, to show the similarities of pause and end-of-queue as
terminations of queue execution.
Trigger events are described in Table 28-22.
Table 28-22. Trigger Events
Trigger
Events
T1
T2
When a trigger event causes a CCW execution in progress to be aborted, the aborted conversion is shown
as a ragged end of a shortened CCW rectangle.
The situation diagrams also show when key status bits are set.
Table 28-23 describes the status bits.
Table 28-23. Status Bits
Bit
Function
CF flag
PF flag
Trigger overrun
error (TOR)
Set when a new trigger event occurs before the queue is finished
servicing the previous trigger event
Below the queue execution flows are three sets of blocks that show the status information that is made
available to the user. The first two rows of status blocks show the condition of each queue as:
Idle
Active
Pause
Suspended (queue 2 only)
Trigger pending
The third row of status blocks shows the 4-bit QS status register field that encodes the condition of the two
queues. Two transition status cases, QS = 0011 and QS = 0111, are not shown because they exist only very
briefly between stable status conditions.
28-39
The first three examples in Figure 28-23 through Figure 28-25 (S1, S2, and S3) show what happens when
a new trigger event is recognized before the queue has completed servicing the previous trigger event on
the same queue.
In situation S1 (Figure 28-23), one trigger event is being recognized on each queue while that queue is still
working on the previously recognized trigger event. The trigger overrun error status bit is set, and the
premature trigger event is otherwise ignored. A trigger event that occurs before the servicing of the
previous trigger event is through does not disturb the queue execution in progress.
T1
Q1:
T1
C1
C2
C3
C4
T2
TOR1
T2
CF1
Q2:
C1
C2
C3
TOR2
IDLE
Q1:
IDLE
0000
QS:
CF2
IDLE
ACTIVE
Q2:
C4
IDLE
ACTIVE
1000
0000
0000
0010
In situation S2 (Figure 28-24), more than one trigger event is recognized before servicing of a previous
trigger event is complete. The trigger overrun bit is again set, but the additional trigger events are otherwise
ignored. After the queue is complete, the first newly detected trigger event causes queue execution to begin
again. When the trigger event rate is high, a new trigger event can be seen very soon after completion of
the previous queue, leaving little time to retrieve the previous results. Also, when trigger events are
occurring at a high rate for queue 1, the lower priority queue 2 channels may not get serviced at all.
T1
T1
T1
T1
T1
T2
Q1:
C1
C2
C3
C4
C1
C2
C3
Q2:
TOR1 TOR1 TOR1
CF1
T2
T2
C2
C3
C4
C1
TOR2 TOR2
Q1:
IDLE
ACTIVE
1000
1000
CF2
IDLE
ACTIVE
IDLE
Q2:
QS:
IDLE
C4
CF1
0000
ACTIVE
IDLE
0010
0000
Situation S3 (Figure 28-25) shows that when the pause feature is used, the trigger overrun error status bit
is set the same way and that queue execution continues unchanged.
Freescale Semiconductor
T1
T1
C1
C2
C3
T2
TOR1
T2
TOR1
C1
ACTIVE
QS:
PF2
PAUSE
1001
0101
CF2
IDLE
ACTIVE
0110
0100
C4
TOR2
ACTIVE
1000
0000
C3
PAUSE
IDLE
Q2:
T2
CF1
C2
TOR2
IDLE
C4
T2
PF1
Q2:
Q1:
T1
0001
ACTIVE
IDLE
0010
0000
The next two situations consider trigger events that occur for the lower priority queue 2, while queue 1 is
actively being serviced.
Situation S4 (Figure 28-26) shows that a queue 2 trigger event is recognized while queue 1 is active is
saved, and as soon as queue 1 is finished, queue 2 servicing begins.
T1
Q1:
C1
C2
C3
C4
CF1
T2
C1
C2
C3
C4
Q2:
CF2
Q1:
IDLE
QS:
TRIGGERED
IDLE
Q2:
0000
IDLE
ACTIVE
1000
1011
ACTIVE
IDLE
0010
0000
Situation S5 (Figure 28-27) shows that when multiple queue 2 trigger events are detected while queue 1 is
busy, the trigger overrun error bit is set, but queue 1 execution is not disturbed. Situation S5 also shows
that the effect of queue 2 trigger events during queue 1 execution is the same when the pause feature is
used for either queue.
28-41
T1
Q1:
T1
C1
C2
T2 T2
C3
T2 T2
PF1
Q2:
C1
Q2:
QS:
IDLE
0110
CF2
IDLE
ACTIVE
ACTIVE
ACTIVE
1000 1011
0000
C4
TOR2
PAUSE
TRIG
IDLE
C3
PF2
ACTIVE
CF1
C2
TOR2
Q1:
C4
PAUSE
TRIG
ACTIVE
IDLE
0010
0000
The remaining situations, S6 through S11, show the impact of a queue 1 trigger event occurring during
queue 2 execution. Because queue 1 has higher priority, the conversion taking place in queue 2 is aborted
so that there is no variable latency time in responding to queue 1 trigger events.
In situation 6 (Figure 28-28), the conversion initiated by the second CCW in queue 2 is aborted just before
the conversion is complete, so that queue 1 execution can begin. Queue 2 is considered suspended. After
queue 1 is finished, queue 2 starts over with the first CCW, when the RESUME control bit is set to 0.
Situation S7 (Figure 28-29) shows that when pause operation is not used with queue 2, queue 2 suspension
works the same way.
T1
Q1:
T1
C1
C2
C3
C4
RESUME = 0
T2
PF1
Q2:
CF1
C1
C1
C2
C2
C3
C4
CF2
Q1:
Q2:
QS
IDLE
ACTIVE
PAUSE
IDLE
0000
1000
0100
ACTIVE
ACTIVE
IDLE
ACTIVE
SUSPEND
ACTIVE
0110
1010
0010
IDLE
0000
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T1
Q1:
T1
C1
C2
T2
Q2:
C3
PF1
C1
C1
C4
T2
C1
CF1
C3
C2
C3
C4
CF2
PF2
IDLE
Q1:
ACTIVE
Q2:
IDLE
ACTIVE
QS:
0000
0010
SUSPEND
PAUSE
ACTIVE
0101 0110
0110
1010
SUSPEND
1010
IDLE
ACTIVE
IDLE
0010
0000
Situations S8 and S9 (Figure 28-30 and Figure 28-31) repeat the same two situations with the RESUME
bit set to a 1. When the RESUME bit is set, following suspension, queue 2 resumes execution with the
aborted CCW, not the first CCW, in the queue.
T1
Q1:
T1
C1
C2
C3
C4
T2
PF1
Q2:
CF1
C1
C2
C2
C3
RESUME=1
C4
CF2
Q1:
IDLE
Q2:
QS:
ACTIVE
PAUSE
IDLE
0000
1000
0100
ACTIVE
ACTIVE
IDLE
ACTIVE
SUSPEND
ACTIVE
IDLE
0110
1010
0010
0000
28-43
T1
Q1:
T1
C1
C2
T2
Q2:
C3
PF1
C1
C1
C2
C4
T2
CF1
C4
C3
C2
C4
CF2
PF2
ACTIVE
IDLE
Q1:
Q2:
IDLE
ACTIVE
QS:
0000
0010
PAUSE
ACTIVE
1010
RESUME=1
0110 0101
IDLE
IDLE
SUSPEND ACT
0110
1010
0000
0010
Situations S10 and S11 (Figure 28-32 and Figure 28-33) show that when an additional trigger event is
detected for queue 2 while the queue is suspended, the trigger overrun error bit is set, the same as if queue
2 were being executed when a new trigger event occurs. Trigger overrun on queue 2 thus allows the user
to know that queue 1 is taking up so much QADC time that queue 2 trigger events are being lost.
T1
Q1:
T2
Q2:
T1
C1
C2
T2
C1
C3
PF1
T2
C1
C2
C2
TOR2
Q2:
IDLE
QS:
0000
ACTIVE
0010
SUSPEND
1010
T2
CF1
C3
C3
PF2
ACTIVE
IDLE
Q1:
C4
PAUSE
ACTIVE
PAUSE ACT
0110
0101 0110
C4
CF2
TOR2
ACTIVE
SUSPEND
1010
RESUME = 0
IDLE
ACTIVE
IDLE
0010
0000
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T1
C1
Q1:
T2
Q2:
T1
C2
T2
C1
PF1
C2
IDLE
QS:
0000
ACTIVE
C3
C4
PAUSE
RESUME = 1
C4
CF2
ACTIVE
ACTIVE
0110 0101
1010
CF1
TOR2
0010
C4
T2
PF2
ACTIVE
IDLE
Q2:
T2
C2
TOR2
Q1:
C3
0110
IDLE
SUSPEND ACT
1010
0010
IDLE
0000
The previous situations cover normal overlap conditions that arise with asynchronous trigger events on the
two queues. An additional conflict to consider is that the freeze condition can arise while the QADC is
actively executing CCWs. The conventional use for the debug mode is for software/hardware debugging.
When the CPU enters background debug mode, peripheral modules can cease operation. When freeze is
detected, the QADC completes the conversion in progress, unlike the abort that occurs when queue 1
suspends queue 2. After the freeze condition is removed, the QADC continues queue execution with the
next CCW in sequence.
Trigger events that occur during freeze are not captured. When a trigger event is pending for queue 2 before
freeze begins, that trigger event is remembered when the freeze is passed. Similarly, when freeze occurs
while queue 2 is suspended, after freeze, queue 2 resumes execution as soon as queue 1 is finished.
Situations 12 through 19 (Figure 28-34 to Figure 28-41) show examples of all of the freeze situations.
FREEZE
T1
Q1:
C1
C2
C3
C4
CF1
28-45
FREEZE
T2
Q2:
C1
C2
C3
C4
CF2
T1
Q1:
T1 T1
C1
C2
C3
C4
T2 T2
CF1
T2
Q2:
T2 T2
C1
C2
C3
C4
T1 T1
CF2
T1
Q1:
T1
C1
C2
T1
C3
PF1
C4
CF1
Freescale Semiconductor
TRIGGERS IGNORED
FREEZE
T2
T2
Q2:
C1
T2
C2
C3
C4
PF2
CF2
C1
C2
C3
C4
T2
CF1
Q2:
TRIGGER CAPTURED, RESPONSE DELAYED AFTER FREEZE
C1
C2
C3
C4
CF2
C1
C2
C3
C4
T2
Q2:
CF1
C1
C2
C3
C4
C4
CF2
28.8.2
Boundary Conditions
28-47
BQ2 (beginning of queue 2) is set beyond the end of the CCW table (64127) and a trigger event
occurs on queue 2. The end-of-queue condition is recognized immediately, the completion flag is
set, and the queue becomes idle. A conversion is not performed.
NOTE
Multiple end-of-queue conditions may be recognized simultaneously,
although there is no change in QADC behavior. For example, if BQ2 is set
to CCW0, CCW0 contains the EOQ code, and a trigger event occurs on
queue 1, the QADC reads CCW0 and detects both end-of-queue conditions.
The completion flag is set and queue 1 becomes idle.
Boundary conditions also exist for combinations of pause and end-of-queue. One case is when a pause bit
is in one CCW and an end-of-queue condition is in the next CCW. The conversion specified by the CCW
with the pause bit set completes normally. The pause flag is set. However, because the end-of-queue
condition is recognized, the completion flag is also set and the queue status becomes idle, not paused.
Examples of this situation include:
The pause bit is set in CCW5 and the channel 63 (EOQ) code is in CCW6.
The pause is in CCW63.
During queue 1 operation, the pause bit is set in CCW20 and BQ2 points to CCW21.
Another pause and end-of-queue boundary condition occurs when the pause and an end-of-queue
condition occur in the same CCW. Both the pause and end-of-queue conditions are recognized
simultaneously. The end-of-queue condition has precedence so a conversion is not performed for the CCW
and the pause flag is not set. The QADC sets the completion flag and the queue status becomes idle.
Examples of this situation are:
The pause bit is set in CCW10 and EOQ is programmed into CCW10.
During queue 1 operation, the pause bit set in CCW32, which is also BQ2.
28.8.3
Scan Modes
The QADC queuing mechanism allows application software to utilize different requirements for
automatically scanning input channels.
In single-scan mode, a single pass through a sequence of conversions defined by a queue is performed. In
continuous-scan mode, multiple passes through a sequence of conversions defined by a queue are
executed.
The possible modes are:
Disabled mode and reserved mode
Software-initiated single-scan mode
Externally triggered single-scan mode
Externally gated single-scan mode
Interval timer single-scan mode
Software-initiated continuous-scan mode
Externally triggered continuous-scan mode
Externally gated continuous-scan mode
Periodic timer continuous-scan mode
The following paragraphs describe single-scan and continuous-scan operations.
Freescale Semiconductor
28.8.4
Disabled Mode
When disabled mode is selected, the queue is not active. Trigger events cannot initiate queue execution.
When both queue 1 and queue 2 are disabled, there is no possibility of encountering wait states when
accessing CCW table and result RAM. When both queues are disabled, it is safe to change the QCLK
prescaler values.
28.8.5
Reserved Mode
Reserved mode is available for future mode definitions. When reserved mode is selected, the queue is not
active. The behavior is the same as disabled mode.
28.8.6
Single-Scan Modes
A single-scan queue operating mode is used to execute a single pass through a sequence of conversions
defined by a queue. By programming the MQ1 field in QACR1 or the MQ2 field in QACR2, these modes
can be selected:
Software-initiated single-scan mode
Externally triggered single-scan mode
Externally gated single-scan mode
Interval timer single-scan mode
NOTE
Queue 2 cannot be programmed for externally gated single-scan mode.
In all single-scan queue operating modes, queue execution is enabled by writing the single-scan enable bit
to a 1 in the queues control register. The single-scan enable bits, SSE1 and SSE2, are provided for queue
1 and queue 2, respectively.
Until a queues single-scan enable bit is set, any trigger events for that queue are ignored. The single-scan
enable bit may be set to a 1 during the same write cycle that selects the single-scan queue operating mode.
The single-scan enable bit can be written only to 1, but will always read 0. Once set, writing the single-scan
enable bit to 0 has no effect. Only the QADC can clear the single-scan enable bit. The completion flag,
completion interrupt, or queue status is used to determine when the queue has completed.
After the single-scan enable bit is set, a trigger event causes the QADC to begin execution with the first
CCW in the queue. The single-scan enable bit remains set until the queue is completed. After the queue
reaches completion, the QADC resets the single-scan enable bit to 0. Writing the single-scan enable bit to
a 1 or a 0 before the queue scan is complete has no effect; however, if the queue operating mode is changed,
the new queue operating mode and the value of the single-scan enable bit are recognized immediately. The
conversion in progress is aborted, and the new queue operating mode takes effect.
In software-initiated single-scan mode, writing a 1 to the single-scan enable bit causes the QADC to
generate a trigger event internally, and queue execution begins immediately. In the other single-scan queue
operating modes, once the single-scan enable bit is written, the selected trigger event must occur before
the queue can start. The single-scan enable bit allows the entire queue to be scanned once. A trigger
overrun is captured if a trigger event occurs during queue execution in an edge-sensitive external trigger
mode or a periodic/interval timer mode.
In the interval timer single-scan mode, the next expiration of the timer is the trigger event for the queue.
After queue execution is complete, the queue status is shown as idle. The queue can be restarted by setting
the single-scan enable bit to 1. Queue execution begins with the first CCW in the queue.
28-49
28.8.6.1
Software can initiate the execution of a scan sequence for queue 1 or 2 by selecting software-initiated
single-scan mode and writing the single-scan enable bit in QACR1 or QACR2. A trigger event is generated
internally and the QADC immediately begins execution of the first CCW in the queue. If a pause occurs,
another trigger event is generated internally, and then execution continues without pausing.
The QADC automatically performs the conversions in the queue until an end-of-queue condition is
encountered. The queue remains idle until the single-scan enable bit is again set. While the time to
internally generate and act on a trigger event is very short, the queue status field can be read as
momentarily indicating that the queue is paused. The trigger overrun flag is never set while in
software-initiated single-scan mode.
The software-initiated single-scan mode is useful when:
Complete control of queue execution is required
There is a need to easily alternate between several queue sequences
28.8.6.2
The externally triggered single-scan mode is available on both queue 1 and queue 2. Both rising and falling
edge triggered modes are available. A scan must be enabled by setting the single-scan enable bit for the
queue.
The first external trigger edge causes the queue to be executed one time. Each CCW is read and the
indicated conversions are performed until an end-of-queue condition is encountered. After the queue is
completed, the QADC clears the single-scan enable bit. The single-scan enable bit can be written again to
allow another scan of the queue to be initiated by the next external trigger edge.
The externally triggered single-scan mode is useful when the input trigger rate can exceed the queue
execution rate. Analog samples can be taken in sync with an external event, even though application
software does not require data taken from every edge. Externally triggered single-scan mode can be
enabled to get one set of data and, at a later time, be enabled again for the next set of samples.
When a pause bit is encountered during externally triggered single-scan mode, another trigger event is
required for queue execution to continue. Software involvement is not required for queue execution to
continue from the paused state.
28.8.6.3
The QADC provides external gating for queue 1 only. When externally gated single-scan mode is selected,
the input level on the associated external trigger signal enables and disables queue execution. The polarity
of the external gate signal is fixed so that only a high level opens the gate and a low level closes the gate.
Once the gate is open, each CCW is read and the indicated conversions are performed until the gate is
closed. Queue scan must be enabled by setting the single-scan enable bit for queue 1. If a pause is
encountered, the pause flag does not set, and execution continues without pausing.
While the gate is open, queue 1 executes one time. Each CCW is read and the indicated conversions are
performed until an end-of-queue condition is encountered. When queue 1 completes, the QADC sets the
completion flag (CF1) and clears the single-scan enable bit. Set the single-scan enable bit again to allow
another scan of queue 1 to be initiated during the next open gate.
If the gate closes before queue 1 completes execution, the current CCW completes, execution of queue 1
stops, the single-scan enable bit is cleared, and the PF1 bit is set. The CWPQ1 field can be read to
determine the last valid conversion in the queue. The single-scan enable bit must be set again and the PF1
Freescale Semiconductor
bit should be cleared before another scan of queue 1 is initiated during the next open gate. The start of
queue 1 is always the first CCW in the CCW table.
Because the gate level is only sampled after each conversion during queue execution, closing the gate for
a period less than a conversion time interval does not guarantee the closure will be captured.
28.8.6.4
Both queues can use the periodic/interval timer in a single-scan queue operating mode. The timer interval
can range from 27 to 217 QCLK cycles in binary multiples. When the interval timer single-scan mode is
selected and the single-scan enable bit is set in QACR1 or QACR2, the timer begins counting. When the
time interval elapses, an internal trigger event is generated to start the queue and the QADC begins
execution with the first CCW.
The QADC automatically performs the conversions in the queue until a pause or an end-of-queue
condition is encountered. When a pause occurs, queue execution stops until the timer interval elapses
again, and queue execution continues. When queue execution reaches an end-of-queue situation, the
single-scan enable bit is cleared. Set the single-scan enable bit again to allow another scan of the queue to
be initiated by the interval timer.
The interval timer generates a trigger event whenever the time interval elapses. The trigger event may
cause queue execution to continue following a pause or may be considered a trigger overrun. Once queue
execution is completed, the single-scan enable bit must be set again to allow the timer to count again.
Normally, only one queue is enabled for interval timer single-scan mode, and the timer will reset at the
end-of-queue. However, if both queues are enabled for either single-scan or continuous interval timer
mode, the end-of-queue condition will not reset the timer while the other queue is active. In this case, the
timer will reset when both queues have reached end-of-queue. See Section 28.8.9, Periodic/Interval
Timer for a definition of interval timer reset conditions.
The interval timer single-scan mode can be used in applications that need coherent results. For example:
When it is necessary that all samples are guaranteed to be taken during the same scan of the analog
signals
When the interrupt rate in the periodic timer continuous-scan mode would be too high
In sensitive battery applications, where the interval timer single-scan mode uses less power than
the software-initiated continuous-scan mode
28.8.7
Continuous-Scan Modes
A continuous-scan queue operating mode is used to execute multiple passes through a sequence of
conversions defined by a queue. By programming the MQ1 field in QACR1 or the MQ2 field in QACR2,
these modes can be selected:
Software-initiated continuous-scan mode
Externally triggered continuous-scan mode
Externally gated continuous-scan mode
Periodic timer continuous-scan mode
NOTE
Queue 2 cannot be programmed for externally gated continuous-scan mode.
When a queue is programmed for a continuous-scan mode, the single-scan enable bit in the queue control
register does not have any meaning or effect. As soon as the queue operating mode is programmed, the
selected trigger event can initiate queue execution.
MCF5282 Coldfire Microcontroller Users Manual, Rev. 2.3
Freescale Semiconductor
28-51
In the case of software-initiated continuous-scan mode, the trigger event is generated internally and queue
execution begins immediately. In the other continuous-scan queue operating modes, the selected trigger
event must occur before the queue can start. A trigger overrun is captured if a trigger event occurs during
queue execution in the externally triggered continuous-scan mode or the periodic timer continuous-scan
mode.
After queue execution is complete, the queue status is shown as idle. Because the continuous-scan queue
operating modes allow the entire queue to be scanned multiple times, software involvement is not needed
for queue execution to continue from the idle state. The next trigger event causes queue execution to begin
again, starting with the first CCW in the queue.
NOTE
In continuous-scan modes, all samples are guaranteed to be taken during
one pass through the queue (coherently), except when a queue 1 trigger
event halts queue 2 execution. The time between consecutive conversions
has been designed to be consistent. However, for queues that end with a
CCW containing the EOQ code (channel 63), the time between the last
queue conversion and the first queue conversion requires one additional
CCW fetch cycle. Continuous samples are not coherent at this boundary.
In addition, the time from trigger to first conversion cannot be guaranteed,
because it is a function of clock synchronization, programmable trigger
events, queue priorities, and so on.
28.8.7.1
When software-initiated continuous-scan mode is selected, the trigger event is generated automatically by
the QADC. Queue execution begins immediately. If a pause is encountered, another trigger event is
generated internally, and execution continues without pausing. When the end-of-queue is reached, another
internal trigger event is generated and queue execution restarts at the beginning of the queue.
While the time to internally generate and act on a trigger event is very short, the queue status field can be
read as momentarily indicating that the queue is idle. The trigger overrun flag is never set while in
software-initiated continuous-scan mode.
The software-initiated continuous-scan mode keeps the result registers updated more frequently than any
of the other queue operating modes. The result table can always be read to get the latest converted value
for each channel. The channels scanned are kept up to date by the QADC without software involvement.
The software-initiated continuous-scan mode may be chosen for either queue, but is normally used only
with queue 2. When software-initiated continuous-scan mode is chosen for queue 1, that queue operates
continuously and queue 2, being lower in priority, never gets executed. The short interval of time between
a queue 1 completion and the subsequent trigger event is not sufficient to allow queue 2 execution to begin.
The software-initiated continuous-scan mode is a useful choice with queue 2 for converting channels that
do not need to be synchronized to anything or for slow-to-change analog channels. Interrupts are normally
not used with the software-initiated continuous-scan mode. Rather, the latest conversion results can be read
from the result table at any time. Once initiated, software action is not needed to sustain conversions of
channel.
28.8.7.2
The QADC provides external trigger signals for both queues. When externally triggered continuous-scan
mode is selected, a transition on the associated external trigger signal initiates queue execution. The
MCF5282 Coldfire Microcontroller Users Manual, Rev. 2.3
28-52
Freescale Semiconductor
polarity of the external trigger signal is programmable, so that a mode which begins queue execution on
the rising or falling edge can be selected. Each CCW is read and the indicated conversions are performed
until an end-of-queue condition is encountered. When the next external trigger edge is detected, queue
execution begins again automatically. Software involvement is not needed between trigger events.
When a pause bit is encountered in externally triggered continuous-scan mode, another trigger event is
required for queue execution to continue. Software involvement is not needed for queue execution to
continue from the paused state.
Some applications need to synchronize the sampling of analog channels to external events. There are cases
when it is not possible to use software initiation of the queue scan sequence, because interrupt response
times vary. Externally triggered continuous-scan mode is useful in these cases.
28.8.7.3
The QADC provides external gating for queue 1 only. When externally gated continuous-scan mode is
selected, the input level on the associated external trigger signal enables and disables queue execution. The
polarity of the external gate signal is fixed so that a high level opens the gate and a low level closes the
gate. Once the gate is open, each CCW is read and the indicated conversions are performed until the gate
is closed. When the gate opens again, queue execution automatically restarts at the beginning of the queue.
Software involvement is not needed between trigger events. If a pause in a CCW is encountered, the pause
flag does not set, and execution continues without pausing.
The purpose of externally gated continuous-scan mode is to continuously collect digitized samples while
the gate is open and to have the most recent samples available. It is up to the programmer to ensure that
the gate is not opened so long that an end-of-queue is reached.
In the event that the queue completes before the gate closes, the CF1 flag will set, and the queue will roll
over to the beginning and continue conversions until the gate closes. If the gate remains open and the CF1
flag is not cleared, when the queue completes a second time the TOR1 flag will set and the queue will
roll-over again. The queue will continue to execute until the gate closes or the mode is disabled.
If the gate closes before queue 1 completes execution, the QADC stops and sets the PF1 bit to indicate an
incomplete queue. The CWPQ1 field can be read to determine the last valid conversion in the queue. If the
gate opens again, execution of queue 1 restarts. The start of queue 1 is always the first CCW in the CCW
table. The condition of the gate is only sampled after each conversion during queue execution, so closing
the gate for a period less than a conversion time interval does not guarantee the closure will be captured.
28.8.7.4
The QADC includes a dedicated periodic timer for initiating a scan sequence on queue 1 and/or queue 2.
A programmable timer interval ranging from 27 to 217 times the QCLK period in binary multiples can be
selected. The QCLK period is prescaled down from the MCU clock.
When a periodic timer continuous-scan mode is selected, the timer begins counting. After the programmed
interval elapses, the timer generated trigger event starts the appropriate queue. The QADC automatically
performs the conversions in the queue until an end-of-queue condition or a pause is encountered. When a
pause occurs, the QADC waits for the periodic interval to expire again, then continues with the queue.
Once EOQ has been detected, the next trigger event causes queue execution to restart with the first CCW
in the queue.
The periodic timer generates a trigger event whenever the time interval elapses. The trigger event may
cause queue execution to continue following a pause or queue completion or may be considered a trigger
overrun. As with all continuous-scan queue operating modes, software action is not needed between
28-53
trigger events. Because both queues may be triggered by the periodic/interval timer, see Section 28.8.9,
Periodic/Interval Timer for a summary of periodic/interval timer reset conditions.
28.8.8
Figure 28-42 is a block diagram of the QCLK subsystem. The QCLK provides the timing for the A/D
converter state machine which controls the timing of the conversion. The QCLK is also the input to a
17-stage binary divider which implements the periodic/interval timer. To retain the specified analog
conversion accuracy, the QCLK frequency (fQCLK) must be within the tolerance specified in MCF5282
Electrical Characteristics.
Before using the QADC, the prescaler must be initialized with values that put the QCLK within the
specified range. Though most applications initialize the prescaler once and do not change it, write
operations to the prescaler fields are permitted.
QPR[6:0]
System Clock
Divide
by 2
Prescaler
SAR Control
ATD Converter
State Machine
SAR
10
Binary Counter
27 28 29 210 211 212 213 214 215 216 217
Queue 1 and Queue 2 Timer
Mode Rate Selection
Periodic/Interval Trigger
Event for Q1 and Q2
CAUTION
A change in the prescaler value while a conversion is in progress is likely to
corrupt the result. Therefore, any prescaler write operation should be done
only when both queues are in the disabled modes.
To accommodate the wide range of the system clock frequency, QCLK is generated by a programmable
prescaler which divides the system clock. To allow the A/D conversion time to be maximized across the
spectrum of system clock frequencies, the QADC prescaler permits the QCLK frequency to be software
selectable. The frequency of QCLK is set with the QPR field in QACR0.
28.8.9
Periodic/Interval Timer
The QADC periodic/interval timer can be used to generate trigger events at a programmable interval,
initiating execution of queue 1 and/or queue 2. The periodic/interval timer stays reset under these
conditions:
MCF5282 Coldfire Microcontroller Users Manual, Rev. 2.3
28-54
Freescale Semiconductor
Both queue 1 and queue 2 are programmed to any mode which does not use the periodic/interval
timer.
System reset is asserted.
Stop mode is enabled.
Debug mode is enabled.
NOTE
Interval timer single-scan mode does not start the periodic/interval timer
until the single-scan enable bit is set.
These conditions will cause a pulsed reset of the periodic/interval timer during use:
A queue 1 operating mode change to a mode which uses the periodic/interval timer, even if queue
2 is already using the timer
A queue 2 operating mode change to a mode which uses the periodic/interval timer, provided queue
1 is not in a mode which uses the periodic/interval timer
Roll over of the timer
During stop mode, the periodic/interval timer is held in reset. Because stop mode causes QACR1 and
QACR2 to be reset to 0, a valid periodic or interval timer mode must be written after leaving stop mode to
release the timer from reset.
When QADC debug mode is entered and a periodic or interval timer mode is selected, the timer counter
is reset after the conversion in progress completes. When the periodic or interval timer mode has been
enabled (the timer is counting), but a trigger event has not been issued, debug mode takes effect
immediately, and the timer is held in reset. Removal of the QADC debug condition restarts the counter
from the beginning. Refer to Section 28.3.1, Debug Mode for more information.
28-55
Conversion Command
Word (CCW) Table
00
Beginning of Queue 1
00
Channel Select,
Sample, Hold,
A/D Conversion
End of Queue 1
Beginning of Queue 2
63
63
End of Queue 2
[7:6]
[5:0]
15 14 13 12 11 10
[9:0]
BYP
IST
CHAN
0 0 0 0 0 0
RESULT
[15:6]
S
RESULT
[5:0]
0 0 0 0 0 0
[5:0]
RESULT
0 0 0 0 0 0
To prepare the QADC for a scan sequence, write to the CCW table to specify the desired channel
conversions. The criteria for queue execution is established by selecting the queue operating mode. The
queue operating mode determines what type of trigger event starts queue execution. A trigger event refers
to any of the ways that cause the QADC to begin executing the CCWs in a queue or subqueue. An external
trigger is only one of the possible trigger events.
A scan sequence may be initiated by:
A software command
Expiration of the periodic/interval timer
An external trigger signal
An external gated signal (queue 1 only)
The queue can be scanned in single pass or continuous fashion. When a single-scan mode is selected, the
scan must be engaged by setting the single-scan enable bit. When a continuous-scan mode is selected, the
queue remains active in the selected queue operating mode after the QADC completes each queue scan
sequence.
During queue execution, the QADC reads each CCW from the active queue and executes conversions in
three stages:
Initial sample
Final sample
MCF5282 Coldfire Microcontroller Users Manual, Rev. 2.3
28-56
Freescale Semiconductor
Resolution
During initial sample, a buffered version of the selected input channel is connected to the sample capacitor
at the input of the sample buffer amplifier.
During the final sample period, the sample buffer amplifier is bypassed, and the multiplexer input charges
the sample capacitor directly. Each CCW specifies a final input sample time of 2, 4, 8, or 16 QCLK cycles.
When an analog-to-digital conversion is complete, the result is written to the corresponding location in the
result word table. The QADC continues to sequentially execute each CCW in the queue until the end of
the queue is detected or a pause bit is found in a CCW.
When the pause bit is set in the current CCW, the QADC stops execution of the queue until a new trigger
event occurs. The pause status flag bit is set, and an interrupt may optionally be requested. After the trigger
event occurs, the paused state ends, and the QADC continues to execute each CCW in the queue until
another pause is encountered or the end of the queue is detected.
An end-of-queue condition occurs when:
The CCW channel field is programmed with 63 to specify the end of the queue.
The end-of-queue 1 is implied by the beginning of queue 2, which is specified by the BQ2 field in
QACR2.
The physical end of the queue RAM space defines the end of either queue.
When any of the end-of-queue conditions is recognized, a queue completion flag is set, and if enabled, an
interrupt is requested. These situations prematurely terminate queue execution:
Queue 1 is higher in priority than queue 2. When a trigger event occurs on queue 1 during queue 2
execution, the execution of queue 2 is suspended by aborting the execution of the CCW in progress,
and queue 1 execution begins. When queue 1 execution is complete, queue 2 conversions restart
with the first CCW entry in queue 2 or the first CCW of the queue 2 subqueue being executed when
queue 2 was suspended. Alternately, conversions can restart with the aborted queue 2 CCW entry.
The RESUME bit in QACR2 selects where queue 2 begins after suspension. By choosing to
re-execute all of the suspended queue 2 CCWs (RESUME = 0), all of the samples are guaranteed
to have been taken during the same scan pass. However, a high trigger event rate for queue 1 can
prevent completion of queue 2. If this occurs, execution of queue 2 can begin with the aborted
CCW entry (RESUME = 1).
Any conversion in progress for a queue is aborted when that queues operating mode is changed to
disabled. Putting a queue into the disabled mode does not power down the converter.
Changing a queues operating mode to another valid mode aborts any conversion in progress. The
queue restarts at its beginning once an appropriate trigger event occurs.
For low-power operation, the stop bit can be set to prepare the module for a loss of clocks. The
QADC aborts any conversion in progress when stop mode is entered.
When the QADC debug bit is set and the CPU enters background debug mode, the QADC freezes
at the end of the conversion in progress. After leaving debug mode, the QADC resumes queue
execution beginning with the next CCW entry. Refer to Section 28.3.1, Debug Mode for more
information.
28-57
Chapter 33
Electrical Characteristics
This chapter contains electrical specification tables and reference timing diagrams for the MCF5282
microcontroller unit. This section contains detailed information on power considerations, DC/AC
electrical characteristics, and AC timing specifications of MCF5282.
The electrical specifications are preliminary and are from previous designs or design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle; however,
these specifications will be met for production silicon. Finalized specifications will be published after
complete characterization and device qualifications have been completed.
NOTE
The parameters specified in this MCU document supersede any values
found in the module specifications.
33.1
Maximum Ratings
Table 33-1. Absolute Maximum Ratings1, 2
Rating
Symbol
Value
Unit
VDD
0.3 to +4.0
VDDPLL
0.3 to +4.0
VSTBY
0.3 to + 4.0
VDDF
0.3 to +4.0
VPP
0.3 to + 6.0
VDDA
0.3 to +6.0
VRH
0.3 to +6.0
VDDH
0.3 to +6.0
Supply Voltage
VIN
0.3 to + 6.0
VAIN
0.3 to + 6.0
VEXTAL
0 to 3.3
VXTAL
0 to 3.3
ID
25
mA
IDD
300
mA
TA
40 to 85
Tstg
65 to 150
Tj
105
oC
HBM
2000
Model6
33-1
Electrical Characteristics
2
4
5
33.2
This device contains circuitry protecting against damage due to high static voltage or electrical
fields; however, it is advised that normal precautions be taken to avoid application of any
voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either
VSS or VDD).
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive and negative clamp voltages,
then use the larger of the two values. 6.0V voltage excludes XTAL and EXTAL pads.
All functional non-supply pins are internally clamped to VSS and VDD.
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (Vin > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Insure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power (ex; no
clock).Power supply must maintain regulation within operating VDD range during instantaneous
and operating maximum current conditions.
All ESD testing methodology is in conformity with CDF-AEC-Q100 Stress Test Qualification for
Automotive Grade Integrated Circuits.
Thermal Characteristics
2
3
4
5
Value
Unit
JMA
261,2
C/W
JMA
231,2
C/W
Junction to board
JB
153
C/W
Junction to case
JC
104
C/W
jt
21,5
C/W
Symbol
Natural convection
JMA and jt parameters are simulated in accordance with EIA/JESD Standard 51-2 for natural convection.
Freescale recommends the use of JA and power dissipation specifications in the system design to prevent device
junction temperatures from exceeding the rated specification. System designers should be aware that device
junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the
device junction temperature specification can be verified by physical measurement in the customers system using
the jt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is
written as Psi-JT.
Freescale Semiconductor
DC Electrical Specifications
Where:
TA= Ambient Temperature, C
QJMA= Package Thermal Resistance, Junction-to-Ambient, C/W
PD= PINT + PI/O
PINT= IDD VDD, Watts - Chip Internal Power
PI/O= Power Dissipation on Input and Output Pins User Determined
For most applications PI/O < PINT and can be neglected. An approximate relationship between
PD and TJ (if PI/O is neglected) is:
P D = K ( T J + 273C ) (2)
where K is a constant pertaining to the particular part. K can be determined from equation (3)
by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and
TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA.
33.3
DC Electrical Specifications
Table 33-3. DC Electrical Specifications1
(VSS = VSSPLL= VSSF = VSSA= 0 VDC)
Characteristic
Symbol
Min
Max
Unit
VIH
0.7 x VDD
5.25
VIL
Input Hysteresis
VHYS
0.06 x
VDD
mV
Iin
-1.0
1.0
IOZ
-1.0
1.0
VOH
VDD - 0.5
__
VOL
__
0.5
IAPU
-10
-130
7
7
Input Capacitance
All input-only pins
All input/output (three-state) pins
Cin
pF
33-3
Electrical Characteristics
Symbol
Load Capacitance3
(50% Partial Drive)
(100% Full Drive)
Min
Max
Unit
pF
CL
VDD
25
50
2.7
3.6
0.0
1.8
3.6
3.6
2.7
3.6
V
V
VSTBY
Refer to Table 33-8 through Table 33-12 for additional PLLQADC, and Flash specifications.
This parameter is characterized before qualification rather than 100% tested.
3
Refer to the chip configuration section for more information. Drivers for the SDRAM pins are at 25pF
drive strength.Drivers for the QADC pins are at 50pF drive strength.
2
33.4
Typical
Master Mode
Typical
Single Chip
Mode1
Max2
Unit
IDD
25
7.9
mA
IDD
7.3
5.6
mA
IDD
4.5
4.7
mA
IDD
400
750
1000
Characteristic
Single chip mode current measured with all pins in general purpose input mode except for the UART0 and FEC pins that are enabled
for their module functionality.
2 Maximum values can vary depending on the systems state and signal loading.
Figure 33-1 shows typical WAIT/DOZE and RUN mode power consumption for both master and single
chip mode as measured on an M5282EVB.
For master mode the RUN mode current was measured executing a continuous loop that performs no
operation while running from the on-chip SRAM.
For WAIT/DOZE mode measurements the peripherals on the device are in their default power savings
mode, so the WAIT and DOZE power consumption are the same. Some modules can be programmed to
shutdown in WAIT and/or DOZE modes. Refer to module chapters for more information.
All single chip mode measurements were taken with all pins in general purpose input mode except for the
UART0 and FEC pins that are enabled for their module functionality; however, neither module is being
accessed at the time of the current measurement. Single chip RUN mode current was measured executing
a continuous loop that performs no operation while running from the on-chip Flash.
MCF5282 Coldfire Microcontroller Users Manual, Rev. 2.3
33-4
Freescale Semiconductor
250
Idd (mA)
200
150
50
0
8
16
24
32
40
48
56
64
72
80
Frequency (MHz)
Table 33-5 lists the estimated power consumption for individual modules. The current consumption is for
the module itself and does not include power for I/O.
Table 33-5. Estimated Module Power Consumption
Module
Estimated Power
Unit
EIM
20
A/MHz
SDRAMC
30
A/MHz
FEC
60
A/MHz
Watchdog
1.5
A/MHz
PIT
A/MHz
FlexCAN
15
A/MHz
75
A/MHz
33-5
Electrical Characteristics
Current
181.6 mA
155 mA
Symbol
Typical
Max
Unit
200
240
150
mA
mA
mA
125
150
mA
mA
4
2
1
10
mA
mA
mA
A
10
7
20
A
mA
A
16.53
254
1.64
0.2
30
64
20
10
mA
mA
mA
A
5.0
10.0
mA
A
IDD
IDDPLL
ISTBY
IDDF
IDDA
Current measured at maximum system clock frequency, all modules active, and default drive
strength with matching load.
2 Programming and erasing all 8 blocks of the Flash.
3 Measured with f
sys of 64 MHz.
4 Measured with f
sys of 32 MHz and fclk of 187.5 kHz.
Freescale Semiconductor
33.5
Min
Max
fref_crystal
fref_ext
fref_1:1
2
2
33.33
10.0
10.0
80
3, 4
4, 5
0
fref / 32
80
80
fLOR
100
1000
kHz
fSCM
MHz
tcst
10
ms
VDD- 1.0
2.0
VDD
VDD
VSS
VSS
1.0
0.8
VDD- 1.0
0.5
pF
500
10.5
500
ms
s
VIHEXT
VILEXT
VOL
VOL
tlpll
4, 5,8
Unit
MHz
fsys
Symbol
MHz
V
V
tlplk
tskew
-2
ns
tdc
40
60
% fsys
fUL
- 1.5
1.5
% fsys
fLCK
- 0.75
0.75
% % fsys
10
.01
% fsys
Duty Cycle of
reference 4
Cjitter
Freescale Semiconductor
33-7
Electrical Characteristics
8
Assuming a reference is available at power up, lock time is measured from the time VDD and VDDPLL are valid
to RSTO negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal start up
time must be added to the PLL lock time to determine the total start-up time.
9
PLL is operating in 1:1 PLL mode.
10
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
fsys. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency
increase the Cjitter percentage for a given interval
11
Based on slow system clock of 40 MHz measured at fsys max.
33.6
Symbol
Min
Max
Unit
VDDA
0.3
6.0
VDD
0.3
4.0
VRH
0.3
6.0
VSS VSSA
0.1
0.1
VDD VDDA
6.0
4.0
VRH VRL
0.3
6.0
VRH VDDA
6.0
6.0
VRL VSSA
0.3
0.3
VDDH VDDA
1.0
1.0
IMA
25
25
mA
1,
4, 5, 6
Symbol
Min
Max
Unit
VDDA
3.3
5.5
VSS VSSA
-100
100
mV
VRL
VSSA
VSSA + 0.1
VRH
VDDA 0.1
VDDA
VRH VRL
3.3
5.5
Freescale Semiconductor
Symbol
Min
Max
Unit
VINDC
VSSA0.3
VDDA + 0.3
VIH
0.7 (VDDA)
VDDA + 0.3
VIL
VSSA 0.3
0.4(VDDA)
VHYS
0.5
VOH
VDDH-0.8
IDDA
5.0
10.0
mA
A
IREF
IREF
250
2.0
A
mA
CL
50
pF
IOFF
-200
200
nA
15
10
Input Voltage
Total Input
PQA Not Sampling
PQB Not Sampling
Incremental Capacitance added during sampling
1
2
3
4
5
6
CIN
pF
QADC converter specifications are only guaranteed for VDDH and VDDA = 5.0V +/- 0.5V. VDDH and VDDA may be
powered down to 2.7V with only GPIO functions supported.
To obtain full-scale, full-range results, VSSA VRL VINDC VRH VDDA
Parameter applies to the following pins:
Port A: PQA[4:3]/AN[56:55]/ETRIG[2:1], PQA[1:0]/AN[53:52]/MA[1:0]
Port B: PQB[3:0]/AN[3:0]/AN[Z:W]
Current measured at maximum system clock frequency with QADC active.
Maximum leakage occurs at maximum operating temperature. Current decreases by approximately one-half for each 8
to 12 C, in the ambient temperature range of 50 to 125 C.
This parameter is characterized before qualification rather than 100% tested.
33-9
Electrical Characteristics
Parameter
QADC Clock (QCLK) Frequency1
Symbol
Min
Max
Unit
FQCLK
0.5
2.1
MHz
CC
14
28
QCLK
cycles
TCONV
7.0
14.0
TSR
10
mV
-2
Counts
-3
Counts
Conversion Cycles
Conversion Time
FQCLK = 2.0 MHz1
Min = CCW/IST =%00
Max = CCW/IST =%11
Resolution2
AE
error 3, 4, 5
7
1
2
3
4
Conversion characteristics vary with FQCLK rate. Reduced conversion accuracy occurs at max FQCLK rate. Using the
QADC pins as GPIO functions during conversions may result in degraded results. Best QADC conversion accuracy is
achieved at a frequency of 2 MHz.
At VRH VRL = 5.12 V, one count = 5 mV
Accuracy tested and guaranteed at VRH VRL = 5.0V 0.5V
Current Coupling Ratio, K, is defined as the ratio of the output current, Iout, measured on the pin under test to the
injection current, Iinj, when both adjacent pins are overstressed with the specified injection current. K = Iout/Iinj. The
input voltage error on the channel under test is calculated as Verr = Iinj * K * RS.
Performance expected with production silicon.
33.7
The Flash memory characteristics are shown in Table 33-12 and Table 33-13.
Table 33-12. SGFM Flash Program and Erase Characteristics
(VDDF = 2.7 to 3.6 V)
Parameter
System clock (read only)
System clock (program/erase)
1
Symbol
Min
Typ
Max
Unit
fsys(R)
80
MHz
fsys(P/E)
0.15
80
MHz
Symbol
Value
Unit
P/E
10,0002
Cycles
Retention
10
Years
Freescale Semiconductor
Electrical Characteristics
* The timings are also valid for inputs sampled on the negative clock edge.
1.5V
CLKOUT(66.67 MHz)
TSETUP
Invalid
Vh = VIH
Invalid
trise = 1.5 ns
Vl = VIL
Vh = VIH
CLKOUT
THOLD
tfall = 1.5 ns
Vl = VIL
B4
B5
Inputs
33.9
Characteristic
Symbol
Min
Max
Unit
tCHCV
0.5tCYC +10
ns
tCHBV
0.5tCYC +10
ns
Control Outputs
B6a
B6b
B6c
tCHOV
0.5tCYC +10
ns
B7
tCHCOI
0.5tCYC + 2
ns
B7a
tCHCI
0.5tCYC + 2
ns
Freescale Semiconductor
ANEXO 4
NMRA STANDARD
Electrical Standards
S 9.1
10
15
20
25
30
The NMRA baseline digital command control signal consists of a stream of transitions between two equal
voltage levels that have opposite polarity1. Alternate transitions separate one bit from the next. The
remaining transitions divide each bit into a first part and a last part. Digital Command Stations shall
encode bits within this digital command control stream of transitions by varying the duration of the parts of
the bits, or frequency of the transitions.
In a "1" bit, the first and last part of a bit shall have the same duration, and that duration shall nominally be
58 microseconds2, giving the bit a total duration of 116 microseconds. Digital Command Station
components shall transmit "1" bits with the first and last parts each having a duration of between 55 and 61
microseconds. A Digital Decoder must accept bits whose first and last parts have a duration of between 52
and 64 microseconds, as a valid bit with the value of "1".
In a "0" bit, the duration of the first and last parts of each transition shall nominally be greater than or
equal to 100 microseconds. To keep the DC component of the total signal at zero as with the "1" bits, the
first and last part of the "0" bit are normally equal to one another. Digital Command Station components
shall transmit "0" bits with each part of the bit having a duration of between 95 and 9900 microseconds
with the total bit duration of the "0" bit not exceeding 12000 microseconds. A Digital Decoder must accept
bits whose first or last parts have a duration of between 90 and 10000 microseconds as a valid bit with the
value of "0". Figure 1 provides an example of bits encoded using this technique.
Digital Decoders must accept one bits whose positive and negative components differ by as much as 6
microseconds.
1 Note
that since a locomotive or piece of rolling stock can be placed upon a given section of track facing in
either direction, it is impossible to define, from the point of view of a Digital Decoder, whether the first or
last part of a bit will have the "positive" voltage polarity.
2 All
40
Result
Bad
OK
OK
Bad
Result
OK
OK
OK
The NMRA digital signal applied to the track by any Digital Command Control system, as measured at the
power station output, shall have the following characteristics, as measured under conditions ranging from
no load to the maximum continuous load permitted by the power source. Transitions that cross the region
between -4 volts and +4 volts3 shall occur at 2.5 volts per microsecond or faster. This signal may contain
non-monotonic distortion at the zero-crossing transitions, provided that this distortion shall have an
amplitude of no greater than +/- 2 volts4.
50
55
Digital Decoders shall be designed to correctly decode signals with transitions whose slope is 2.0 volts per
microsecond or faster across the voltage range from -4 volts to +4 volts. A Digital Decoder shall correctly
decode at least 95% of properly addressed baseline packets, as defined in S-9.2, in the presence of noise
(and/or other types of signals) above 100 kHz with a total peak-to-peak amplitude of less than one fourth of
the peak-to-peak amplitude of the NMRA digital signal5.
The exact shape of the NMRA digital signal shall be designed to minimize electromagnetic radiation such
that a large layout operated using this standard can meet applicable United States Federal Communications
Commission electromagnetic interference requirements6.
30
4 This
standard specifically permits super-imposing non-NMRA signals upon the rails for other purposes,
provided that the NMRA Digital Decoder can reject these signals.
5 This
measurement is made with the Digital Decoder electrically connected to a track or accessory bus.
6 All
components of a NMRA compliant digital system shall meet all applicable FCC and/or CE
requirements.
2001,2004 by the National Model Railroad Association, Inc.
S-9.1 Electrical Standards for DCC
Page 2 of 3
25
25
POWER STATION MAXIMUM
20
20
15
10
VOLTAGE
15
10
0
ZERO-CROSSING
+5uS
+10uS
ZERO-CROSSING
+5uS
+10uS
25
20
15
10
20
VOLTAGE
70
The baseline method for providing the power to operate locomotives and accessories, which shall be
supported by all Digital Command Stations and Digital Decoders, is by full-wave rectification of the
bipolar NMRA digital signal within the Digital Decoder7. In order to maintain power to the Digital
Decoders, gaps in bit transmission are only allowed at specified times (see S-9.2, Section C). The RMS
value of NMRA digital signal, measured at the track, shall not exceed by more than 2 volts8 the voltage
specified in standard S9 for the applicable scale9. In no case should the peak amplitude of the command
control signal exceed +/- 22 volts. The minimum peak value of the NMRA digital signal needed to provide
power to the decoder shall be +/-7 volts measured at the track. Digital Decoders intended for "N" and
smaller scales shall be designed to withstand a DC voltage of at least 24 volts as measured at the track.
Digital Decoders intended for scales larger than "N" shall be designed to withstand a DC voltage of at
least 27 volts as measured at the track.
VOLTAGE
65
VOLTAGE
60
15
10
DECODER MINIMUM
ZERO-CROSSING
+5uS
+10uS
ZERO-CROSSING
+5uS
+10uS
7 Alternate
means for supplying power are acceptable, provided that Digital Command Station power units
are capable of producing the baseline track signal, and Digital Decoders are capable of operation from the
baseline track signal as described by this standard.
8 The
additional voltage is to compensate for voltage drop in the Digital Decoder, to ensure that the
maximum voltage as specified in the NMRA Electrical Standard (S-9) is available at the motor brushes.
9
Care should be taken to ensure that any motors exposed directly to the digital signal for extended periods
have a stall rating that exceeds the amplitude of the signal, or sufficiently high impedance at 4-9 kHz to
reduce the current to normal operating level. This appears to only be a concern for high-precision core-less
can motors, which present a low impedance load, or for layouts using an NMRA digital signal with an
amplitude in excess of +-18 volts.
2001,2004 by the National Model Railroad Association, Inc.
S-9.1 Electrical Standards for DCC
Page 3 of 3
ANEXO 5
NMRA STANDARD
5
This Standard received approval from the NMRA
Membership and the Board of Trustees in January
1994, July 2002 and July 2004.
Communications Standards
For Digital Command Control,
All Scales
Adopted July 2004
10
15
S 9.2
This standard covers the format of the information sent via Digital Command Stations to Digital Decoders. A
Digital Command Station transmits this information to Digital Decoders by sending a series of bits using the
NMRA digital signal described in S-9.1. This sequence of bits, termed a packet, is used to encode one of a set of
instructions that the Digital Decoder operates upon. Packets must be precisely defined to ensure that the intended
instructions can be properly encoded and decoded.
20
Preamble:
The preamble to a packet consists of a sequence of "1" bits. A digital decoder must not
accept as a valid, any preamble that has less then 10 complete one bits, or require for
proper reception of a packet with more than 12 complete one bits. A command station
must send a minimum of 14 full preamble bits.
The packet start bit is the first bit with a value of "0" that follows a valid preamble. The
Packet Start Bit terminates the preamble and indicates that the next bits are an address
data byte.
The first data byte of the packet normally contains eight bits of address information2.
The first transmitted address bit shall be defined to be the most significant bit of the
address data byte. Address Data Bytes with values 00000000, 11111110, and 11111111
are reserved for special operations and must not be transmitted except as provided in this
Standard or associated Recommended Practices.
This bit precedes a data byte and has the value of "0".
Data Byte:
Each data byte contains eight bits of information used for address, instruction, data, or
error detection purposes. The first transmitted data bit of each data byte shall be defined
to be the most significant bit of the data byte. ]
This bit marks the termination of the packet and has a value of "1"3.
It is permissible for Digital Decoders to accept formats in addition to the NMRA General Packet Format. See
Section C for details.
2
The first byte can also be used in special cases to indicate instructions. See the Service Mode Recommended
Practice (RP-9.2.3) for an example of this dual use.
3
The Packet End Bit may count as one of the preamble bits of the subsequent packet if there are no inter-packet bits
from an alternative command control protocol. The DCC bitstream must continue for an additional 26 S
(minimum) after the packet end bit.
2001-2004, by the National Model Railroad Association, Inc.
S-9.2 Communications Standards for DCC
Page 1 of 4
Figure 1 provides an example of an acceptable command control packet that uses three data bytes: one address data
byte, one instruction data byte and one error detection data byte.
1 11 1 1 1 11 1 1 11 0
Preamble
Packet Start Bit
0 0 11 0 111 0
Address Data Byte
Data Byte Start Bit
0 11 1 0 1 0 0 0 0 1 0 0 0 0 11 1
Instruction Data Byte Error Detection Data Byte
Data Byte Start Bit
25
B: Baseline Packets
30
The Baseline Packets are included to provide the minimum interoperability between different systems. More
complex packet formats that support different types of decoders, additional functions, addresses and speeds are
provided in the Extended Packet Format Recommended Practice (RP-9.2.1). It is the intention of this Standard
that, in order to conform: a Command Station must encode operator control input in conformance with the Baseline
Packet semantics; and a Digital Decoder must recognize and provide suitable locomotive control electrical output in
conformance with the Baseline Packet semantics. Digital Decoder Idle Packets and Digital Decoder Broadcast Stop
Packets4 (defined below) are optional for Command Stations, and required for decoders.
35
0AAAAAAA 0 01DCSSSS 0
Byte One
Byte Two
EEEEEEEE 1
Byte Three (Error Detection Data Byte)
40
45
50
55
Byte One: Address Data Byte = 0AAAAAAA The address data byte contains the address of the intended recipient
of the packet. Every Digital Decoder shall be capable of retaining and recognizing its own address for
purposes of responding to Baseline Packets. Locomotive Digital Decoders shall support the full range of
baseline addresses in such a manner that this address is easily configurable by the user5. It is acceptable
for Digital Command Stations to restrict the number of valid addresses supported so long as this
restriction is clearly and plainly labeled on the package and in the instructions.
Byte Two: Instruction Data Byte = 01DCSSSS The instruction data byte is a data byte used to transmit speed and
direction information to the locomotive Digital Decoder. Bits 0-36 provides 4 bits for speed (S) with bit
0 being the least significant speed bit. Bit four of byte 2 (C) by default shall contain one additional speed
bit, which is the least significant speed bit. For backward compatibility, this bit may instead be used to
control the headlight. This optional use is defined in RP-9.2.1. Bit 5 provides one bit for direction (D).
When the direction bit (D) has a value of "1" the locomotive should move in the forward direction7. A
direction bit with the value of "0" should cause the locomotive to go in the reverse direction. Bits 7 and 6
contain the bit sequence "01"8 which are used to indicate that this instruction data byte is for speed and
direction.
4 Broadcast Stop Packet requirement for decoders, effective 1-Aug-2002.
5
The Service Mode Recommended Practice (RP-9.2.3) contains one example of an acceptable method for user address
configuration.
6
Bits within a byte are numbered right to left with bit 0 (the right most bit) being the least significant bit and bit 7
(the left most bit) being the most significant bit.
7
Forward in this case is in the direction of the front of the locomotive, as observed from the engineer's position
within the locomotive.
8
Other bit patterns in bits 7 and 6 are reserved for other types of instruction data, and are defined in the Extended
Packet Format Recommended Practice (RP-9.2.1).
2001-2004, by the National Model Railroad Association, Inc.
S-9.2 Communications Standards for DCC
Page 2 of 4
CS3S 2S 1S 0
Speed
CS3S 2S 1S 0
Speed
CS3S 2S 1S 0
Speed
CS3S 2S 1S 0
Speed
00000
10000
00001
10001
00010
10010
00011
10011
Stop
Stop (I)
E-Stop*
E-Stop* (I)
Step 1
Step 2
Step 3
Step 4
00100
10100
00101
10101
00110
10110
00111
10111
Step 5
Step 6
Step 7
Step 8
Step 9
Step 10
Step 11
Step 12
01000
11000
01001
11001
01010
11010
01011
11011
Step 13
Step 14
Step 15
Step 16
Step 17
Step 18
Step 19
Step 20
01100
11100
01101
11101
01110
11110
01111
11111
Step 21
Step 22
Step 23
Step 24
Step 25
Step 26
Step 27
Step 28
60
65
Byte Three: Error Detection Data Byte = EEEEEEEE The error detection data byte is a data byte used to detect the
presence of transmission errors. The contents of the Error Detection Data Byte shall be the bitwise
exclusive OR of the contents of the Address Data Byte and the Instruction Data Byte in the packet
concerned. (e.g. the exclusive OR of bit 0 of the address data byte and bit 0 of the instruction data byte
will be placed in bit 0 of the error detection data byte...) Digital Decoders receiving a Baseline Packet
shall compare the received error detection data byte with the bitwise exclusive OR of the received address
and instruction data bytes and ignore the contents of the packet if this comparison is not identical.
70
The example packet shown in figure 1 illustrates a baseline packet with the instruction to locomotive 55 to proceed
in the forward direction at speed step 6.
111111111111 000000000 0
Preamble
Byte One
80
85
00000000 0
Byte Two
00000000 1
Byte Three (Error Detection Data Byte)
A three byte packet, where all eight bits within each of the three bytes contains the value of "0", is defined as a
Digital Decoder Reset Packet. When a Digital Decoder receives a Digital Decoder Reset Packet, it shall erase all
volatile memory (including any speed and direction data), and return to its normal power-up state. If the Digital
Decoder is operating a locomotive at a non-zero speed when it receives a Digital Decoder Reset, it shall bring the
locomotive to an immediate stop.
Following a Digital Decoder Reset Packet, a Command Station shall not send any packets with an address data byte
between the range "01100100" and "01111111" inclusive within 20 milliseconds, unless it is the intent to enter
service mode9.
111111111111 0
11111111 0
00000000 0
11111111 1
Preamble
Byte One
Byte Two
Byte Three (Error Detection Data Byte)
95
A three byte packet, whose first byte contains eight "1"s, whose second byte contains eight "0"s and whose third
and final byte contains eight "1"s, is defined as a Digital Decoder Idle Packet. Upon receiving this packet, Digital
Decoders shall perform no new action, but shall act upon this packet as if it were a normal digital packet addressed
to some other decoder.
Digital Decoders can have their configurations altered immediately after a digital decoder reset packet. See the
Service Mode Recommended Practice(RP-9.2.3) for details.
2001-2004, by the National Model Railroad Association, Inc.
S-9.2 Communications Standards for DCC
Page 3 of 4
105
110
Byte One
Byte Two
A three byte packet, whose first byte contains eight "0"s, whose second byte contains a specific stop command and
whose third and final byte contains an error byte that is identical to the second byte of the packet, is defined as a
Digital Decoder Broadcast Stop Packet. Upon receiving this packet where bit zero of byte two (S) contains a value
of "0", digital decoders intended to control a locomotive's motor shall bring the locomotive to a stop.
Upon receiving this packet where bit zero of byte two (S) contains a value of "1", digital decoders intended to
control a locomotive's motor shall stop delivering energy to the motor. If bit four of byte 2 (C) contains a value of
"1", the direction bit contained in bit five of byte 2 (D) may optionally be ignored for all direction sensitive
functions.
120
125
130
Packets sent to Digital Decoders should be repeated as frequently as possible, as a packet may have been lost due to
noise or poor electrical conductivity between wheels and rails. Power may also be removed from the rails between
the Packet End Bit and the Preamble of the next packet to allow for alternative command control formats. A Digital
Decoder shall be able to act upon multiple packets addressed to it, provided the time between the packet end bit of
the first packet and the packet start bit of the second packet are separated by at least 5 milliseconds11. If a decoder
receives a bit sequence with a missing or invalid data byte start bit, a missing or invalid packet end bit, or an
incorrect error detection byte, it must recognize the next valid preamble sequence as the beginning of a new packet.
Alternative command control formats are specifically allowed between the packet end bit and the start of the next
preamble.
Manufacturers of decoders are encouraged to provide automatic conversion for a variety of power signals and
command control formats in addition to the NMRA digital signal (per S-9.1), provided that automatic conversion
to these alternate power signals can be disabled. If automatic conversion is enabled, Digital Decoders must remain
in digital mode and not convert to using any alternate power signal so long as the time between Packet Start Bits is
less than or equal to 30 milliseconds in duration. If automatic conversion is disabled, Digital Decoders must
remain in digital mode regardless of the timing of Packet Start Bits. It shall be possible to configure Digital
Command Stations to transmit at least one complete packet every 30 milliseconds as measured from the time
between packet start bits12. 13
Care must be taken to ensure that two packets with identical addresses are not are not transmitted within 5
milliseconds of each other for addresses in the range between 112-127 as older decoders may interpret these packets as
service mode packets (see RP-9.2.3).
12
Some DCC decoders manufactured prior to the NMRA standards require a valid baseline packet be received every
30 milliseconds to prevent analog power conversion.
13
Longer repetition rates may result in less than optimal decoder performance
ANEXO 6
Selective Photodiode
EPD-740-5
Spectral range
Type
Technology
Case
Infrared
EPD-740-5
AlGaAs/AlGaAs/GaAs
5 mm plastic lens
Description
Applications
Optical communications,
safety equipment
7,1 - 0,6
2,54
5,3 - 0,3
0,8 - 0,4
Anode
1,7 - 0,1
6,2 - 0,5
1,1 - 0,1
2
10,6 - 0,6
16,5 - 2,0
0,7 - 0,4
Maximum Ratings
Parameter
Value
Unit
Storage Temperature
- 40...+90
Operating Temperature
Soldering Temperature
-40...+85
240
C
C
Test conditions
Active area
Symbol
Min
Peak sensitivity
Smax
0,5
Typ
Max
mm2
0.13
700
740
Unit
780
nm
60
nm
40
deg.
Responsivity at 740 nm
VR = 0 V
0.5
A/W
Short-circuit current*
VR = 0, Ee=1
mW/cm
ISC
Dark current
VR = 5 V, Ee=0
ID
40
Reverse voltage
IR = 10 A
VR
10
Junction capacitance
VR = 0, Ee=0
40
pF
Rise time
RL = 50
tr
15
Fall time
VR = 5 V
tf
30
200
Parameter
Test conditions Symbol
Min
Typ
Max
*Light source is an AlGaAs LED with a peak emission wavelength of 740 nm
pA
ns
Unit
rev.04/01
GENERAL DESCRIPTION
APPLICATIONS
ADXL320
CDC
AC
AMP
DEMOD
OUTPUT
AMP
OUTPUT
AMP
SENSOR
COM
ST
RFILT
32k
YOUT
CY
XOUT
CX
04993-001
RFILT
32k
Figure 1.
Rev.0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
ADXL320
TABLE OF CONTENTS
Specifications..................................................................................... 3
Self-Test ....................................................................................... 12
ESD Caution.................................................................................. 4
REVISION HISTORY
9/04Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADXL320
SPECIFICATIONS 1
TA = 25C, VS = 3 V, CX = CY = 0.1 F, Acceleration = 0 g, unless otherwise noted.
Table 1.
Parameter
SENSOR INPUT
Measurement Range
Nonlinearity
Package Alignment Error
Alignment Error
Cross Axis Sensitivity
SENSITIVITY (RATIOMETRIC) 2
Sensitivity at XOUT, YOUT
Sensitivity Change due to Temperature 3
ZERO g BIAS LEVEL (RATIOMETRIC)
0 g Voltage at XOUT, YOUT
0 g Offset Versus Temperature
NOISE PERFORMANCE
Noise Density
FREQUENCY RESPONSE 4
CX, CY Range 5
RFILT Tolerance
Sensor Resonant Frequency
SELF-TEST 6
Logic Input Low
Logic Input High
ST Input Resistance to Ground
Output Change at XOUT, YOUT
OUTPUT AMPLIFIER
Output Swing Low
Output Swing High
POWER SUPPLY
Operating Voltage Range
Quiescent Supply Current
Turn-On Time 7
TEMPERATURE
Operating Temperature Range
Conditions
Each axis
Min
Max
X sensor to Y sensor
Unit
g
%
Degrees
Degrees
%
5
0.2
1
0.1
2
% of full scale
Each axis
VS = 3 V
VS = 3 V
Each axis
VS = 3 V
Typ
156
174
0.01
192
mV/g
%/C
1.3
1.5
0.6
1.7
V
mg/C
@ 25C
250
0.002
g/Hz rms
32 15%
5.5
10
F
k
kHz
Self-test 0 to 1
0.6
2.4
50
55
V
V
k
mV
No load
No load
0.3
2.5
V
V
2.4
5.25
V
mA
ms
70
0.48
20
20
All minimum and maximum specifications are guaranteed. Typical specifications are not guaranteed.
Sensitivity is essentially ratiometric to VS. For VS = 2.7 V to 3.3 V, sensitivity is 154 mV/V/g to 194 mV/V/g typical.
3
Defined as the output change from ambient-to-maximum temperature or ambient-to-minimum temperature.
4
Actual frequency response controlled by user-supplied external capacitor (CX, CY).
5
Bandwidth = 1/(2 32 k C). For CX, CY = 0.002 F, bandwidth = 2500 Hz. For CX, CY = 10 F, bandwidth = 0.5 Hz. Minimum/maximum values are not tested.
6
Self-test response changes cubically with VS.
7
Larger values of CX, CY increase turn-on time. Turn-on time is approximately 160 CX or CY + 4 ms, where CX, CY are in F.
2
Rev. 0 | Page 3 of 16
ADXL320
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Acceleration (Any Axis, Unpowered)
Acceleration (Any Axis, Powered)
VS
All Other Pins
Output Short-Circuit Duration
(Any Pin to Common)
Operating Temperature Range
Storage Temperature
Rating
10,000 g
10,000 g
0.3 V to +7.0 V
(COM 0.3 V) to
(VS + 0.3 V)
Indefinite
55C to +125C
65C to +150C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 4 of 16
ADXL320
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC
VS
VS
NC
NC
XOUT
ST
ADXL320
NC
COM
TOP VIEW
(Not to Scale)
YOUT
NC
NC
NC = NO CONNECT
04993-022
NC
Mnemonic
NC
ST
COM
NC
COM
COM
COM
NC
NC
YOUT
NC
XOUT
NC
VS
VS
NC
Description
Do Not Connect
Self-Test
Common
Do Not Connect
Common
Common
Common
Do Not Connect
Do Not Connect
Y Channel Output
Do Not Connect
X Channel Output
Do Not Connect
2.4 V to 5.25 V
2.4 V to 5.25 V
Do Not Connect
Rev. 0 | Page 5 of 16
ADXL320
CRITICAL ZONE
TL TO TP
tP
TP
TEMPERATURE
RAMP-UP
TL
tL
TSMAX
TSMIN
tS
RAMP-DOWN
04993-002
PREHEAT
t25C TO PEAK
TIME
Rev. 0 | Page 6 of 16
Sn63/Pb37
3C/second max
Pb-Free
3C/second max
100C
150C
60 120 seconds
150C
200C
60 150 seconds
3C/second
3C/second
183C
60 150 seconds
240C + 0C/5C
10 30 seconds
6C/second max
6 minutes max
217C
60 150 seconds
260C + 0C/5C
20 40 seconds
6C/second max
8 minutes max
ADXL320
25
25
20
20
% OF POPULATION
15
10
04993-006
1.40 1.42 1.44 1.46 1.48 1.50 1.52 1.54 1.56 1.58 1.60
1.40 1.42 1.44 1.46 1.48 1.50 1.52 1.54 1.56 1.58 1.60
OUTPUT (V)
OUTPUT (V)
35
35
30
30
25
25
% OF POPULATION
% OF POPULATION
10
5
04993-003
15
20
15
10
0
2.82.4 2.0 1.61.2 0.8 0.4 0
15
10
5
04993-004
20
04993-007
% OF POPULATION
90
70
80
60
70
% OF POPULATION
50
40
30
40
30
20
20
10
0
164
166
168
170
172
174
176
178
180
182
04993-008
10
04993-005
% OF POPULATION
50
60
0
164
184
SENSITIVITY (mV/g)
166
168
170
172
174
176
178
180
SENSITIVITY (mV/g)
Rev. 0 | Page 7 of 16
182
184
ADXL320
1.54
0.180
0.179
1.53
0.177
SENSITIVITY (V/g)
1.51
1.50
1.49
0.176
0.175
0.174
0.173
1.48
0.172
1.46
30
04993-009
1.47
20
10
10
20
30
40
50
60
70
04993-012
0.178
1.52
0.171
0.170
30
80
20
10
10
TEMPERATURE (C)
20
30
40
50
60
70
80
TEMPERATURE (C)
35
30
30
25
% OF POPULATION
20
15
10
20
15
10
5
04993-010
0
170
190
210
230
250
270
290
310
330
04993-013
% OF POPULATION
25
0
170
350
190
210
230
NOISE ug/ Hz
270
290
310
330
350
25
30
25
% OF POPULATION
20
15
10
20
15
10
0
5
04993-014
5
04993-011
% OF POPULATION
250
NOISE ug/ Hz
0
5
Rev. 0 | Page 8 of 16
60
60
50
50
% OF POPULATION
40
30
20
30
20
10
04993-015
10
40
0
35
40
45
50
55
60
65
70
04993-017
% OF POPULATION
ADXL320
75
35
SELF-TEST (mV)
40
45
50
55
60
65
70
75
SELF-TEST (mV)
40
35
25
20
15
04993-020
10
04993-016
% OF POPULATION
30
0
420 430 440 450 460 470 480 490 500 510 520 530
CURRENT (A)
Rev. 0 | Page 9 of 16
ADXL320
XL
320J
#1234
5678P
YOUT = 1.500V
XOUT = 1.500V
YOUT = 1.326V
XOUT = 1.674V
YOUT = 1.50V
XOUT = 1.500V
YOUT = 1.500V
EARTH'S SURFACE
Rev. 0 | Page 10 of 16
04993-018
YOUT = 1.674V
XOUT = 1.326V
XL
320J
#1234
5678P
XOUT = 1.500V
XL
320J
#1234
5678P
XL
320J
#1234
5678P
ADXL320
THEORY OF OPERATION
The ADXL320 is a complete acceleration measurement system
on a single monolithic IC. The ADXL320 has a measurement
range of 5 g. It contains a polysilicon surface-micromachined
sensor and signal conditioning circuitry to implement an openloop acceleration measurement architecture. The output signals
are analog voltages that are proportional to acceleration. The
accelerometer measures static acceleration forces, such as
gravity, which allows it to be used as a tilt sensor.
The sensor is a polysilicon surface-micromachined structure
built on top of a silicon wafer. Polysilicon springs suspend the
structure over the surface of the wafer and provide a resistance
against acceleration forces. Deflection of the structure is
measured using a differential capacitor that consists of
independent fixed plates and plates attached to the moving
mass. The fixed plates are driven by 180 out-of-phase square
waves. Acceleration deflects the beam and unbalances the
differential capacitor, resulting in an output square wave whose
amplitude is proportional to acceleration. Phase-sensitive
demodulation techniques are then used to rectify the signal and
determine the direction of the acceleration.
PERFORMANCE
Rather than using additional temperature compensation
circuitry, innovative design techniques have been used to ensure
high performance is built-in. As a result, there is neither
quantization error nor nonmonotonic behavior, and
temperature hysteresis is very low (typically less than 3 mg over
the 20C to +70C temperature range).
Figure 10 shows the zero g output performance of eight parts
(X- and Y-axis) over a 20C to +70C temperature range.
Figure 13 demonstrates the typical sensitivity shift over
temperature for supply voltages of 3 V. This is typically better
than 1% over the 20C to +70C temperature range.
Rev. 0 | Page 11 of 16
ADXL320
APPLICATIONS
POWER SUPPLY DECOUPLING
For most applications, a single 0.1 F capacitor, CDC, adequately
decouples the accelerometer from noise on the power supply.
However, in some cases, particularly where noise is present at
the 140 kHz internal clock frequency (or any harmonic
thereof), noise on the supply may cause interference on the
ADXL320 output. If additional decoupling is needed, a 100
(or smaller) resistor or ferrite bead may be inserted in the
supply line. Additionally, a larger bulk bypass capacitor (in the
1 F to 4.7 F range) may be added in parallel to CDC.
Capacitor (F)
4.7
0.47
0.10
0.05
0.027
0.01
SELF-TEST
The ST pin controls the self-test feature. When this pin is set to
VS, an electrostatic force is exerted on the accelerometer beam.
The resulting movement of the beam allows the user to test if
the accelerometer is functional. The typical change in output is
315 mg (corresponding to 55 mV). This pin may be left opencircuit or connected to common (COM) in normal use.
Peak-to-Peak Value
2 rms
4 rms
6 rms
8 rms
Rev. 0 | Page 12 of 16
ADXL320
Peak-to-peak noise values give the best estimate of the
uncertainty in a single measurement. Table 7 gives the typical
noise output of the ADXL320 for various CX and CY values.
Table 7. Filter Capacitor Selection (CX, CY)
Bandwidth
(Hz)
10
50
100
500
CX, CY
(F)
0.47
0.1
0.047
0.01
RMS Noise
(mg)
1.0
2.25
3.2
7.1
Peak-to-Peak Noise
Estimate (mg)
6
13.5
18.9
42.8
Rev. 0 | Page 13 of 16
ADXL320
OUTLINE DIMENSIONS
0.20 MIN
PIN 1
INDICATOR
0.20 MIN
13
PIN 1
INDICATOR
4.15
4.00 SQ
3.85
0.65 BSC
TOP
VIEW
16
1
12
2.43
1.75 SQ
1.08
BOTTOM
VIEW
9
4
8
0.55
0.50
0.45
1.95 BSC
0.05 MAX
0.02 NOM
SEATING
PLANE
0.35
0.30
0.25
COPLANARITY
0.05
072606-A
1.50
1.45
1.40
ORDERING GUIDE
Model
ADXL320JCP 1
ADXL320JCPREEL1
ADXL320JCPREEL71
ADXL320EB
Measurement
Range
5 g
5 g
5 g
Specified
Voltage (V)
3
3
3
Temperature
Range
20C to +70C
20C to +70C
20C to +70C
Rev. 0 | Page 14 of 16
Package Description
16-Lead LFCSP_LQ
16-Lead LFCSP_LQ
16-Lead LFCSP_LQ
Evaluation Board
Package
Option
CP-16-5a
CP-16-5a
CP-16-5a
IL74
DUAL CHANNEL ILD74
QUAD CHANNEL ILQ74
SINGLE CHANNEL
PHOTOTRANSISTOR OPTOCOUPLER
FEATURES
7400 Series T2L Compatible
Transfer Ratio, 35% Typical
Coupling Capacitance, 0.5 pF
Single, Dual, & Quad Channel
Industry Standard DIP Package
Underwriters Lab File #E52744
V
The IL74 is an optically coupled pair with a Gallium Arsenide infrared LED and a silicon NPN
phototransistor. Signal information, including a
DC level, can be transmitted by the device while
maintaining a high degree of electrical isolation
between input and output. The IL74 is especially
designed for driving medium-speed logic, where
it may be used to eliminate troublesome gound
loop and noise problems. Also it can be used to
replace relays and transformers in many digital
interface applications, as well as analog applications such as CRT modulation.
1
6 Base
Anode 1
.248 (6.30)
.256 (6.50)
5 Collector
Cathode 2
4
4 Emitter
NC 3
.335 (8.50)
.343 (8.70)
D E
DESCRIPTION
.300 (7.62)
typ.
.039
(1.00)
min.
.130 (3.30)
.150 (3.81)
4
typ.
18 typ.
.020 (.051) min.
.031 (0.80)
.035 (0.90)
.018 (0.45)
.022 (0.55)
.300 (7.62)
.347 (8.82)
.268 (6.81)
.255 (6.48)
5
.110 (2.79)
.150 (3.81)
.010 (.25)
.014 (.35)
Anode
8 Emitter
Cathode
7 Collector
Cathode
6 Collector
Anode
5 Emitter
.390 (9.91)
.379 (9.63)
.305 typ.
(7.75) typ.
4
Typ.
.040 (1.02)
.030 (.76 )
.022 (.56)
.018 (.46)
39
10
Typ.
.135 (3.43)
.115 (2.92)
.012 (.30)
.008 (.20)
Anode 1
.240 (6.10)
.260 (6.60)
9
10
11
12
13
14
15
.780 (19.81)
.800 (20.32)
.040 (1.02)
.050 (1.27)
.048 (1.22)
.052 (1.32)
51
Cathode 2
15 Collector
Cathode 3
14 Collector
pin one
ID. Anode 4
13 Emitter
Anode 5
12 Emitter
Cathode 6
11 Collector
Cathode
10 Collector
Anode 8
Emitter
.300 (7.62)
typ.
.034 (.86)
.130 (3.30)
.150 (3.81)
.280 (7.11)
.330 (8.38)
.014
(.35)
typ.
.016 (.41)
.020 (.51)
16
16 Emitter
.033 (.84)
typ.
.020 (.51)
.030 (.76)
.0255 (.65)
typ.
.100 (2.54) typ.
.130 (3.30)
.150 (3.81)
3 to 9
.008 (.20)
.012 (.31)
Maximum Ratings
VF - Forward Voltage - V
1.0
0.9
Ta = 85C
0.8
0.7
1.0
0.5
NCTR(SAT)
NCTR
VF
1.3
1.5
IF=20 mA
Reverse Current
IR
0.1
100
VR=3.0 V
Capacitance
CO
25
pF
VR=0
Emitter
Detector
50
Leakage Current,
Collector-Emitter
ICEO
5.0
Capacitance,
Collector-Emitter
CCE
10.0
500
1.5
Condition
BVCEO
IC=1 mA
nA
VCE=5 V,
IF=0
pF
VCE=0,
F=1 MHz
1.0
100
Ta = 50C
0.5
NCTR(SAT)
NCTR
0.0
.1
CTRDC
Saturation Voltage,
Collector-Emitter
VCEsat
0.3
Resistance, Input
to Output
RIO
100
Capacitance, Input
to Output
CIO
0.5
pF
Switching Times
tON,tOFF
3.0
0.5
V
IF=16 mA,
VCE=5 V
IC=2 mA,
IF=16 mA
100
Normalized to:
Vce = 10V, IF = 10mA
Ta = 25C
1.0
0.5
Ta = 70C
NCTR(SAT)
NCTR
0.0
RE=100 ,
VCE=10 V,
IC=2 mA
1
10
IF - LED Current - mA
35
1
10
IF - LED Current - mA
Normalized to:
Vce = 10V, IF = 10mA, Ta = 25C
CTRce(sat) Vce = 0.4V
1.5
Package
12.5
100
Breakdown
Voltage,
Collector-Emitter
1
10
IF - Forward Current - mA
Normalized to:
Vce = 10V, IF = 10mA
Ta = 25C
0.0
.1
Max.
20
Ta = 25C
1.1
1.5
Typ.
Forward Voltage
1.2
Ta = -55C
.1
Package
Isolation Test Voltage (t=1 sec.) ........ 5300 VACRMS
Isolation Resistance
VIO=500 V, TA=25C ............................... 1012
VIO=500 V, TA=100C ............................. 1011
Total Package Dissipation
at 25C Ambient (LED Plus Detector)
IL74.........................................................200 mW
ILD74 ......................................................400 mW
IL74Q ......................................................500 mW
Derate Linearly from 25C
IL74.....................................................2.7 mW/C
ILD74 ................................................5.33 mW/C
ILQ74 ................................................6.67 mW/C
Creepage ............................................... 7 mm min.
Clearance............................................... 7 mm min.
Storage Temperature ...................55C to +150C
Operating Temperature ...............55C to +100C
Lead Soldering Time at 260C .................... 10 sec.
Symbol
1.3
.1
1
10
IF - LED Current - mA
100
IL/ILD/ILQ74
52
Normalized to:
Vce = 10V, IF = 10mA, Ta = 25C
CTRce(sat) Vce = 0.4V
1.0
0.5
Ta = 85C
NCTR(SAT)
NCTR
0.0
.1
1
10
IF - LED Current - mA
100
10
1
.1
.01
100
.1
100
1
10
IF - LED Current - mA
10
35
Normalized to:
30
25
Normalized Photocurrent
Ta = 25C
1.5
50C
20
15
70C
25C
85C
10
5
0
0
10
20
30
40
IF - LED Current - mA
50
If = 10ma, Ta = 25C
1
NIB-Ta=-20C
.1
NIb,Ta=25C
NIb,Ta=50C
NIb,Ta=70C
60
.01
.1
100
10
If LED Current mA
5
10
4
10
3
10
10 2
10
10
1.2
NHFE - Normalized HFE
Iceo - Collector-Emitter - nA
Vce = 10V
TYPICAL
10 -1
10 -2
-20
70C
50C
1.0
-20C
0.8
0.6
0.4
1
0
20
40
60
80
100
Ta - Ambient Temperature - C
10
100
Ib - Base Current - A
1000
1.5
1.5
Normalized to:
IF =10 mA
Vcb = 9.3 V
Ta = 25C
1.0
0.5
NHFE(sat) - Normalized
Saturated HFE
25C
Normalized to:
Ib = 20A
Vce = 10 V
Ta = 25C
25C
50C
70C
0.0
.1
1
10
IF - LED Current - mA
100
70C
1.0
50C
25C
Normalized to:
Vce = 10V
Ib = 20A
Ta = 25C
-20C
0.5
Vce = 0.4V
0.0
1
10
100
Ib - Base Current - (A)
1000
IL/ILD/ILQ74
53
2.5
tpHL
100
2.0
1.5
10
tpLH
1
1.0
.1
10
1000
tpLH - Propagation Delay - s
Ta = 25C, IF = 10mA
Vcc = 5 V, Vth = 1.5 V
1000
100
2.5
Ta = 25C, IF = 10mA
Vcc = 5 V, Vth = 1.5 V
tpHL
100
2.0
1.5
10
tpLH
1
1.0
.1
1
10
RL - Collector Load Resistor - K
100
IL/ILD/ILQ74
54
L298
..
..
.
DESCRIPTION
The L298 is an integrated monolithic circuit in a 15lead Multiwatt and PowerSO20 packages. It is a
high voltage, high current dual full-bridge driver designed to accept standard TTL logic levels and drive
inductive loads such as relays, solenoids, DC and
stepping motors. Two enable inputs are provided to
enable or disable the device independently of the input signals. The emitters of the lower transistors of
each bridge are connected together and the corresponding external terminal can be used for the con-
Multiwatt15
PowerSO20
BLOCK DIAGRAM
Jenuary 2000
1/13
L298
ABSOLUTE MAXIMUM RATINGS
Symbol
VS
VSS
VI,Ven
IO
Vsens
Value
Unit
Power Supply
Parameter
50
0.3 to 7
3
2.5
2
A
A
A
1 to 2.3
25
25 to 130
40 to 150
Ptot
Top
Tstg, Tj
Multiwatt15
15
CURRENT SENSING B
14
OUTPUT 4
13
OUTPUT 3
12
INPUT 4
11
ENABLE B
10
INPUT 3
GND
INPUT 2
ENABLE A
INPUT 1
SUPPLY VOLTAGE VS
OUTPUT 2
OUTPUT 1
CURRENT SENSING A
D95IN240A
GND
20
GND
Sense A
19
Sense B
N.C.
18
N.C.
Out 1
Out 2
PowerSO20
17
Out 4
16
Out 3
VS
15
Input 4
Input 1
14
Enable B
Enable A
13
Input 3
Input 2
12
VSS
10
11
GND
GND
D95IN239
THERMAL DATA
Symbol
Parameter
PowerSO20
Multiwatt15
Unit
Rth j-case
Max.
C/W
Rth j-amb
Max.
13 (*)
35
C/W
2/13
L298
PIN FUNCTIONS (refer to the block diagram)
MW.15
PowerSO
Name
1;15
2;19
Sense A; Sense B
Function
2;3
4;5
Out 1; Out 2
VS
5;7
7;9
Input 1; Input 2
6;11
8;14
Enable A; Enable B
1,10,11,20
GND
12
VSS
10; 12
13;15
Input 3; Input 4
13; 14
16;17
Out 3; Out 4
3;18
N.C.
ELECTRICAL CHARACTERISTICS (VS = 42V; VSS = 5V, Tj = 25C; unless otherwise specified)
Symbol
Parameter
Test Conditions
Operative Condition
IS
Ven = H; IL = 0
ISS
Ven = L
Quiescent Current from VSS (pin 9) Ven = H; IL = 0
VS
VSS
ViH
IiL
IiH
Ven = L
Ven = H
Ien = L
Ien = H
VCEsat (H)
Total Drop
Vsens
Max.
Unit
46
5
13
50
7
22
70
V
mA
mA
24
7
4
36
12
mA
mA
mA
0.3
6
1.5
mA
V
2.3
VSS
10
100
4.5
Ven = L
ViL
Min.
Typ.
VIH +2.5
Vi = L
Vi = H
Vi = X
Vi = L
Vi = H
Vi = X
Vi = L
Vi = H VSS 0.6V
30
0.3
1.5
2.3
VSS
10
V
A
30
100
1.35
2
1.2
1.7
1.7
2.7
1.6
2.3
3.2
4.9
V
V
V
V
V
V
Ven = L
Ven = H VSS 0.6V
IL = 1A
IL = 2A
IL = 1A
IL = 2A
IL = 1A
IL = 2A
0.95
(5)
(5)
(5)
(5)
0.85
1.80
1 (1)
3/13
L298
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
(2); (4)
1.5
0.9 IL to 0.1 IL
(2); (4)
0.2
0.5 Vi to 0.1 IL
(2); (4)
0.1 IL to 0.9 IL
(2); (4)
0.7
T5 (Vi)
0.5 Vi to 0.9 IL
(3); (4)
0.7
T6 (Vi)
0.9 IL to 0.1 IL
(3); (4)
0.25
T7 (Vi)
0.5 Vi to 0.9 IL
(3); (4)
1.6
T8 (Vi)
0.1 IL to 0.9 IL
(3); (4)
0.2
T1 (Vi)
0.5 Vi to 0.9 IL
T2 (Vi)
T3 (Vi)
T4 (Vi)
Commutation Frequency
IL = 2A
T1 (Ven)
fc (Vi)
25
T2 (Ven)
0.9 IL to 0.1 IL
T3 (Ven)
T4 (Ven)
0.1 IL to 0.9 IL
T5 (Ven)
T6 (Ven)
0.9 IL to 0.1 IL
T7 (Ven)
T8 (Ven)
0.1 IL to 0.9 IL
(2); (4)
(2); (4)
(2); (4)
(2); (4)
(3); (4)
(3); (4)
(3); (4)
(3); (4)
40
0.3
0.4
2.2
0.35
0.25
0.1
1) 1)Sensing voltage can be 1 V for t 50 sec; in steady state Vsens min 0.5 V.
2) See fig. 2.
3) See fig. 4.
4) The load must be a pure resistor.
4/13
KHz
L298
Figure 3 : Source Current Delay Times vs. Input or Enable Switching.
5/13
L298
Figure 5 : Sink Current Delay Times vs. Input 0 V Enable Switching.
Inputs
Ven = H
Ven = L
L = Low
6/13
C=H;D=L
C=L;D=H
C=D
C=X;D=X
H = High
Function
Forward
Reverse
Fast Motor Stop
Free Running
Motor Stop
X = Dont care
L298
Figure 7 : For higher currents, outputs can be paralleled. Take care to parallel channel 1 with channel 4
and channel 2 with channel 3.
L298
This solution can drive until 3 Amps In DC operation
and until 3.5 Amps of a repetitive peak current.
On Fig 8 it is shown the driving of a two phase bipolar
stepper motor ; the needed signals to drive the inputs of the L298 are generated, in this example,
from the IC L297.
Fig 9 shows an example of P.C.B. designed for the
application of Fig 8.
8/13
VF 1.2 V @ I = 2 A
trr 200 ns
L298
Figure 9 : Suggested Printed Circuit Board Layout for the Circuit of fig. 8 (1:1 scale).
Figure 10 : Two Phase Bipolar Stepper Motor Control Circuit by Using the Current Controller L6506.
9/13
L298
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
0.197
2.65
0.104
1.6
0.063
0.039
0.49
0.55
0.019
0.022
0.66
0.75
0.026
0.030
1.02
1.27
1.52
0.040
0.050
0.060
G1
17.53
17.78
18.03
0.690
0.700
0.710
H1
19.6
0.772
H2
20.2
0.795
21.9
22.2
22.5
0.862
0.874
0.886
L1
21.7
22.1
22.5
0.854
0.870
0.886
L2
17.65
18.1
0.695
L3
17.25
17.5
17.75
0.679
0.689
0.699
L4
10.3
10.7
10.9
0.406
0.421
0.429
L7
2.65
2.9
0.104
0.713
0.114
4.25
4.55
4.85
0.167
0.179
0.191
M1
4.63
5.08
5.53
0.182
0.200
0.218
1.9
2.6
0.075
S1
1.9
2.6
0.075
0.102
Dia1
3.65
3.85
0.144
0.152
10/13
OUTLINE AND
MECHANICAL DATA
0.102
Multiwatt15 V
L298
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
0.197
2.65
0.104
1.6
0.063
0.49
0.55
0.019
0.022
0.66
0.75
0.026
0.030
1.14
1.27
1.4
0.045
0.050
0.055
G1
17.57
17.78
17.91
0.692
0.700
0.705
H1
19.6
0.772
H2
20.2
0.795
20.57
0.810
L1
18.03
0.710
L2
2.54
L3
17.25
L4
10.3
L5
0.100
17.5
17.75
0.679
0.689
0.699
10.7
10.9
0.406
0.421
0.429
5.28
L6
OUTLINE AND
MECHANICAL DATA
0.208
2.38
0.094
L7
2.65
2.9
0.104
0.114
1.9
2.6
0.075
0.102
S1
1.9
2.6
0.075
0.102
Dia1
3.65
3.85
0.144
0.152
Multiwatt15 H
11/13
L298
DIM.
A
a1
a2
a3
b
c
D (1)
D1
E
e
e3
E1 (1)
E2
E3
G
H
h
L
N
S
T
MIN.
mm
TYP.
0.1
0
0.4
0.23
15.8
9.4
13.9
MAX.
3.6
0.3
3.3
0.1
0.53
0.32
16
9.8
14.5
MIN.
0.004
0.000
0.016
0.009
0.622
0.370
0.547
1.27
11.43
10.9
inch
TYP.
0.050
0.450
11.1 0.429
2.9
6.2
0.228
0.1
0.000
15.9 0.610
1.1
1.1
0.031
10 (max.)
8 (max.)
5.8
0
15.5
0.8
OUTLINE AND
MECHANICAL DATA
MAX.
0.142
0.012
0.130
0.004
0.021
0.013
0.630
0.386
0.570
10
0.437
0.114
0.244
0.004
0.626
0.043
0.043
JEDEC MO-166
0.394
PowerSO20
N
a2
b
DETAIL A
c
a1
DETAIL B
e3
H
DETAIL A
lead
slug
a3
DETAIL B
20
11
0.35
Gage Plane
-C-
SEATING PLANE
E2
E1
BOTTOM VIEW
T
E3
1
h x 45
12/13
10
PSO20MEC
(COPLANARITY)
D1
II.- PLANOS
PLANOS
II.- PLANOS
1. Lista de Planos
2. Esquemticos
3. Circuitos Impresos
3.1. Circuito Integrado
3.2. Mscara de soldadura
3.3. Serigrafa
PLANOS
1. Lista de Planos
PLANOS
2. Esquemticos
PLANOS
3. Circuitos Impresos
III.- PLIEGO DE
CONDICIONES
CONDICIONES
1. Generales y Econmicas
2. Tcnicas y particulares
CONDICIONES
Generales y econmicas
1. Generales y Econmicas
1.1. CONDICIONES GENERALES
Las condiciones y clusulas que se establecen en este documento
tratan de la contratacin, por parte de persona fsica o jurdica, del
hardware (tarjeta) y el software incorporado a la misma, que ha sido
desarrollado en este proyecto.
1.
2.
3.
4.
CONDICIONES
5.
Generales y econmicas
El plazo de entrega ser de tres semanas a partir de la fecha de
la firma del contrato.
6.
7.
8.
9.
10.
CONDICIONES
Generales y econmicas
Los precios indicados en este proyecto son firmes y sin revisin por
ningn concepto, siempre y cuando se acepten dentro del perodo de
validez posteriormente indicado. El perodo de validez del presupuesto es
hasta el mes de Diciembre de 2008.
CONDICIONES
Tcnicas y particulares
2. Tcnicas y particulares
2.1. CIRCUITO IMPRESO
El tipo de soporte aislante usado ser de fibra de vidrio impregnada con resina
epoxi para dar rigidez. Se recomiendan las siguientes caractersticas para el
soporte aislante:
CONDICIONES
Tcnicas y particulares
Los dimetros recomendados para los pads de los distintos componentes son
los que se muestran a continuacin:
CONDICIONES
Tcnicas y particulares
Los dimetros recomendados para los taladros son los que se muestran a
continuacin:
CONDICIONES
2.7. OTROS CRITERIOS DE DISEO
Tcnicas y particulares
- Una vez montada y comprobada la tarjeta del circuito impreso, se aplicar sobre
ella una capa de barniz para efectuar la tropicalizacin de la misma, y evitar as
los defectos de una posible corrosin que se diera por inclemencias del medio
ambiente en el que pudiera instalarse el equipo.
CONDICIONES
Tcnicas y particulares
2.8. NORMATIVA
El equipo tendr que cumplir las normas citadas a continuacin:
IV.- PRESUPUESTO
PRESUPUESTO
IV.- PRESUPUESTO
1. Mediciones
2. Presupuestos parciales
3. Presupuesto total
PRESUPUESTO
1. Mediciones
1.1. Circuito 1: Etapa de potencia, medida de intensidad
por el motor, acondicionamiento microprocesador.
# COMPONENTE REFERENCIA #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0
1NF
1NF
1NF
1NF
1NF
1
2N3904
2k
4.7K
4X 22
4X 22
5.6k
6.8k
10K
10K
10UF TANT.
10UF TANT.
10u
13k
43
68NF
68NF
68NF
68NF
68NF
68NF
68NF
C2
C3
C4
C5
C17
R1B
C6
C7
C8
C9
C14
R6
Q1
R7
R4
RP1
RP2
R3
R11
R12
R13
C1
C16
C3B
R8
R1
C18
C19
C20
C21
C22
C23
C24
34
68NF
C25
COMPONENTE
35
68NF
36
68NF
37
100N
38
100N
39
100PF
40
100PF
41
100PF
42
100PF
43
100PF
44
150k
45
200
46
270
47
7805/SIP
48
CARGA
49 Conector Acelermetro
50
DIODE BRIDGE
51 DIODE ZENER (3.3 V)
52 DIODE ZENER (3.3 V)
53
FUENTE
54
Flash Voltage Ref.
55
L298/MUTIV
56
MCF5282CVF66
57
OP-07
58
OP-07
59
OP-07
60
OP-07
61
SIPSOC-3
62
STANDBY SUPPLY
63
STANDBY SUPPLY
64
STANDBY SUPPLY
65
Voltage Ref. High
66
Voltage Ref. Low
67
ilq74
REFERENCIA
C26
C27
C1B
C2B
C10
C11
C12
C13
C15
R9
R2
R10
U9
J7
J10
D2
D1
D3
J8
JP1
U3
U1
U4
U5
U6
U7
J9
JP2
JP4
JP6
JP3
JP5
U2
PRESUPUESTO
1.5K
1.5K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
3.3U
3.3U
5.6K
5.6K
100K
R8
R10
R2
R3
R4
R5
R6
R12
R13
R14
R15
R16
C1
C2
R7
R9
R1
COMPONENTE
18
100K
19
ADXL320
20
BYV28-150
21
BYV28-150
22
BYV28-150
23
BYV28-150
24 CONECTOR ACELERMETRO
25
FUENTE
26
FUENTE
27
FUENTE
28
OP-07
29
OP-07
30
OP-07
31
OP-07
32
OP-07
33
OP-07
REFERENCIA
R11
U1
D1
D2
D3
D4
J4
J1
J2
J3
U2
U3
U4
U5
U6
U7
0.33K
0.33K
0.47K
0.47K
1.5k
1K
1K
1K
1K
1K
1K
2N3904
2N3904
4.7k
70k
100K
100K
100K
R1
R6
R14
R15
R8
R2
R5
R9
R10
R16
R17
Q1
Q2
R4
R13
R3
R7
R11
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
COMPONENTE
REFERENCIA
100K
Conector Micro
DIODE ZENER (3.3V)
DUMMY
DUMMY
FUENTE
FUENTE
LED
LED
OP-07
OP-07
OP-07
OP-07
OP-07
OP-07
PHOTODIODE
PHOTODIODE
R12
J4
D7
D2
D4
J1
J2
D8
D9
U1
U2
U3
U4
U5
U6
D1
D3
PRESUPUESTO
2. Presupuestos parciales
2.1. Circuito 1: Etapa de potencia, medida de intensidad
por el motor, acondicionamiento microprocesador.
REFERENCIA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
COMPONENTE
C1,C16
10uF TANT.
C1,C2
100n
C10,C11,C12,C13,C15
100pF
C18,C19,C20,C21,C22,C23,
68nF
C1B,C2B
100n
C2,C3,C4,C5,C17
0.1uF
C24,C25,C26,C27
C3
10u
C3B
10u
C6,C7,C8,C9,C14
1nF
D1,D3
DIODE ZENER (3V)
D1,D3
DIODE ZENER (3.3 V)
D2
DIODE BRIDGE
D2
DIODE BRIDGE
J10
Conector Acelermetro
J7
CARGA
J7
CARGA
J8
FUENTE
J8
FUENTE
J9
SIPSOC-3
J9
SIPSOC-3
JP1
Flash Voltage Ref.
JP2,JP4,JP6
Standby supply
JP3
Voltage Ref. High
JP5
Voltage Ref. Low
Q1
2N3904
Q1
2N3904
R1
43
R1
43
R10
270
R10
270
R11
6.8k
R11
6.8k
R12,R13
10k
R12,R13
10k
UDS.
2
2
5
10
2
5
1
1
5
2
2
1
1
1
1
1
1
1
1
1
1
3
1
1
1
1
1
1
1
1
1
1
2
2
PRECIO
UD.
1,60
0,01
0,01
0,01
0,01
0,01
0,01
0,01
0,01
0,01
0,03
0,03
0,15
0,15
0,20
0,20
0,20
0,20
0,20
0,20
0,20
0,15
0,15
0,15
0,15
0,03
0,03
0,02
0,02
0,02
0,02
0,02
0,02
0,02
0,02
TOTAL
3,20
0,02
0,05
0,10
0,02
0,05
0,00
0,01
0,01
0,05
0,06
0,06
0,15
0,15
0,20
0,20
0,20
0,20
0,20
0,20
0,20
0,15
0,45
0,15
0,15
0,03
0,03
0,02
0,02
0,02
0,02
0,02
0,02
0,04
0,04
PRESUPUESTO
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
R1B
R2
R2
R3
R3
R4
R4
R6
R6
R7
R7
R8
R8
R9
R9
RP1,RP2
U1
U10
U2
U3
U4,U5,U6,U7
U9
0
200
200
5.6k
5.6k
4.7k
4.7k
1
1
2k
2k
13k
13k
150k
150k
4x 22
MCF5282CVF66
7803/SIP
ilq74
L298/MUTIV
OP-07
7805/SIP
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
4
1
0,02
0,02
0,02
0,02
0,02
0,02
0,02
0,02
0,02
0,02
0,02
0,02
0,02
0,02
0,02
0,70
47,29
0,53
2,77
4,45
0,04
0,53
TOTAL
0,02
0,02
0,02
0,02
0,02
0,02
0,02
0,02
0,02
0,02
0,02
0,02
0,02
0,02
0,02
1,40
47,29
0,53
2,77
4,45
0,16
0,53
63,92
1
2
3
4
5
6
7
8
9
10
REFERENCIA
COMPONENTE
UDS.
PRECIO
UD.
C1,C2
D1,D2,D3,D4
J1,J2,J3
J4
R1,R11
R2,R3,R4,R5,R6,R12,R13,
R14,R15,R16
R7,R9
R8,R10
U1
U2,U3,U4,U5,U6,U7
3.3u
BYV28-150
FUENTE
Conector Acelermetro
100k
1k
2
4
3
1
2
10
0,01
0,02
0,20
0,20
0,02
0,02
5.6k
1.5k
ADXL320
OP-07
2
2
1
6
0,02
0,02
10,08
0,04
TOTAL
TOTAL
0,02
0,08
0,60
0,20
0,04
0,20
0,00
0,04
0,04
10,08
0,24
11,54
PRESUPUESTO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
REFERENCIA
COMPONENTE
UDS.
PRECIO
UD.
TOTAL
D1,D3
D2,D4
D7
D8,D9
J1,J2
J4
Q1,Q2
R1,R6
R2,R5,R9,R10,R16,R17
R3,R7,R11,R12
R4
R8
R13
R14,R15
U1,U2,U3,U4,U5,U6
PHOTODIODE
Dummy
DIODE ZENER (3.3V)
LED
FUENTE
Conector Micro
2N3904
0.33k
1k
100k
4.7k
1.5k
70k
0.47k
OP-07
2
2
1
2
2
1
2
2
6
4
1
1
1
2
6
10,44
10,44
0,03
0,44
0,20
0,20
0,03
0,02
0,02
0,02
0,02
0,02
0,02
0,02
0,03
20,88
20,88
0,03
0,88
0,40
0,20
0,06
0,04
0,12
0,08
0,02
0,02
0,02
0,04
0,18
TOTAL
43,85
2.4. Maqueta:
1
2
3
COMPONENTE
UDS.
PRECIO UD.
TOTAL
1
2
12
89,5
1,1
1,1
89,5
2,2
13,2
TOTAL
104,9
2.5. Recursos:
Concepto
Ordenador AMD Athlon 64
Licencia Matlab
Licencia Freescale Codewarrior
Licencia PSPICE
Licencia Microsoft Office
TOTAL
UDS.
PRECIO
UD.
TOTAL
1
1
1
1
1
1200.00
600.00
380.00
350.00
450.00
1200.00
600.00
380.00
350.00
450.00
3580.00
PRESUPUESTO
2.6. Diseo:
Concepto
Hora ingeniera
TOTAL
UDS.
PRECIO
UD.
TOTAL
1056
35.00
36960.00
36960.00
PRESUPUESTO
3. Presupuesto total
Concepto
Gastos de materiales
Gastos de recursos empleados
Gastos de ingeniera
TOTAL
TOTAL
224,21
3580
36960
40764,21