module processor_8bit(in,out,rst,clk,q0,q1,q2,irout,pcout);

input rst,clk;
input [7:0] in;
output q0,q1,q2;
output [7:0] irout;
output [4:0] pcout;
output [7:0] out;
wire aload,pcload,irload,jmpmux,aeq0,apos,memwr,meminst,sub;
wire [1:0] asel;
datapath n1(aload,pcload,irload,jmpmux,rst,clk,in,out,aeq0,apos,asel,memwr,memin
st,irout,sub);
cu n2(clk,rst,aeq0,apos,irout[7],irout[6],irout[5],irload,jmpmux,pcload,aload,me
minst,memwr,
asel,sub,q0,q1,q2);
endmodule
module
datapath(aload,pcload,irload,jmpmux,rst,clk,in,out,aeq0,apos,asel,memwr,meminst,
irout,sub);
input aload,pcload,irload,jmpmux,rst,clk,memwr,meminst,sub;
input [1:0] asel;
input [7:0] in;
output [7:0] out;
output [7:0] irout;
output aeq0,apos;
wire [7:0] accout;
wire [7:0] memout,addsubout,accin;
wire [4:0] pcout,mux1out,mux2out,incout;
mux4x1 m1(memout,addsubout,in,,asel[0],asel[1],accin);
ram m2(accout,memout,mux2out,memwr,clk);
mux2X1 m3(pcout,irout[4:0],meminst,mux2out);
mux2X1 m4(incout,irout[4:0],jmpmux,mux1out);
inc m5(pcout,incout);
addsub m6(addsubout,accout,memout,sub);
acc m7(aload,accin,accout,clk,rst);
ir m8(irload,memout,irout,clk,rst);
pc m9(pcload,mux1out,pcout,clk,rst);
nor m10(aeq0,accout[0],accout[1],accout[2],accout[3],accout[4],accout[5],accout[
6],accout[7]);
not m11(apos,accout[7]);
assign out=accout;
endmodule
module cu(clk,rst,aeq0,apos,ir7,ir6,ir5,irload,jmpmux,pcload,aload,meminst,memwr
,asel,sub
,q0,q1,q2);
input clk,rst,aeq0,ir7,ir6,ir5,apos;
output irload,pcload,aload,meminst,jmpmux,memwr,sub,q0,q1,q2;
wire
d0,d1,d2,q0,q1,q2,d21,d22,d23,d11,d12,d13,d14,d01,d02,d03,d04,d05,pcload1,pcload
2,pcload3,alo
ad,q0b,q1b,q2b,jzmux,jpmux;
output [1:0] asel;
wire aload1,aload2;
//Gates at the input of DFF
not(q0b,q0);
not(q1b,q1);
not(q2b,q2);

not(ir7b,ir7);
not(ir6b,ir6);
not(ir5b,ir5);
and(d21,q2,q1,q0);
and(d22,q2b,q1,q0b,ir7);
and(d23,q2b,q1,q0b,ir6);
or(d2,d21,d22,d23);
and(d11,q2,q1,q0);
and(d12,q2b,q1,q0b,ir7,ir5);
xnor(d141,ir7,ir6);
and(d13,q2b,q1,q0b,d141);
and(d14,q2b,q1b,q0);
or(d1,d11,d12,d13,d14);
and(d01,q2,q1,q0);
and(d02,q2b,q1,q0b,ir6b,ir5b);
and(d03,q2b,q1,q0b,ir6b,ir7b);
and(d04,q2b,q1,q0b,ir6,ir7,ir5);
and(d05,q2b,q1b,q0b);
or(d0,d01,d02,d03,d04,d05);
//DFF Instantiation
dffa a1(d0,rst,clk,q0);
dffa a2(d1,rst,clk,q1);
dffa a3(d2,rst,clk,q2);
//Control Signal Generation
and(irload,q2b,q1b,q0);
and(pcload1,q2b,q1b,q0);
and(pcload2,q2,q1,q0b,aeq0,ir7,ir6b,ir5);
and(pcload3,q2,q1,q0b,apos,ir7,ir6,ir5b);
or(pcload,pcload1,pcload2,pcload3);
//and(inmux,q2b,q1,q0);
and(aload2,q2,q1b);
and(aload1,q2b,q1,q0,ir5b,ir6b,ir7b);
or (aload,aload1,aload2);
//and(aload2,q2,q1b,q0);
//or(aload,aload1,aload2);
and(jpmux,q2,q1,q0b,apos,ir7,ir6,ir5b);
and(jzmux,q2,q1,q0b,aeq0,ir7,ir6b,ir5);
or(jmpmux,jpmux,jzmux);
//and(halt,q2,q1,q0);
or(meminst,q2,q1);
and(memwr,q2b,q1,q0b,ir7b,ir6b,ir5);
and(sub,ir7b,ir6,ir5);
assign asel={ir7,ir6};
endmodule
// DFF
module dffa(d,clr,clk,q);
input d,clr,clk;
output reg q;
always @(posedge clk,posedge clr)
begin
if(clr)
begin
q=0;
end
else
begin
q=d;
10
end

end
end
endmodule
// Accumulator
module acc(aload,in,out,clk,rst);
input clk,rst,aload;
input [7:0] in;
output [7:0] out;
reg [7:0] registor=8'b00000000;
always @(posedge clk)
begin
if (rst)
registor=8'b00000000;
else if (aload)
registor=in;
end
assign out=registor;
endmodule
// Adder subtractor unit
module adder(sum,cout,a,b,c);
output sum,cout;
input a,b,c;
wire y1,y2,y3;
xor (y1,a,b);
and (y2,a,b);
xor (sum,y1,c);
and (y3,y1,c);
or (cout,y3,y2);
endmodule
// N bit adder
module addsub(out,a,b,sub);
parameter n=8;
input [n-1:0] a,b;
output [n-1:0] out;
wire cout;
input sub;
wire [n-1:0] x;
wire [n:0] c;
assign c[0]=sub;
genvar i;
generate for(i=0;i<n;i=i+1) begin: adder_loop
xor (x[i],b[i],sub);
adder m1(out[i],c[i+1],a[i],x[i],c[i]);
end
endgenerate
endmodule
// instruction register
module ir(irload,d,ir,clk,rst);
input clk,rst,irload;
input [7:0] d;
output [7:0] ir;
reg [7:0] registor=8'b00000000;
always @(posedge clk)
begin
if (rst)

registor=8'b00000000;
else if (irload)
registor=d;
end
assign ir=registor;
endmodule
// Program counter
module pc(pcload,d,pc,clk,rst);
input clk,rst,pcload;
input [4:0] d;
output [4:0] pc;
reg [4:0] registor=8'b00000000;
always @(posedge clk)
begin
if (rst)
registor=5'b00000;
else if (pcload)
registor=d;
end
assign pc=registor;
endmodule
// Incrementing unit
module inc(in,out);
input [4:0] in;
output [4:0] out;
assign out=in+1;
endmodule
// Memory unit
module ram(datain,dataout,add,rw,clk);
input rw,clk;
reg [7:0] mem [0:31];
input [7:0] datain;
output reg [7:0] dataout;
input [4:0] add;
initial
begin
mem [0]=8'b00010000;
mem [1]=8'b10101100;
mem [2]=8'b10000000;
mem [3]=8'b00111001;
mem [4]=8'b01010001;
mem [5]=8'b00011001;
mem [16]=8'b00000010;
mem [17]=8'b00000110;
end
always @(posedge clk)
begin
if (rw==0)
dataout=mem[add];
else if(rw==1)
mem[add]=datain;
end
endmodule
// Multiplexors
module mux4x1(d0,d1,d2,d3,s0,s1,y);
parameter n=8;
input [n-1:0] d0,d1,d2,d3;
input s0,s1;
wire [n-1:0] y1,y2;

output [n-1:0] y;
mux2X18 m1(d0,d1,s0,y1);
mux2X18 m2(d2,d3,s0,y2);
mux2X18 m3(y1,y2,s1,y);
endmodule
module mux2X1(d0,d1,s,y);
parameter n=5;
input s;
input [n-1:0] d0,d1;
output reg [n-1:0] y;
always @(*)
begin
case(s)
1'b0: y=d0;
1'b1: y=d1;
default: $display("Invalid Condition");
endcase
end
endmodule
module mux2X18(d0,d1,s,y);
parameter n=8;
input s;
input [n-1:0] d0,d1;
output reg [n-1:0] y;
always @(*)
begin
case(s)
1'b0: y=d0;
1'b1: y=d1;
default: $display("Invalid Condition");
endcase
end
endmodule