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Algunas de las figuras de esta presentacin fueron tomadas de las pginas de internet de los autores de los textos: A.S. Sedra and K.C. Smith, Microelectronic Circuits. New York, NY: Oxford University Press, 1998. A.R. Hambley, Electronics: A Top-Down Approach to Computer-Aided Circuit Design. Englewood Cliffs, NJ: Prentice Hall, 2000. R.C. Jager, Microelectronic Circuit Design. New York, NY: McGraw Hill, 1997. Dr. J.E. Rayas Snchez
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tor lec l Co n+
n
p
ep ita xy
i Em
iC
tte
+ n
n +
i
E
se Ba n
i
B
xy + ita p ep
+ bu rie dl ay er p
+ p p
iB
Emitter
iC iC iE = iB (1 + ) = = /(1 + )
IS v iB = e
iC = I S e v
BE
/ VT
BE
/ VT
iE =
IS v e
BE
/ VT
IS v iB = e
iC = I S e v
BE
/ VT
BE
/ VT
IS v iE = e
Dr. J.E. Rayas Snchez
BE
/ VT
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iC iC iE = iB (1 + ) = = /(1 + )
IS v iB = e
iC = I S e v
EB
/ VT
EB
/ VT
IS v iE = e
EB
/ VT
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IS v iB = e
iC = I S e v
EB
/ VT
EB
/ VT
IS v iE = e
Dr. J.E. Rayas Snchez
EB
/ VT
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14
Efecto Early
15
Collector
CB2
> v
CB1
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PNP
/ VT
VEC v )e iC = I S (1 + VA
EB
/ VT
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Saturation Region Forward Bias (Closed Switch) Reverse-Active Region (Inverse-Active Region) (Poor Amplifier)
Dr. J.E. Rayas Snchez
Reverse Bias
Modelo de Ebers-Moll
iDE = I SE (e v iDC = I SC (e v
BE
/ VT
1) 1)
BC
/ VT
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Modelo de Transporte
IS v (e iB = F
iT = I S (e v
BE BE
/ VT
IS v 1) + (e R
BC
BC
/ VT
1)
/ VT
1) + I S (e v
/ VT
1)
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2.0mA
I = 80 uA B
I = 60 uA B
I B = 40 uA
I = 20 uA B
I = 0 uA B 0.0mA Cutoff
Reverse-Active Region
Saturation Region 0V 5V
= 25 = 5
F R 10V 24
-1.0mA -5V
V CE
25
r =
gm
IC gm = VT
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r = gm
VA ro = IC
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