INFORME PRACTICA No.1.

DISEÑO E IMPLEMENTACIÓN DE CIRCUITOS

COMBINACIONALES MODULARE

MAURICIO REYES ROSERO

TOMÁS MESA SÁNCHEZ

UNIVERSIDAD DE ANTIOQUIA
FACULTAD DE INGENIERIA
DEPARTAMENTO DE INGENIERIA ELECTRONICA
MEDELLIN
2021
 OBJETIVOS
-Utilizar la herramienta Vivado para programar hardware.
-Representar números en un display de siete segmentos a partir de los diferentes
componentes electrónicos como: Alu, decodificador de bcd a 7 segmentos, mux,
driver triestado y flip flops.
-Implementar un divisor de reloj para hacer registros por intervalos de tiempo
 CONCLUSIONES
-El divisor de reloj es de gran ayuda para registrar datos y mostrarlos en
intervalos de tiempo específicos.
-El programa Vivado es una herramienta esencial para crear circuitos
digitales.
-Cuando se necesita hacer una lectura de información la memoria Rom es
muy funcional.
-El decodificador siempre debe estar bien programado porque o sino el
circuito puede estar bueno, pero lo que muestra el display va a ser erróneo.
 CIRCUITO

El circuito se efectuó, realizando un archivo (.vhd) para implementar cada

uno de los componentes como son:
- MEMORIAS ROM
- MUX
- FLIP – FLOP
- UNIDAD ARITMETICA Y LOGICA (ALU)
- DIVISOR DE RELOJ
- DECODIFIADOR DE BCD A 7 SEGMENTOS

REPRECENTACION ESQUEMATICO
 MEMORIA ROM (A)

Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ROMA is
Port ( add_A : in STD_LOGIC_VECTOR (2 downto 0);
salida_roma : out STD_LOGIC_VECTOR (3 downto 0));
end ROMA;

architecture Behavioral of ROMA is

type ROMA_array is array (0 to 7) of std_logic_vector(3 downto 0);
constant ROM : ROMA_array :=(

0 => "1011",
1 => "1111",
2 => "0100",
3 => "1000",
4 => "1010",
5 => "1011",
6 => "1100",
others => "1111"
);

begin
salida_roma <= ROM(conv_integer(add_A)); --salida_roma <=
ROM(direccion (add_A)"convertida de binario a entero")

end Behavioral;
MUX (2 -1)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity MUX is
Port ( FA : in STD_LOGIC;
sal_ROMA : in STD_LOGIC_VECTOR (3 downto 0);
DATA_A : in STD_LOGIC_VECTOR (3 downto 0);
SALIDA_MUX : out STD_LOGIC_VECTOR (3 downto 0));
end MUX;

architecture Behavioral of MUX is

begin

process (FA,sal_ROMA,DATA_A)
begin
if FA = '0' then
SALIDA_MUX <= sal_ROMA;
else
SALIDA_MUX <= DATA_A;
end if;
end process;

end Behavioral;
flip_flop_a (FLIP_FLOP TIPO D)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity FLIP_FLOP_A is
Port ( DA : in STD_LOGIC_VECTOR (3 downto 0);
QA : out STD_LOGIC_VECTOR (3 downto 0);
en0 : in STD_LOGIC;
clk : in STD_LOGIC);
end FLIP_FLOP_A;

architecture Behavioral of FLIP_FLOP_A is

begin
process (clk)
begin
if(clk'event and clk='1') then
if(en0='1') then
QA <= DA;
end if;
end if;
end process;

end Behavioral;

MEMORIA ROM (B)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ROMB is
Port ( add_b : in STD_LOGIC_VECTOR (2 downto 0);
salida_romb : out STD_LOGIC_VECTOR (3 downto 0));
end ROMB;

architecture Behavioral of ROMB is

type ROMB_array is array (0 to 7) of std_logic_vector (3 downto 0);
constant ROM_B : ROMB_array :=(
0 => "1100",
1 => "0100",
2 => "1100",
3 => "0110",
4 => "1000",
5 => "0010",
6 => "1111",
others => "0111"
);

begin
salida_romb <= ROM_B(conv_integer(add_b));
end Behavioral;

DIVER TRI-ESTADO
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity DRIVERS is
Port ( DataB:in STD_LOGIC_VECTOR (3 downto 0);
entrada_driver_2: in STD_LOGIC_VECTOR (3 downto 0);
Salida_Drivers: out STD_LOGIC_VECTOR (3 downto 0);
FB:in STD_LOGIC);
end DRIVERS;

architecture Behavioral of DRIVERS is

begin
process (FB,DataB,entrada_driver_2)
begin
if FB= '0' then
salida_Drivers <=DataB;

else
salida_Drivers <= entrada_driver_2;

end if;
end process;

end Behavioral;
FLIP_FLOP_B (flip-flop tipo D)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity FLIP_FLOP_B is
Port ( DB : in STD_LOGIC_VECTOR (3 downto 0);
QB : out STD_LOGIC_VECTOR (3 downto 0);
clk1 : in STD_LOGIC;
en0 : in STD_LOGIC);
end FLIP_FLOP_B;

architecture Behavioral of FLIP_FLOP_B is

begin
process (clk1)
begin
if(clk1'event and clk1='1') then
if(en0='1') then
QB <= DB;
end if;
end if;
end process;

FLIP_FLOP_O (flip-flop tipo D)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity FLIP_FLOP_O is
Port ( DO : in STD_LOGIC_VECTOR (3 downto 0);
QO : out STD_LOGIC_VECTOR (3 downto 0);
en2 : in STD_LOGIC;
clk : in STD_LOGIC);
end FLIP_FLOP_O;

architecture Behavioral of FLIP_FLOP_O is

begin
process (clk)
begin
if(clk'event and clk='1') then
if(en2='1') then
QO<= DO;
end if;
end if;
end process;

end Behavioral;

DECODIFICADOR
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.ALL;
use IEEE.std_logic_unsigned.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity DECODIFICADOR is
Port ( entrada_dec : in STD_LOGIC_VECTOR (3 downto 0);
salida_dec:out std_logic_vector (6 downto 0 ));
-- ent_dec : in STD_LOGIC_VECTOR (3 downto 0));

end DECODIFICADOR;

architecture Behavioral of DECODIFICADOR is

signal display : std_logic_vector(6 downto 0);

--signal entrada_dec :std_logic_vector(3 downto 0);

begin

with entrada_dec select

display <= "1000000" when "0000",
"1111001" when "0001",
"0100100" when "0010",
 "0110000" when "0011",
"0011001" when "0100",
"0010010" when "0101",
"0000011" when "0110",
"0111000" when "0111",
"0000000" when "1000",
"0000100" when "1001",
"1111110" when "1010",
"0110000" when "1011",
"1101101" when "1100",
"1111001" when "1101",
"0110011" when "1110",
"1011011" when others;

salida_dec <= display;

end Behavioral;

DIVISOR DE RELOJ
Para reducir la frecuencia de la señal de reloj que nos a a controlar los enable