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INTEGRANTES:
INGENIERÍA ELECTRÓNICA.
5º SEMESTRE.
ACTIVIDAD 4.2
Lógicas Aritméticas
S1 S0 S2=0 S2=1
0 0 ̅
𝑨 𝑨+𝑩+𝟏
0 1 ̅+𝑩
𝑨 𝑨−𝑩−𝟏
1 0 𝑨∙𝑩 −𝑨 − 𝟏
1 1 𝑨⊕𝑩 −𝑩 + 𝟏
Tabla 1: Tabla de operaciones solicitadas en función de S2,S1 y S0
Realizar una ALU con diferentes operaciones lógicas y aritméticas las cuales funcionarán
por medio del uso de multiplexores. El multiplexor a utilizar será el encargado de
realizar,seleccionar datos y controlar nuestra Unidad Lógica Aritmética. Por tanto, el
diseño se seccionará en: el módulo lógico, módulo aritmético y un multiplexor para el
control general.
En cuanto a la selección de los dos módulos ,se emplea el bit más significativo del
selector de la ALU para la distinción del módulo a ocupar (aritmético o el lógico ) , en
cuanto a los otros dos bits para la selección de las operaciones a mostrar de cada
módulo.
1. MÓDULO LÓGICO:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity MOD_LOGIG is
Port ( Ain : in STD_LOGIC_VECTOR (3 downto 0);
Bin : in STD_LOGIC_VECTOR (3 downto 0);
selec : in STD_LOGIC_VECTOR (1 downto 0);
Salida1 : out STD_LOGIC_VECTOR (7 downto 0));
end MOD_LOGIG;
architecture Behavioral of MOD_LOGIG is
begin
process(Ain,Bin,selec)
begin
case (selec) is
when "00" =>
Salida1 <= ("0000" & (not Ain));
when "01" =>
Salida1 <= ("0000"& (not Ain)) + ("0000"& Bin);
when "10" =>
Salida1 <= Ain * Bin;
when "11" =>
Salida1 <= ("0000"& Ain) xor ("0000"& Bin) ;
when others =>
Salida1 <= "00000000";
end case;
end process;
end Behavioral;
2. MÓDULO ARITMÉTICO:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
entity MOD_ARITH is
Port ( Ain : in STD_LOGIC_VECTOR (3 downto 0);
Bin : in STD_LOGIC_VECTOR (3 downto 0);
selec : in STD_LOGIC_VECTOR (1 downto 0);
Salida2 : out STD_LOGIC_VECTOR (7 downto 0));
end MOD_ARITH;
architecture Behavioral of MOD_ARITH is
begin
process(Ain,Bin,selec)
begin
case (selec) is
when "00" =>
Salida2 <= ("0000"& Ain)+("0000" & Bin) + '1';
when "01" =>
Salida2 <= ("0000" & Ain) + ( "0000" &(not Bin) + '1') - '1';
when "10" =>
Salida2 <= ("0000" &(not Ain) + '1') - '1';
when "11" =>
Salida2 <= ( "0000" &(not Bin) + '1') + '1' ;
when others =>
Salida2 <= "00000000";
end case;
end process;
end Behavioral;
3. MUX:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX is
Port ( En1 : in STD_LOGIC_VECTOR (7 downto 0);
En2 : in STD_LOGIC_VECTOR (7 downto 0);
Salida: out STD_LOGIC_VECTOR (7 downto 0);
selec : in STD_LOGIC);
end MUX;
begin
with selec select
Salida <= En1 when ('0'),
En2 when others;
end Behavioral;
4. TOP ALU:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TOP_ALU is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (2 downto 0);
Result : out STD_LOGIC_VECTOR (7 downto 0));
end TOP_ALU;
component MOD_LOGIG is
Port ( Ain : in STD_LOGIC_VECTOR (3 downto 0);
Bin : in STD_LOGIC_VECTOR (3 downto 0);
selec : in STD_LOGIC_VECTOR (1 downto 0);
Salida1 : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component MOD_ARITH is
Port ( Ain : in STD_LOGIC_VECTOR (3 downto 0);
Bin : in STD_LOGIC_VECTOR (3 downto 0);
selec : in STD_LOGIC_VECTOR (1 downto 0);
Salida2 : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component MUX is
Port ( En1 : in STD_LOGIC_VECTOR (7 downto 0);
En2 : in STD_LOGIC_VECTOR (7 downto 0);
Salida: out STD_LOGIC_VECTOR (7 downto 0);
selec : in STD_LOGIC);
end component;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Test_benchALU is
end Test_benchALU;
architecture Behavioral of Test_benchALU is
-- Component Declaration for the Unit Under Test (UUT)
component TOP_ALU is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (2 downto 0);
Result : out STD_LOGIC_VECTOR (7 downto 0));
end component;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal S : std_logic_vector(2 downto 0) := (others => '0');
--Outputs
signal Result: std_logic_vector(7 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
--constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: TOP_ALU PORT MAP (
A => A,
B => B,
S => S,
Result => Result
);
-- Stimulus process
stim_proc: process
begin
wait;
end process;
end Behavioral;
ANÁLISIS DE RESULTADOS.
En la ilustración podemos observar que las entradas A,B y el selector del módulo
aritmético y lógico están conectados entre sí, además que sus salidas junto con el
selector son las entradas del multiplexor.