Documentos de Académico
Documentos de Profesional
Documentos de Cultura
SUMADOR/RESTADOR
Cristian Fabian Rojas Diaz
Cundinamarca, Fundacin Universitaria los Libertadores
Bogot, Colombia
crisfarodi@hotmail.com
Obtendremos en el osciloscopio la
siguiente seal siendo la amarilla de
entrada y la blanca de salida,
sumador inversor aun si sumarle la
la segunda seal de entrada
Imagen 1. Seal visualizada en el osciloscopio. visualizamos lo siguiente:
SUMADOR INVERSOR
En la siguientes imgenes
podremos visualizar el resultado de
la seal sumada: IV.
Ecuacin 4.
A continuacin veremos la
configuracin restador:
En la siguiente imagen
visualizaremos la seal que
aplicamos desde el generador de
seales:
V. CONCLUSIONES
Los amplificadores
operacionales con estas
configuraciones nos da una
ganancia estable.
BIBLIOGRAFIA
Amplificadores operacionales
y circuitos integrados
lineales. - robert f coughlin.
Amplificadores operacionales
Arthur B. Williams.
VI. REFERENCIAS
XV.
XVI. Autor: Aamir A. Farooqui, Vojin G. Oklobdzijas2 , Farzad Chechrazi.
XVII. Titulo: Multiplexer based adder for media signal processing.
XVIII. Published in:VLSI Technology, Systems, and Applications, 1999. International
Symposium on.
XIX. Date of Conference: 1999.
XX. Page(s): 100 103.
XXI. Meeting Date : 08 Jun 1999-10 Jun 1999.
XXII.
XXIII.
XXIV. Autor: Gin Yee and Carl Sechen.
XXV. Titulo: Clock-delayed domino for adder and combinational logic design.
XXVI. Published in: Computer Design: VLSI in Computers and Processors, 1996.
ICCD '96. Proceedings., 1996 IEEE International Conference on.
XXVII. Date of Conference: 7-9 Oct 1996.
XXVIII. Page(s): 332 337.
XXIX. Meeting Date : 07 Oct 1996-09 Oct 1996
XXX.
XXXI.
XXXII.
XXXIII.
XXXIV.
XXXV.
XXXVI.
XXXVII.
XXXVIII. Autor: Neil Burgess.
XXXIX. Titulo: Fast Ripple-Carry Adders in Standard-Cell CMOS VLSI.
XL. Published in: Computer Arithmetic (ARITH), 2011 20th IEEE Symposium on.
XLI. Date of Conference: 25-27 July 2011.
XLII. Page(s): 103 111.
XLIII.
XLIV.
XLV. Autor: M. Nadi Senejani, M. Hosseinghadiry, M. Miryahyaei.
XLVI. Titulo: Low Dynamic Power High Performance Adder.
XLVII. Published in: Future Computer and Communication, 2009. ICFCC 2009.
International Conference on.
XLVIII. Date of Conference: 3-5 April 2009.
XLIX. Page(s): 482 486.
L.
LI.
LII. Autor: M. Nadi Senejani, M. Hossein Ghadiry.
LIII. Titulo: Low dynamic power high performance adder.
LIV. Published in: CAD Systems in Microelectronics, 2009. CADSM 2009. 10th
International Conference - The Experience of Designing and Application of.
LV. Date of Conference: 24-28 Feb. 2009.
LVI. Page(s): 242 245.
LVII.
LVIII.
LIX. Autor: Victor NavarroBotello, Juan A. MontielNelson, Saeid Nooshabadi.
LX. Titulo: Fast adder design in dynamic logic.
LXI. Published in: Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest
Symposium on.
LXII. Date of Conference: 5-8 Aug. 2007.
LXIII. Page(s): 851 854.
LXIV.
LXV.
LXVI. Titulo: Multiple-input neuron MOS operational amplifier for voltage-mode
multivalued full adders.
LXVII. Published in: Circuits and Systems II: Analog and Digital Signal Processing,
IEEE Transactions on (Volume:45 , Issue: 9 ).
LXVIII. Date of Publication: Sep 1998.
LXIX. Page(s): 1307 1311.
LXX.
LXXI.
LXXII. Autor: W. W. Goldsworthy.
LXXIII. Titulo: Semilogarithmic Amplifier System.
LXXIV. Published in: Nuclear Science, IEEE Transactions on (Volume:12 , Issue: 1).
LXXV. Date of Publication: Feb. 1965.
LXXVI. Page(s): 336 345.
LXXVII.
LXXVIII.
LXXIX.
LXXX.
LXXXI.
LXXXII.
LXXXIII. Autor: Po-Chiun Huang, Yi-Huei Chen, and Chorng-Kuang Wang, Member,
IEEE.
LXXXIV. Titulo: A 2-V 10.7-MHz CMOS limiting amplifier/RSSI.
LXXXV. Published in: Solid-State Circuits, IEEE Journal of (Volume:35 , Issue: 10 ).
LXXXVI. Date of Publication: Oct. 2000.
LXXXVII. Page(s):1474 1480.
LXXXVIII.