--en esta seccion del codigo se debe

--poner un ancabezado
--obligatorio para el laboratorio

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sumador is
port(
x_i :in std_logic_vector(3 downto 0);
y_i :in std_logic_vector(3 downto 0);
c_i :in std_logic;
Z_o :out std_logic_vector(3 downto 0);
c_o :out std_logic
);
end entity;

architecture comportamental of sumador is

signal carry :std_logic_vector(3 downto 0);
begin

U1: entity work.FA

port map(
x_i => x_i(0),
y_i => y_i(0),
c_i => c_i,
c_o => carry(0),
S_o => Z_o(0)
);
U2: entity work.FA
port map(
x_i => x_i(1),
y_i => y_i(1),
c_i => carry(0),
c_o => carry(1),
S_o => Z_o(1)
);

U3: entity work.FA

port map(
x_i => x_i(2),
y_i => y_i(2),
c_i => carry(1),
c_o => carry(2),
S_o => Z_o(2)
);

U4: entity work.FA

port map(
x_i => x_i(3),
 y_i => y_i(3),
c_i => carry(2),
c_o => c_o,
S_o => Z_o(3)
);

end comportamental;