5.

- Implementar un circuito que genere la siguiente forma de onda:

SEL DC
00 10%
01 25%
10 75%
11 90%
Sabiendo que la seal de reloj es de 48MHz y la salida tiene una
frecuencia de 1KHz.

Cdigo:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity prob_1 is
Port (clk: in std_logic;
sel: in std_logic_vector(1 downto 0);
z: buffer std_logic);
end prob_1;
architecture Behavioral of prob_1 is
signal conta: std_logic_vector(8 downto 0);
signal a1,a2,a3,a4: std_logic;
begin
process(clk)
begin
if clk='1' and clk'event then conta<=conta+1;
if conta = 49 then a1<='1';
end if;
if conta = 124 then a2<='1';
end if;
if conta = 374 then a3<='1';
end if;
if conta = 449 then a4<='1';
end if;
if conta=499 then conta<=(others=>'0');
a1<='0';
a2<='0';
a3<='0';
a4<='0';
end if;
end if;
end process;
z<= a1 when sel="00" else
a2 when sel="01" else
a2 when sel="10" else a4;

end Behavioral;
6.- Implementar un circuito divisor de frecuencia programable
SEL Fout
000 0
001 CLK/2
010 CLK/10
011 CLK/50
100 CLK/100
101 CLK/200
110 CLK/1000
111 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity div_8opc is
port(clk: in std_logic;
sel: in std_logic_vector(2 downto 0);
z: out std_logic);
end div_8opc;

architecture solucion of div_8opc is

signal clk1,clk2: std_logic;
signal cont4: std_logic_vector(1 downto 0);
signal cont10: std_logic_vector(3 downto 0);
signal cont50: std_logic_vector(5 downto 0);
begin

process(clk)
begin
if clk = '1' and clk'event then cont4 <= cont4+1;
end if;
end process;

process(clk1)
begin
if clk1 = '1' and clk1'event then cont10 <= cont10 + 1;
if cont10 = 9 then cont10 <= "0000";
end if;
end if;
end process;

process(clk2)
begin
if clk2 = '1' and clk2'event then cont50 <= cont50 + 1;
if cont50 = 49 then cont50 <= "000000";
end if;
end if;
end process;

clk1 <= cont4(0) when sel = "110" else clk;

clk2 <= cont4(0) when sel = "100" else
cont4(1) when sel = "101" else
cont10(3) when sel = "110" else clk;

with sel select z <='0' when "000",

'1' when "111",
cont4(0) when "001",
cont10(3) when "010",
cont50(5) when others;
end solucion;

7.- Implementar un circuito para temporizar:

SEL Tiempo
00 10ms
01 100ms
10 500ms
11 1000ms

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity timer is
port ( sel : in std_logic_vector(1 downto 0);
ena : in std_logic;
reset : in std_logic;
clk : in std_logic;
z : out std_logic);
end timer;
architecture Behavioral of timer is
signal cuenta : std_logic_vector(25 downto 0);
signal trigger : integer;
signal habilitado : std_logic;
begin
process(clk,reset)
begin
if reset = '1' then habilitado <= '0';
elsif ena = '1' then habilitado <= '1';
end if;
end process;

process(clk,reset)
begin
if reset = '1' then cuenta <= (others =>'0');
 z <= '0';
elsif clk = '1' and clk'event then
if habilitado = '1' then cuenta <= cuenta + 1;
if cuenta = trigger then cuenta <= (others => '0');
z <= '1';
end if;
end if;
end if;
end process;

with sel select trigger <= 48000 when "00",

480000 when "01",
2400000 when "10",
4800000 when others;
end Behavioral;

8.- Implementar un circuito para generar una seal PWM con la siguiente
caracterstica:

Resolucin: Resolucin: 10 bits.

Escalador: x1, x2, x4, x8, x16
El ciclo de trabajo (DC) se define con 110 bits de entrada.
Tiene habilitador.

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity pwm_prog is
port ( clk : in std_logic;
DC : in std_logic_vector(10 downto 0);
hab : in std_logic;
esc : in std_logic_vector(2 downto 0);
z : out std_logic);
end pwm_prog;

architecture Behavioral of pwm_prog is

signal cuenta1 : std_logic_vector(2 downto 0);
signal cuenta2 : std_logic_vector(9 downto 0);
signal x : std_logic_vector(2 downto 0);
signal clk1 : std_logic;
signal clk2 : std_logic;
begin

process (clk)
begin
if clk = '1' and clk'event then cuenta1 <= cuenta1 + 1;
if cuenta1 <= x then cuenta1 <= (others => '0');
clk1 <= not clk1;
end if;
end if;
end process;

with esc select x <= "000" when "001",

"001" when "010",
"011" when "011",
"111" when others;

with esc select clk2 <= clk when "000",

clk1 when others;

process (clk2,hab)
begin
if hab = '0' then cuenta2 <= (others => '0');
z <= '0';
elsif clk2 = '1' and clk2'event then cuenta2 <= cuenta2 + 1;
if cuenta2 = DC then z <= '0';
elsif cuenta2 = 1023 then cuenta2 <= (others => '0');
z <= '1';
end if;
end if;
end process;

end Behavioral;

9.- Implementar un reloj que cuente los segundos y minutos (MM:SS) y que
muestre la informacin en 4 display a 7 segmentos del tipo nodo comn y
comparten los mismos pines de los segmentos. Utilice el componente diseado
en la pregunta 3 como generador
de reloj.