TRABAJO DE SECUENCIALES PROBLEMA1

VHDL library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity prob1 is port(clk: in std_logic; x: in std_logic_vector (1 downto 0); z: out std_logic); end prob1; architecture funcion of prob1 is type estados is (s0,s1); signal pres, fut: estados; begin proceso1: process (pres,x) begin case pres is when s0 => if x="00" then fut <= s0; z <='0'; elsif x="01" then fut <= s0; z <='1'; elsif x="10" then fut <= s0; z <='1'; elsif x="11" then fut <= s1; z <='0'; end if; when s1 => if x="00" then fut <= s0; z <='1'; elsif x="01" then fut <= s1; z <='0';

elsif x="10" then fut <= s1; z <='0'; elsif x="11"then fut <= s1; z <='1'; end if; end case; end process proceso1; proceso2: process(clk) begin if (clk='1' and clk'event) then pres <= fut; end if; end process proceso2; end funcion;

PROBLEMA2

VHDL library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity prob2 is port(clk,x: in std_logic; z: out std_logic_vector (1 downto 0)); end prob2; architecture funcion of prob2 is type estados is (s0,s1,s2,s3); signal pres, fut: estados; begin proceso1: process (pres,x) begin case pres is when s0 => z <="00"; if x='0' then fut <= s1; else fut <= s2; end if; when s1 => z <="00"; if x='0' then fut <= s1; else fut <= s3; end if; when s2 => if x='0' then fut <= s3; z <="11"; else fut <= s0; z <="10"; end if; when s3 => z <="00"; if x='0' then fut <= s0; else fut <= s3; end if; end case; end process proceso1; proceso2: process(clk) begin if (clk='1' and clk'event) then pres <= fut; end if; end process proceso2; end funcion;

PROBLEMA3A

VHDL library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity prob3a is port(clk,x: in std_logic; z: out std_logic); end prob3a; architecture funcion of prob3a is type estados is (s0,s1,s2,s3); signal pres, fut: estados; begin proceso1: process (pres,x) begin case pres is when s0 => z <='0'; if x='0' then fut <= s1; else fut <= s3; end if; when s1 => z <='1'; if x='0' then fut <= s3; else fut <= s1;

end if; when s2 => if x='0' then fut <= s1; z <='1'; else fut <= s3; z <='0'; end if; when s3 => z <='0'; if x='0' then fut <= s3; else fut <= s1; end if; end case; end process proceso1; proceso2: process(clk) begin if (clk='1' and clk'event) then pres <= fut; end if; end process proceso2; end funcion;

PROBLEMA3B

VHDL library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity prob3b is port(clk: in std_logic; x: in std_logic_vector (1 downto 0); z: out std_logic); end prob3b; architecture funcion of prob3b is type estados is (s0,s1,s2,s3); signal pres, fut: estados; begin proceso1: process (pres,x) begin case pres is when s0 => if x="00" then fut <= s1; z <='0'; elsif x="11" then fut <= s1; z <='0'; elsif x="01" then fut <= s3; z <='1'; elsif x="10" then fut <= s3; z <='1'; end if; when s1 => if x="00" then fut <= s2; z <='1'; elsif x="11" then fut <= s2; z <='1'; elsif x="01" then fut <= s1; z <='0'; elsif x="10"then fut <= s1; z <='0'; end if; when s2 => if x="00" then

fut <= s2; z <='1'; elsif x="11" then fut <= s2; z <='1'; elsif x="01" then fut <= s1; z <='0'; elsif x="10" then fut <= s1; z <='0'; end if; when s3 => if x="00" then fut <= s1; z <='0'; elsif x="11" then fut <= s1; z <='0'; elsif x="01" then fut <= s3; z <='1'; elsif x="10" then fut <= s3; z <='1'; end if; end case; end process proceso1; proceso2: process(clk) begin if (clk='1' and clk'event) then pres <= fut; end if; end process proceso2; end funcion;

PROBLEMA3C

VHDL library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity prob3c is port(clk,x: in std_logic; z: out std_logic); end prob3c; architecture funcion of prob3c is type estados is (s0,s1,s2,s3); signal pres, fut: estados; begin proceso1: process (pres,x) begin case pres is when s0 => z <='0'; if x='0' then fut <= s0; else fut <= s1; end if; when s1 => z <='0'; if x='0' then fut <= s0; else fut <= s3; end if; when s2 => z <='1'; if x='0' then fut <= s0; else fut <= s2;

end if; when s3 => z <='0'; if x='0' then fut <= s0; else fut <= s2; end if; end case; end process proceso1; proceso2: process(clk) begin if (clk='1' and clk'event) then pres <= fut; end if; end process proceso2; end funcion;

PROBLEMA6

VHDL

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity Registro is PORT (clk,clr,C,SI,SD: in std_logic; Q: inout std_logic_vector (2 downto 0)); end Registro; architecture Desplazamiento of Registro is signal Q_int: std_logic_vector (2 downto 0); signal control: std_logic; begin Q <= Q_int; process(clk) begin if(clk 'event and clk='1') then if(clr='1') then Q_int <= "000"; else case C is when '0' => Q_int <= Q_int (1 downto 0)&SI; when '1' => Q_int <= SD&Q_int (2 downto 1); when others => end case; end if; end if; end process; end Desplazamiento;