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-- Nombre:
-- Documento:
-- Fecha:
-- Proyecto:
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity contador is
Port ( clk, reset : in STD_LOGIC;
Salida : out STD_LOGIC_VECTOR (3 downto 0)
);
end contador;
process (clk)
begin
if clk'event and clk='1' then
if reset='1' then
Q <= "0000";
else
Q <= Q+1;
end if;
end if;
end process;
salida <= Q;
end Behavioral;
entity Simulacion is
--
end Simulacion;
component contador
Port ( clk, reset : in STD_LOGIC;
Salida : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
-- Señales de salidas
signal Salida : STD_LOGIC_VECTOR (3 downto 0);
begin
process begin
--- Estímulos de la simulación wait for 100 ns;
wait for 100 ns;
reset <= '0';
wait for 100 ns;
wait;
end process;
end Behavioral;