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WW 10.8 Typical .CO Supply Currents .W .W . . . . . . .Y..C . .O. . . . . .W . . . . . . . . . . . . . . . . . . . 93
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WW .100Y.C M.TW WW .100Y. Appendix M .TW A. MC68HRC705KJ1 W .100
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. . . . . . . . . . . . . 103
W O WW 00Y.CO .TW WW .100Y.C M.TW
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Data Sheet — MC68HC705KJ1
W W.1 Y.COM W W
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WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y M .TW
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W. 1 1.1 Features
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W Y .C W W WW 00Y.CO .TW W
W 00 .T 1 the MC68HC705KJ1
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W W.1 Y.COM W Features
W Y .C W
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W .100 M.T
W 00 M.T W.1 Y.COM W
W .C O • Robust
W W.1 noise .C Oimmunity
W W
WW .100Y M .TW •
W
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W W Y .C O
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WW .100Y.C M.TW • 64W bytes
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W . 1 O M W O
W
WW .100Y.C M.TW
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W 00 Y .T W 0 0 .T .1 M
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W W
W
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W WW 00Y.CO .TW
W W resistor W 00 .T W
W 00
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W W
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W .100 O M .T W
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WW .100Y.C M.TW W crystal.1(MC68HLC705KJ1)
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WW .100Y.C M.TW
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W W
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MOTOROLA WW .100Y.C Introduction .TW WW 13
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W Y .C W
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W W.1 Y.COM
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W W WW 00Y.CO .TW
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W W.1• Internal
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W
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WW 00Y.CO .TW W W 0 0 .T WW .100Y.C M.TW
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W W WW 00Y.CO .TW W
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W W.1 Y.COM W OSCILLATOR W BY Y
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W .C O W W.1 Y.COM TIMER W
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W
WW .100Y M .TW W
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WW .100Y.C M.TW
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WW .100Y.C M.DETECT TW WW .100Y.C M.TW
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WW .100Y.C M.TW
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WW .100Y.C RESETM. T W W .1 0 W
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DATA DIRECTION REGISTER B

W .C O W W .C W W
WW .100YIRQ/V .TW W .100
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WW .100Y.C M.TW CPU WREGISTERS
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WW .100Y .CO .TW
WW .100Y.C M.TW WW .100Y.C M.TW PB2(1)
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WW .100Y M.T
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WW .100Y.C M.TW
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WW .100Y.C M.TW CONDITION W
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DATA DIRECTION REGISTER A
W W .C O W Y W
W 00 Y .T W W 0 0 .1 M
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W W
W .100 O M.T STATIC RAM (SRAM)W
W
W .100 OM
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W W .1 M
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W W Y .C W – 64 BYTES
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W
W W
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WW .100Y.C M.USER 00Y .TW 100
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W
W
WW .100Y.C M.TW
O
W O W O
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W 10-mA sink capability on all I/O pins
WW .100Y.C M.TW WW .100Y.C Notes: M .T W
W O WW 00Y.CO1. 5.5.TmAWsource capability WW 00Y.CO .TW
WW .100Y.C MASKMOPTION . T W REGISTER (MOR) W .1 2. External interrupt
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W C O W W .C OM W
WW .100Y. W Y W W 00 .T
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W .100 O M.T W W.1 Y.COM W
WW .100Y .C
WW .100Y.C M.TW M .TW W
W .100 O M.T
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W
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y .T
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W .100users. OM.T
WW .100Y. C
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W
14 WW .100Y.C Introduction .TW WW MOTOROLA
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
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W . 1 0
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WW .100Y .C W
W O M.T
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M W O Programmable Options
0 Y .CO .TW W W 0 0 Y.C .T W
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W W WW 00Y.CO .TW
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W W.1 Y.COM W
W .C W
M .TW W
W . 100
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W .100 O M.T
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0 0 Y.C .T W WW .100Y.C M.TWTable 1-1.WProgrammable . 1 00Y Options M.T
W
. 1 M W O W .C O
WW 00Y.CO .TW WW .100Y.CFeature .TW WW .100Y M .TW
. 1 M O M W O Option
WW 00Y.CO .TW W WW 00Y.C .TW WW .100Y.C M.TW
1 . 1 M or disabled CO
W W. .C OM
W
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WW 00Y.CO .TW
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W WW 0Y.
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W 0 0 Y .T W . 1 M . 1 Mand
W . 1 O M External
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W W .C O
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W .C W W Y . W W 0 Y .T W
W . 1 00Y M .T WA IRQ pin
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WW .100Y.C M.TW PortW 1
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WW mode O
W
WW .100Y.C M.TW
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.1 OM WW 00Y.CO .TW
W W Y .C O
W W WW internal 0 Y.C .T W W
W
W .10 0
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W .1 0 resistor
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W W.1 Y.COM W
C W W
WW .100Y. M.T
W EPROM W security 100Y
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W
W .100 OM
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W O W .C O W Y.C W
WW .100Y.C M.TW Short oscillator WWdelay.1counter 00Y M .TWEnabled or disabled W .100 M.T
O W O W . C O
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W W. 1
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W W W Y.CO .TW W WW 00Y.CO .TW
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W W W 00 .T W
W
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WW .100Y M .TW W
W . 100 O M .T W
W .100 O M.T
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WW .100Y.C M.TW
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WW .100Y.C M.TW W . 1 00Y M.T
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WW OSC1 .C .TW15 PA0 W W.100Y OM.TW
WW .100Y.C M.TW . 1 00Y2 M
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W
WW .100Y.C M.TW
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W W .C O
W
W
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W 00 Y .T W 0 0 .T .1 M
W W 00 .T W
W
W .100 O M.T PB3W.1 4
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WW .100Y M.T
W O W W .C O W
WW .100Y.C M.TW WPB2 5.100Y 12 .TW
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W .100 OM
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W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
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WW .100Y.C M.TW . 1 00Y 10 MPA5
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W W.1 Y.COM W PA7 8 WW. 0Y9.COPA6 W W WW 00Y.CO .TW
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W Assignments .C O W
WW .100Y.C M.TW Figure 1-2. WPin .100
Y
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W W
W .100 OM
WW .100Y . W Y W W 0 0
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W
W .100 O M.T W W.1
W .C
WW .100Y.C M.TW W .100
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W W
W O W C O
W O Rev. 4.0 W O
WW .100Y.C —M
W O W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
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W . 1 0
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WW .100Y .C W
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W W WW 00Y.CO .TW
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W W 00 .T W 0
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WW .100Y M .TW W
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W W.1 Y.COM W W + O W W WW 00Y.CO .TW
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WW .100Y. M.T
W W .100
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W W 0 .T W
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W W
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WW .100Y MC68HRC705KJ1.) M .TW W
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WW .100Y.C M.TW
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W W .C O
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WFigure .1-4 00and Figure
W 1resonant M.T 1-5 show a typical
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W W
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WW startup
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W W . C O
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W C O
W O W O
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W O W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
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WW .100Y .C W
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0 Y .CO .TW W W 0 0 Y.C .T W
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W W WW 00Y.CO .TW
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W Y W W 0
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WW .100Y.C M.TW WWVSS .100Y.C M.TW
W W .C O
W WW 00Y.MCU CO W W WW C3 00Y.CO .TW
W 00 Y .T W .T .1 M
W.1 Y.COM W W W.1 Y.COM W WW 00Y.COOSC1 .TW
W W 0 0 .T W .1
.CO .TW
W W.1 Y.COM W W W WW XTAL
0 Y
OSC1
OSC2
W .100 .T 0
W
W .100 O M.T W C OM W W.1 Y.COSC2 OM
W W 00 Y. C
.TW W W
1 0 0 Y .
M .T W W .1 0 0 M .TW
. 1 M . W O
W O W
WW .1XTAL .CO .TW WW 00Y
.C W
WW .100Y.C M.TW 00Y M.T
C4
M W . 1 O
O W O .C
W
WW .100Y.C M.TW C3 WW
00Y
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M .TW
27 pF
W . 1 O 27M pF W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WC2WC1 .100Y.C M.TW
W W .C O
W WW 00Y.CO .TW W WW V0SS0Y.CO .TW
W 00 Y .T W .1 M
W W
W
W .100 O M.T
W
W .100 1-4.OCrystal
Figure M.T Connections W W .1
with .COM
.C W Y . C W W 0Y W
WW .100Y M .TW W Oscillator
W . 100 Internal O M .TResistor Mask Option W .10 O M.T
W O WW .100Y. C
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TVW WW .100Y.C M.TW
W W .C O
W WW 00Y.CO .TSSW W WW 00Y.CO .TW
W 00 Y .T W .1 M
W.1 Y.COM W MCU
W W.1 Y.COM WC3 WW 00Y.CO .TW
W W
W
W .100 O M.T
W
W .100 OM
.T
OSC1
W W.1 Y.COM W
C W .C W
WW .100Y. W W .100
Y
M.TXTAL R
W 00
W.1 Y.COM W
.T
OSC1
OSC2
W O M.T R
W W .C O W
WW .100Y.C M.TW 10 MΩ W . 100
Y
M .TW W
OSC2
W .100 O M.T
W O W O W .C
Y
M.T
W
W O W C O
WW .100Y.
W O C4
W O W O
W
WW .100Y.C
O
.T WXTAL WW .100Y.C M.TW
VDD
WW .100Y.C M.TW
C3 M C4 W O C2 C1 W O
W
WW .100Y pF O
27.C
.T W W 27 W
pF
0 0 Y.C .T W WW .100Y.C M.TW
W. 1 OM W O
W OM VSS
WW .100Y.C M.TW
W W .C O
Y W
W 00
W.1 Y.COM Oscillator
.TFigure 1-5. Crystal .1
WConnections .C OM without W W.1 Y.COM W
W W
W W
. 1 00 M .TW Internal
W Resistor
W . 100
Y Mask
O M
Option
.T W
W .100 O M.T
W O WW .100Y .C
WW .100Y.C M.TW WW .100Y.C M.TW .T
W O W C O W W .C OM
WW .100Y . Y
WW .100Y.C M.TW M.T
W W
W .100 OM
WW .100Y . W Y W W 0 0
W O M.T
W
W .100 O M.T W W.1
W .C
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O Rev. 4.0 W O
WW .100Y.C —M
W O W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
1.4.2.2 Ceramic ResonatorW W.1 Oscillator .C OM
W W
M .TW W
W . 100
Y
O M .T W
W .100 O M.T
.CO .TW .C WW .1instead .C W
00Y WWTo reduce. 1 00Y
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W
0 Y.C .T W WW 00Y.C recommendations,
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manufacturer’s O M as the
W resonator O parameters determine the
WW 00Y.CO .TW WW 0component
Wexternal 0 Y.C W
values
T required W Wfor maximum0 0 Y .C .
stabilityT W
and reliable starting.
W .1 O M W .1 O M. W W .1
.C OM design should include all
.C The
WW .100Y load .C
capacitance values used in the oscillator Y circuit W
W
100Y M .TW M .TW W
W .100 O M.T
. O stray capacitances.
W O .C
W
W
W O W O
W O Mount
WWthe .resonator .C and.T components asW close as0possible Y.C to
.TtheW pins for startup
WW .100Y.C M.TW stabilization 1 00Y to minimize
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W
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W W Y .C O
W W WW 00Y.CO .TW W W 0 0 Y.C .T Wresistor of
W 00 .T approximately 2 MΩ is provided between OSC1
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W W.1 Y.COM W mask option. W W WW 00Y.CO .TW
W 00 .T W 0 0 .T .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T VSS
W W.1 Y.COM W
C W .C W
WW .100Y. Y W C3 .100 .T
MCU
W W .100 M.T
W O M.T W C O W W . C OM
W
WW .100Y.C M.TW WW .100Y. M .TW W Y
.100 OSC1 OM.T
W O W C
RESONATOR
W O WW .100Y .
WW .100Y.C M.TW WW .100Y.C M.TW .TW
CERAMIC
OSC1
M
OSC2
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .10OSC2 0Y.C M.TW
W O
W W
. 1 00 Y
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W . 1 O M W .1 0
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W O .C WW .100Y.C M.TW
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W
WW .100Y.C M.TW C3 WRESONATOR .1 00Y C4 M.TW
W W .C O
W
27 pF WW 00Y27.CpFO .TW W WWVDD 00Y.CO .TW
Y W
W 00
W.1 Y.COM W
.T .1 M W.1 Y.COM W
WW 00Y.CO .TW C2 C1WW
W W
.100 M.T
W
W .1 O M W .100 OM
.T
W O C W .C W
WW .100Y.C M.TW WW .100Y. M .TW W VSS .100Y M.T
W O W C O
W
WW .100Y.C M.TW
O
O W O W .C O
W
WW .100Y.C M.TW
Figure 1-6.
WW Ceramic .CResonator
00Y Resistor
Connections
.TW Mask Option WW with . 1 00Y M.T
W
Oscillator W . 1
Internal O M W C O
W O WW .100Y .
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C VM SS .TW WW .100Y.C M.TW
W W .C O
W WW 00Y.CO .C3 W W WW 00Y.CO .TW
W 00 Y .T W T .1 M
W.1 Y.COM W MCU W W.1 Y.COM W WW 00Y.CO .TW
W W 00 .T W .1
W 00 .T W.1 Y.COM W
OSC1 M
RESONATOR
W.1 Y.COM W WW 00Y.CO .TW

CERAMIC
W W W
OSC1
OSC2
W
W .100 O M.T R
W
W .100 OM
.T R
W W.1 Y.COM W
C W .C W OSC2 W
WW .100Y. W
M.T 10 MΩ
W .100
Y
M.T W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. C4 M.TW W .100
Y
M.T
O W O W .C O
W
W O W O
W
WW .100Y.C RESONATOR
O
T
CERAMIC
. W WW .100Y.C M.TWDD
V
WW .100Y.C M.TW
W W C3 Y.COM W C4 WW 00YC2 .COC1 .TW W WW 00Y.CO .T
W 00 .T W .1 M
W.1 Y.COM W
27 pF 27 pF
W W.1 Y.COM VSSW WW 00Y.CO
W W 00 .T W
W
.C W .Twithout W W.100
WW .10Figure 0Y 1-7.
M
W
.TCeramic W
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1Connections M
O W O
W
WW .100Y.COscillator .TW InternalW
W
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M W . 1 O M
W O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M W O Pin Functions
0 Y .CO .TW W W 0 0 Y.C .T W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
1.4.2.3 RC Oscillator W W.1 Y.COM W W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW .C WW .100Y. C
00Y WWRefer 1
to Appendix
00Y M .TA.
W MC68HRC705KJ1. M .TW
. 1 M W . O W O
W
0
O
Y.C1.4.2.4.TW WW .100Y.C M.TW WW .100Y.C M.TW
. 1 0 M External Clock W O W O
.1 M W O W O can be connected to the
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AnWexternal
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Y.C from.Tanother W WW .100Y.C
CMOS-compatible device
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1 OSC1 . 1
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W W. .C OM WW 00is Y CO
.possible W W W 0 .C
Ycrystal/ceramic .T W resonator or the
W 00 Y .T W W
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. 1 M W O W O
W
WW .100Y.C M.TW
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RCWoscillator
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0Yenabled. .TW WW .100Y.C M.TW
. 1 M
W W .C O
W 00 Y .T W .1 M
W W 0 0 .T W .1
W 00 .T W.1 Y.COM W .CO .TW
M
W W.1 Y.COM W W MCU WW
W 0 0 Y
W
W .100 O M.T
W
W .100 OM
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W W.1 Y.COM W
C W .C W
WW .100Y. W W .100
Y
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W .100 .T
OSC1
OSC2
W O M.T W C O W W . C OM
W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
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O W O W .C O
W
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C CMOS .TW
EXTERNAL WW .100Y.C M.TW
M CLOCK
WW 00Y.CO .TW
W W Y .C O
W W WW 00Y.CO .TW W
W 00 .T .1
Figure 1-8.OExternal
M Clock Connections .1 M
W W.1 Y.COM W W W Y .C W W WW 00Y.CO .TW
W 00 .T W 00 .T .1 M
W.1 Y.COM W
1.4.3WRESET W W.1 Y.COM W WW 00Y.CO .TW
W
W
W .100 O M.T
W
W .100 OM
.T .1
WW 00Y.CO .TW
M
W Y .C W W W 0 Y .C T W W
W 00
W.1 Y.COinternal
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W .10 Opin M. the MCU to aWknown
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W.1 startup CO
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M An
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V pulls the W
W W
. 1 00 M .TW W
W . 00
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W RESET
O pin high. A steering between the RESET and
WW DD.100Y.
V C
WW .100Y.Cany M RESET.TW pin voltage WWwhen . 1 0Y.C is removed
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W O W .C O
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WW .100Y.contains CO WW trigger 0Yto .Cimprove TW WW as 0Yinput. W
M .T anWinternal Schmitt
W . 1 0
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W . 1 0an
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WW .100Y.C M.TW
to Section 8. Resets and WWInterrupts 1 00Y M .TW . 100
Y
M .TW
W . O W O
WW 00Y.CO .TW
WPP WW .100Y.C M.TW WW .100Y.C M.TW
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W W. 1
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Y W
W 00
W.1 TheYexternal
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W .C W W W Y
00the CPU. T W PP W 0
10program .T
W
W
00
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Y.CEPROM W register. Y. C 00Y W
WW the 1 00user M .TW and mask W option .100 (See M .TW 2. Memory
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W O M.T
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W5. External
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WW The.1LEVEL .CO in.T Wmask option WWregister Y.C
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W interrupt 00
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W W
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W . 100 O M .T W
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W .C O W Y .C W W W 0 Y .C
WW .100Y M.T
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WW .100Y.C M.TW W .100
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W O W C O
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WW .100Y.C —M
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W O M
W Y .C W
W 00 .T
W W.1 Y.COM
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W . 1 0
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WW .100Y .C W
W O M.T
M WW 00Y.CO .TW
0 Y .CO .TW W
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W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
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W .100IRQ/V OM
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W
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W noise Y .
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W W.PA0–PA3 Y
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W Y .C W W W
interrupt Y
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0 .T W W 0 0
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W.1 Y.COM W .1 M
WW 00Y.CO .TW W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W .1 1.4.5OM
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WW .100Y M.T
W W .100 M.T
W 100
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W O W C O W .C
WW .100Y.C M.TW
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WW .100Y.C M.TW
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W .100 bidirectional
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WW .100Y.C M.TW WW .100Y. M .TW W .100
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W O W O
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WW .100Y.C M.TW
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W W 00 .T W
W
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WW .100Y M .TW W
W . 100 O M .T W
W .100 O M.T
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WW .100Y.C M.TW
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W W .C O
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W W
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W .100 OM
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W W.1 Y.COM W
C W .C W
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W W .100
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W.1 Y.COM W
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W O W O W W .C O
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W O W C O
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WW .100Y.C M.TW
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W O W O
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WW .100Y.C M.TW
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W O W O
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WW .100Y.C M.TW
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W O W O
W
WW .100Y.C M.TW
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W W .C O
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W W 00 .T W
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WW .100Y M.T
W O W .C O W
W W .100
W O W C O W W .COM
.C W Y . W W 0Y
WW .100Y M.T
W W .100 M.T W.1
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W O W W .C O W
WW .100Y.C M.TW W .100
Y
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W W
W O W C O
W O W O
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W O W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
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WW .100Y .C W
W O M.T
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M WW 00Y.CO .TW
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0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
Data Sheet — MC68HC705KJ1W W.1 Y.COM W W
M .TW W
W . 100 O M .T W
W .100 O M.T
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. 1 M W O W O
W
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W C O W .C W W Y W
W Y. W W .100
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W 00 .T
W .C .TW
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W
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W O W O
W
WW .100Y.C M.TW
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W W .C O
W
• W W
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Y .CO (FigureW 2-1) W WW 00Y.CO .TW
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W 00
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W.1 ofY.the C
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M
W W W 0 .T W W 0 0
W 00 .T W.1 of:
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W W.1 Y.COM W • Description
W Y .C W W WW 00Y.CO .TW
W
W .100 O M.T
W
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W Y .C W W 0 Y .C T W W 0 0 Y
W 00 .T 0 . .1 read-only M
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W W
W
W .100 O M.T
Wmemory/one-time
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W Y.C W – Mask
W W option 0 Y .C
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W 00 .T 0 . .1 M
W W include: 00 .T W
W
W .100 O M.TMemory features W.1 Y.COM W W W.1 Y.COM W
.C W
WW .100Y W
M.T • 1232 Bytes
W of User
W .100 EPROM, O M.TPlus Eight BytesWfor
W .100 Vectors
WUser OM
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W O C .C
WW .100Y.C M.T•W 64 BytesWof User.1RAM
W 00Y
.
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Y
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W O W O
W
WW .100Y.C M.TW
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W O W O
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W.1 OM WW 00Y.CO .TW WW 00Y.CO .TW
WW .100Y.C Accessing M. T W an W
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M
W O W C OM W .C
W W Y .C operation.
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1
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0 0 Y .
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M .T W in this W
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. 1 0Y
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0 M .TW
. 1 M are shaded. WW . O W O
W
WW .100Y.C M.TW
O
W 00Y
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W W .C O
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WMemory
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OM W.1 Y.COM W W W.1 Y.COM W
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W W
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Y
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W . 0
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W .100 O M.T
W O a reserved location can Y.C unpredictable effects on
W MCU .C
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Y W
WW .10In0Y .C
Figure 2-2 .TW and in registerWWfigures . 100in this O M .TW reserved
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W
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M W W C
W
WW .1marked .CO the .TWword Reserved WW or .with .C
00Ythe letter R.W WW .100Y. .TW
00Y with M W 1 O M .T W O M
W
WW .100Y.C M.TW
O
W O W O
2.4 Memory Map W
WW .100Y.C M.TW
O
W O
W .CO2-1. .TW WW 00Y.CO .TW WW .100Y.C M.TW
WW See.1Figure 0 0 Y W .1 M
W W .C OM
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100
W O W C O W W .COM
.C W Y . W W 0Y
WW .100Y M.T
W W .100 M.T W.1
0
W O W W .C O W
WW .100Y.C M.TW W .100
Y
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W W
W O W C O
WW .100Y.C M.TW WW .100Y. M.TW
W O Rev. 4.0 W O
W O W
MOTOROLA WW .100Y.C Memory .TW WW 21
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
Memory .TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y.CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
W .100 MT
PORT A DATA .REGISTER (PORTA) $0000
M .TW W
W . 100 O M .T W C O
.CO .TW WW .100Y.C M.TW WW .10PORT 0Y. B DATAMREGISTER .TW (PORTB) $0001
. 1 00Y M W O W O
WW .100Y.C
W O $0002
0 0 Y.C .T W WW .100Y.C M.TW UNIMPLEMENTED
M .TW
. 1 M W O W O $0003
WW 00Y.CO .TW WW .100Y.C M.TW WW DATA 0 0 Y.C .T W
.1 DIRECTION REGISTER M A (DDRA) $0004
.1
WW 00Y.CO .TW
M W W Y .C O
W W WW 00Y.CO .TW
W 00 .T DATA.1DIRECTION REGISTER
OM B (DDRB) $0005
W .1
. C O M W W.1 Y.COM W W W Y .C W
WW .100Y W W .100 M.T
W 00 .T $0006
W O M.T W .C O W W.1 UNIMPLEMENTED
Y .C OM
W
WW .100Y.C M.TW WW .100Y M .TW W . 100 M .T $0007
O W O W O
.C REGISTER
W
WW .100Y.C M.TW WW .100Y.C M.TW WW AND
TIMER STATUS
.1 00Y
CONTROL
M .TW
(TSCR) $0008
W O WWCONTROL
TIMER O (TCR)
REGISTER $0009
W
WW .10$0000
O
0Y.C M.TW WW .100Y.C M.TW W . 1 0 0Y.C M.TW
IRQ STATUS W AND CONTROL REGISTER O (ISCR) $000A
W W
↓ Y .C O
W I/O REGISTERS W WW 00Y.CO .TW W W
1 0 0 Y.C .T W
W .10 0 M.T .1 W. OM $000B
W C O 32 BYTES
W W .C OM W Y .C W
WW $001F Y. W Y W W UNIMPLEMENTED .100 .T ↓
W 100
.$0020 O M.T
W
W .100 O M.T W W .C OM
WW .100Y. C Y W
WW .100Y.C M.TUNIMPLEMENTED .TW W .100 M.T
W $000F
W↓ O W O M PULLDOWNW W .C O
WW .100Y.C M.TW W REGISTER .TW $0010
PORT
WW $00BF.100Y.C M.TW 160 BYTES
. 0Y A (PDRA)
10PORT M
W O W O
WW .100Y.C M.TW
W O PULLDOWN REGISTER B (PDRB) $0011
WW$00C0 .100Y.C M.TW WW .100Y.C M.TW
W W .C O RAM
W WW 00Y.CO .TW W WW 00Y.CO .TW $0012
Y W
W ↓ .100
W
.T
OM64 BYTES W.1 Y.COM W
UNIMPLEMENTED
W W.1 Y.COM W ↓
.C W
W
W$00FF .100Y M.T
W W
W .100 O M.T
W
W .100 O M.T $0017
W O W .C
WW .100Y.CUNIMPLEMENTED
$0100
.TW WW .100Y.C MEPROM .TW PROGRAMMING W REGISTER Y
.100 (EPROG)
W
M.T$0018
M W O W C O
↓ W
WW .100Y.C 512M
O
TW
BYTES
. WW .100Y.C M.TW WW .100Y. M
W
.T$0019
W O W O ↓
$02FF UNIMPLEMENTED
W WW .100Y.C M.TW
$0300 .1 OM W O W O $001E
↓ W
WW 00Y.CEPROM .T W WW .100Y.C M.TW RESERVED WW .100Y.C M .TW
$001F
. 1 M W O W O
WW .100Y.C M.TW
W 1232O BYTES
$07CF WW 0 0 Y.C .T W WW .100Y.C M.TW
$07D0 WWW
.1
.C OM
W WW 00Y.CO .COP W W W(1)W 00Y.CO$07F0 .TW
Y W T REGISTER (COPR)
↓
00
W.1UNIMPLEMENTED OM
.T W.1 Y.COM W W.1 Y.C$07F1 OM
W W 0
.C
30YBYTES
0 .T W W W
1 00 MASK
M .T W
OPTION REGISTER W (MOR)
. 1 0 0 M .TW
. 1 M W . O W O
$07ED
W WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y.C $07F2
M.T
W
$07EE .1 M W O RESERVED W C↓ O
W
WW .12 0BYTES
TEST ROM
0Y.C M.TW
O
$07EF W $07F7 O
W O W
WW .100YTIMER .CO .TW WW .100$07F8 Y.C W
$07F0 WW .100Y.C M.TW INTERRUPT
M VECTOR HIGH
W O M.T
W O C
↓
W ANDYEPROM
REGISTERS
WW 16 BYTES .CO .TW WW .100Y .C INTERRUPT
TIMER .TW VECTOR LOW WW .10$07F9 0Y. .TW
.1 00 M M W O M
W O W
WW .1EXTERNAL .CO .TW VECTOR HIGH WW .1$07FA 00Y
.C W
$07FF
WW .100Y.C M.TW 00Y INTERRUPT M W O M.T
O W O .C
W
WW .100Y.C M.TW WW .EXTERNAL 00Y
.C INTERRUPT .TW
VECTOR LOW WW $07FB . 100
Y
M .TW
1
WSOFTWARE O M VECTOR HIGH W $07FC Y.C W O
W O .CINTERRUPT .TW
WW .100Y.C M.TW WW SOFTWARE . 1 00Y INTERRUPT M .TW W . 100 M
O W O VECTOR LOW W $07FD .C O
W
WW .100Y.C M.TW WW .100RESET Y.C VECTOR W
.THIGH WW $07FE 1 00Y .T
W O W C O M W W .
.C OM
WW .10RESET . Y
WW .100Y.C M.TW 0Y VECTOR M.T LOWW W $07FF.100
W OM
WW .100Y . W Y W W 0 0
.100
Note 1. Writing to bit 0 of $07F0 clears the COP watchdog. W
W O M.T W O M.T W W.1
.C W Y .C W W
WW .100YFigure 2-1.WMemory Map
M.T
W .100 M.T
W O W C O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W
22 WW .100Y.C Memory .TW WW MOTOROLA
W OM
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW Memory
M W O Input/Output Register Summary
. 1 00Y M W O
W O
2.5 Input/OutputWRegister
W
W Y CO
.Summary W W WW 00Y.CO .TW
W 0 .T
O M.T W .1 0
.C OM W W.1 Y.COM W
.C W W
00Y Addr..T
W Register Name W .100
Y
7 .T
M
W .1400 O3M
.T 2
W.1 Y.COM W
Bit
O 6 5 W 1 Bit 0
W W Y .C W W 0 Y .C W
W .10 .T
.100 M.T
W
Port A Data Register W 100 PA7
.Read: OM PA6
.T
PA5 WWPA4 C OM PA2
W C O W .C W Y . PA3
TW
PA1 PA0
W 00 Y. $0000 .TW W
(PORTA) Write:
1 0 0 Y .T W . 1 0 0 M .
.1 M 66. W
. OM W .CO .TW
WW 00Y.CO .TW See page W
W Reset: 0 0 Y.C .T W WWUnaffected 1 0 0byYreset
W .1 O M W .1
C OM 0 W W .
.C OM
WW .100Y .C
.T W
Port B Data Register W W Read:
1 0 0Y
0.
M .T W Refer to Section
W 7.
. 1 00PB3Y
M .TW Refer to Section 7.
W OM W . O Parallel I/O
WW 00Y.CO .TW
Ports PB2 Parallel I/O Ports
W .C
$0001
W (PORTB) W Write: Y . C W (PORTS)W (PORTS)
W .100
Y
M.T
W 00 .T W.1by resetY.COM W
W .C O See page 69.
W
Reset:W.1 Y.COM W W
Unaffected
WW .100Y M .TW W
W . 100 O M .T W
W .100 OM
.T
W O C W . C
WW .1$0002 00Y
.C W
.TUnimplemented W W
1 00Y
.
M .TW W . 100
Y
M .TW
M W . O W O
W
WW .100Y.C M.TW
O
W O W O
WW $0003
W
0 Y.C
O
.T W
Unimplemented WW .100Y.C M.TW WW .100Y.C M.TW
0 O
W.1 OM W O W
WW .100Y.C M.TW
W W .C O
W Read: WW
W Y .CO .TW W WW 00Y.CO .TW
Y 0
00 DDRA7 .10 W.1 DDRA2
W Data Direction Register
.T A M
W.1 Y.COM (DDRA) W DDRA6 M
ODDRA5 DDRA4 DDRA3
W
DDRA1
.CO .TW
DDRA0
$0004
W Write: W Y .C W W 0 Y
W .100 M.pageTW66. Reset: W 0 00 .T .10 0 OM0
W O
See
W.1 0 Y.COM 0 0 0WW .C 0
WW .100Y .C
.T W Read: W0 W
1 0 0 M . W
TSection 7. W .1 00 Y
M .TW
W Data Direction M B
ORegister W . 0 Refer
O to
WWDDRB2 .CORefer to Section 7.
W .C W W Y .C W W 0 0 Y .T W
W .100
Y .T Write: W 00 M.T
Parallel I/O Ports DDRB3
W.1 Y.COM
Parallel I/O Ports
$0005
W . C O M
(DDRB)
W W.1 Y.CO(PORTS) W W (PORTS)W
WW .100Y See page 69.
.T W W . 1 00 M .T W . 1 00 M.T 0
M Reset: 0 W 0 0 O 0 0 W 0 C0 O
W
WW .100Y.C M.TW
O
W O W O
$0006WW
W
0 Y.C
O
Unimplemented .T W WW .100Y.C M.TW WW .100Y.C M.TW
0
W
W 00
W.1Unimplemented OM
.T W.1 Y.COM W W W.1 Y.COM W
. C W
W W .100 M.T
$0007
W .1 00Y M .TW W
W . 100 O M .T W C O
W O WW .100Y .
WW .100Y.C Read: .TWTOF WW .100Y.C M.TW M .TW
O M RTIF W O 0 0 W .C O
TimerW W and Control
Status
W Register 0 Y.C Write: .TW WW TOIE 0 0Y.CRTIE M.TW WW RT1 . 1 00Y RT0 M.TW
1 0 . 1 W O
$0008
W W . (TSCR)
.C OM WW 00Y.CO .TW
TOFR RTIFR
W W 0 Y.C TW
W See page
1
Y
83.
00 Reset:M.T 0 W 0 W 0 .1 0 M 0 0 W 1.1 0 1 OM.
. W O . C
WW Register .CO .TW TCR6 WWTCR5 100Y
.C TW
W
TCR2 W TCR1.100YTCR0 M.T
W
WCounter
Timer . 1 00Y Read: MTCR7 W . TCR4
O M .TCR3 W O
$0009
WW
W (TCR) YWrite:
0 .CO .TW WW .100Y.C M.TW WW .100Y.C M.TW
0 O
W.184. Reset: OM 0
See page 0W 0Y.CO 0 W WW
W
00Y.C M.TW
WW .100Y.C M.TW
0
WW 1 0 0 M .T 0 0
. 10
0WW. 0 .COIRQF W O
IRQ Status and
W
W Read:
WControl 0 Y .COIRQE .TW 0 W 0 0 Y .T W 0 W0W .1000Y.C M.TW
.10Write: OM .1 R M IRQR W O
WW 00Y.CO .TW
$000A Register (ISCR)
See W
page
W 57. Y .C W W W W 0 0 Y.C .TW
W .1 00
Reset: 1 M.T 0 0 . 10 0M 0 0 W . 10 OM
W O
W
WW .100Y.C M.TW
O
W W .C O = Unimplemented
W W W Y .CO U.=TUnaffected W W WW 00Y.CO .T
W 00 Y .T W R = Reserved 0 0 .1 M
W W (Sheet 00 .T W
W Figure
W .1002-2. I/O O
.T
Register
M Summary W.1 1Yof.C2) OM W W.1 Y.COM
.C W W
WW .100Y M .TW W
W .100 O M .T W
W .100
W O WW
W O W O
W O Rev. 4.0 W O
W O W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y . C W
W O M.T
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 4 Y.COM3 W 2
Addr. W
Register Name W.1 Y.COM Bit 7 W 6 W
5 1 Bit 0
.T W W . 1 0 0 M .T W .1 00 M .T
OM W O
Y.C
$000B
W WW 00Y.CO .TW
Unimplemented
W WW .100Y.C M.TW
0 0 ↓ .T . 1 M
W
W .10 0 M.
$000F
O
T Unimplemented .1
W .C OM W W.1 Y.COM W
W Y.C W W Y W W 00 .T
W .100 O M.T
W
.C W .C
W
100Y M
W RegisterW
.TPulldown Port A Read: . 100
Y
M .TW W
W .100 O M.T
W . O W
(PDRA)W Write: PDIA7 .C O PDIA6W PDIA5 WW Y .C PDIA2W
WW .100Y.C M.TW See pageW68.
$0010 PDIA4 PDIA3 PDIA1 PDIA0
W . 1 00Y
O M .T W .100 O M.T
O 0 .C
W
Reset: 0 0 0
WW 0
. 1 00Y M
0 W
.T
0 0
W O W O
WW .100Y.C M.TW
W O Read:
WW .100Y.C Pulldown .T WRegister Port BWW .100Y.C M.TW Refer to Section
W W $0011Y.COM W (PDRB) Write: W W Y .C O
W W
7. W
W PDIB3 0 Y.CO .T W
Refer to Section 7.
W .10 0 M.T
Parallel I/O Ports
.1 0 PDIB2 Parallel I/O Ports
W
W .100 O M.T See page 71. W C O (PORTS) W W .C OM (PORTS)
WW .100Y.C M.TW WW 0Y. .TW0 W 1 00Y .TW
Reset: W0.10 0OM . M
WW .C O
W W Y .C W
0
W WW 00Y.CO .TW
0 0 0 0
W 00 Y .T W 0 0 .T .1 M
W W
W $0012.100
W O M.T
Unimplemented W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW ↓ .100Y. M.T
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W .C O W
WW .100Y.C M.TW
$0017 Unimplemented
WW .100Y M .TW W .100 M.T
O W O W . CO
W
WW .100Y.C M.TW Read: W0
W Y.C .TW 0 WW .100Y M.T
W
W . 100 0 O M W O
WW EPROM O
Programming
Y.C (EPROG) WW .R100Y.C R M.TWR
0 0
WW ELAT Y.C .TW
W
$0018 . 1 00Register M .TW Write: R W . 100 MPGM O M EPGM
W O W
W 0 00Y.C0 O W Y .C W
WW .100YSee .C page 26. .TW Reset: 0W .TW0 0W 0.100 0 OM.T 0
M W . 1 O M W C
W
WW .100Y.C M.TW
O
W O W O
$0019 WW
W Y.C
O
Unimplemented
0 .T W WW .100Y.C M.TW WW .100Y.C M.TW
0
↓ W W.1 Y.COM W WW 00Y.CO .TW W WW 00Y.CO .TW
W
$001E
W 00
W.1Unimplemented OM
.C W
W W
.1 00Y M .TW W
W . 100 O M .T W
W .100 O M.T
W O W Y.C R .TW R WR W .1R00Y .C TW
$001F WW .10Reserved 0Y.C M.TW R W R . 1 R00 M W ORM.
W O
W
WW .100Y.C M.TW
O
W W .C O
Read: W WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 Y .T W .1 M
$07F0 W.1(COPR)Y.C
COP Register OM
Write: W W.1 Y.COM W WW 00YCOPC .CO .TW
W W W
W See page 0
032.
W.1 YReset: OM U
.T W
UW
.100 U OM.TU W W.1 Y0.COM W
.C U W .C W U U
W W
. 1 00 Read: M.TW W
W .100
Y
O M .T W
W .100 OM.T
WW(MOR)00Y.CO SOSCD W .C
Mask Option W Register
.TW
EPMSEC W W
OSCRES
. 1 0Y.C M
0SWAIT PDI.TW PIRQ WLEVEL . 00Y
1COPEN M .TW
$07F1 .1 Write: M W O W O
W27. Y.CO
See page
WW .10Reset: 0 .T W WW .1Unaffected 0 0Y.C by reset .TW WW .100Y.C M.TW
OM M WW 00Y.CO .TW
W W Y .C W W WW 00Y.CO .TW W
W 00
W.1 Y.COM = Unimplemented
.T 1
W=.Reserved .C OM U = Unaffected W W.1 Y.COM W
W W
W Y W .100 M.T
R
W . 1 00 M .TW W
W . 100 O M .T W C O
W O Y.C WW .100Y .
WW Figure 00Y
.C I/O Register .TW WW (Sheet 100 2 ofO2)M.T
W .T
W . 1 2-2.
O M Summary
W .
C W W .C OM
WW .100Y . Y
WW .100Y.C M.TW M.T
W W
W .100 OM
WW .100Y . W Y W W 0 0
W O M.T
W
W .100 O M.T W W.1
W . C
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M W O RAM
0 Y .CO .TW W W 0 0 Y.C .T W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
2.6 RAM W W.1 Y.COM W W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW Y.C W Y. C Wuser RAM and the stack
00Y WWThe .64 1 00addresses M .T W $00C0 to
from W$00FF .
serve
100 as both M .Tthe
. 1 M W Before
RAM. O
processing an interrupt, W
W the CPU O
.C five.Tbytes
uses
W Y.C
O
W WW 0Y.Cof the .TWregisters.W 00Y W of the stack to save
1 0 0 .T the . 1 0
contents M CPU During a. 1subroutine O Mcall, the CPU uses two bytes
.
WW 00Y.CO .TW
M W O
.Cstore WW 00Y.C W
WofWthe stack . 1 0 0 Y to M .T
theW return W
address. The . 1 stack pointer
M .T decrements when the
W . 1 O M W C O W W . C O
.C CPUW stores .
aYbyte on the
.TW stack and increments Y the CPU
when W retrieves a byte from
W
. 100Y M .TW W
the stack.
W . 100 O M
W
W .100 O M.T
W O WW .100Y .C
WW .100Y.C M.TW WW .100Y.C M.TW M.T
W
W O W O
W O NOTE: Be careful
WW .when C
Y.using nested W subroutines WW or multiple Y.Cinterrupt .TW levels. The CPU
WW .100Y.C M.TW may overwrite 1 00data in M
the
.TRAM during a subroutineW . 100 or during O M the interrupt stacking
W W Y .C O
W 00 .T operation. .1
OM .1 M
W W.1 Y.COM W W W Y . C W W WW 00Y.CO .TW
W 0 .T
W .100
W2.7 OM
.T 0
C
EPROM/OTPROM
. W
W W
. 1 00Y M .TW W
W . 100 O M .T W
W .100 O M.T
W O .C WWof erasable, Y. C
WW .100Y.C M.TW An MCUWwith a quartz
W
1 00Y window M
W 1240 bytes
.Thas .100 programmable M .TW ROM
W O .
WquartzYwindow O allows EPROM erasure W W .C O
W .C W (EPROM). W
The .C W W 0
with
0 Y ultraviolet .T W light.
W
W .100
Y
O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C TW an opaque
WW .100Y.NOTE: WKeep the quartz
M.T MCU. AmbientWlight
W window Y
.100 covered M.with
W material 0
0except
W.1 Y.COM W
when .Terasing the
W O W .C O W
WW .100Y.C M.TW
can0Y affect MCU operation. W
W . 10 M .TW W .100 O M.T
O W O .C
W
WW .100Y.C M.In TW an MCU without WW the.1quartz .C
00Y window, .TWthe EPROM WW cannot .10be 0YerasedMand .TWserves
W O M W O
W
WW .100Y.C M.TW
O as 1240 bytes ofW
W one-time 00Y
.C
programmable
.TW ROM (OTPROM). WW .100Y.C M.TW
.1 M W O
W .C O The following addresses WW are Y .COEPROM/OTPROM W W W 0 Y.C W
W W
. 1 00 Y
M .T W W
W . 10 0 user
O M .T locations:
W .1 0
O M.T
W O WW .100Y. C
WW .100Y.C M•.TW $0300–$07CF WW .100Y.C M.TW M .TW
W O
W O W
WWused.1for .CO .TWinterrupt and WWreset.1vectors 00Y
.C W
WW .100Y.C M W
• .T$07F8–$07FF, 00Y user-defined M W O M.T
O W O Y. C
W
WW .100Y.CTheM COP.TWregister (COPR) WW is.1an 00Y
.C
EPROM/OTPROM .TW WW at address
location . 100 $07F0. M .TW
W O M W O
W
WW .100Y.The CO
W W .C
M option registerW
Omask (MOR)
W is Y an O
.CEPROM/OTPROM W W WW at0address
location
0 Y .CO .TW
W Y
00 $07F1. .T W W 0 0 .T .1 M
W W 00 .T W
W
W .100 Programming
O M.T W.1 Y.COM W W W.1 Y.COM W
2.7.1 EPROM/OTPROM .C W W 00 .T
WW .100Y M.T
W O W W .C O W
WW .1The .C Wprogram the Y W W .100 .T
W
00Ytwo ways
O M.T
to W EPROM/OTPROM
W .100 O M.Tare: W W .C OM
C WWbits in.10the .C W 00Y W
WW .10•0Y.Manipulating M .TW the control 0YEPROM M .Tprogramming Wregister.1to
W O M.T
W O the EPROM/OTPROM W a.C O W .C
WW .100Y.C M.TW
program WW .1on 00Y
byte-by-byte
M .TW basis W W.100Y OM.TW
W • Programming O W
WW .100Ywith .CO the .M68HC705J W 00Y
.C W
WW .100Y.C M.TW
the EPROM/OTPROM TW In-Circuit
W
W O M W . 1 O M.T
W Simulator O (M68HC705JICS) available from Motorola
WW .100Y .C
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W .100 O M .T W
W .100
W O WW
W O W O
W O Rev. 4.0 W O
W O W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
2.7.2 EPROM Programming W W.1 YRegister .C OM
W W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW .C programming WW(EPROG) Y. C W control bits for
00Y WWThe .EPROM 1 00Y M .TW register
. 100 contains M .Tthe
. 1 M W
programming O
the EPROM/OTPROM. W O
W
0 Y.C
O
0
. 1
WW 00Y.CO .TW
M W CO
.$0018 WW 00Y.CO .TW
WW Address: 0 0 Y .T W W .1
.1 M W.1 YBit.C7OM 6W WW4 00Y.C OM
WW 00Y.CO .TW W W
1 0 0 .T 5 W . 1 3
M .T2W 1 Bit 0
. 1 O M W . O M W .C O
W
WW .100Y.C M.TW WWRead:.100Y0.C M.0TW 0 WW0 .100Y0 M .TW MPGM
ELAT EPGM
W O W
Write: C O R R WR W RY.C O
W .C W W Y . W W 0 .T W
W .100
Y
M.T
W 00 .T 0 W.
10 0 OM0
W .C O W W.1 0 Y.COM0 W 0
Reset:
W 0 Y .C W 0 0
W Y W W 0 0 .T W 0
=.1Reserved
.T
W 00 .T W.1 Y.C OM
= Unimplemented R M
W W.1 Y.COM W W W W WW 00Y.CO .TW
W 00 .T W 10 0 .T .1Register (EPROG) M
W.1 Y.COM W W W.Figure Y .
2-3.
C OMEPROM Programming
W WW 00Y.CO .TW
W W
W
W .100 O M.T
W
W .100 OM Bit
.T
W W.1 Y.COM W
C ELAT — W
EPROM Bus . CLatch
WW .100Y. M.T
W W 0Y
.10bit Mthe.TW W
W .100 for O M.T
W O This read/write W latches
C O address and data
W buses .C EPROM/OTPROMW
WW .100Y.C M.TW programming. WW .Clearing Y. .TW bit automatically W 00Y the EPGM M.T bit.
W 100 the
O M ELAT W .1clears
C O
W O Y.C cannot WW Y . W clears
WW .100Y.C M.TW EPROM/OTPROM WW .100data M .TW be read while the ELAT . 100 bit isOset. M .T
Reset
W O W
W O
WW .100Y.C M.TW 1 = Address
the ELAT bit.
W .C O WW and data.buses
Y CO configured W W WW 00Y.CO programming
for EPROM/OTPROM W
W W
. 1 00 Y
M .T W W
the EPROM
W . 10 0
O M .T
W .1 O M.T
W O
WWand .data .C WW operation Y.C .TW
WW .100Y.C M.TW 0 = Address 1 00YbusesM .TW
configured for normal
W . 100 O M
W O
W
WW .100Y.C M
O MPGM — MOR Programming
.TW WW .100Y.C Bit .TW WW .100Y.C M.TW
O This read/write bit W O M WIRQ/VY.Cpin O to the
W
WW .100Y.C Mmask .TW option register. WW .100Y.C M.TW
applies programming power from WW the
.1 00 PP M .TW
W O
W O
WW voltage
WReset Y .CO MPGM.
clears
WW .100Y.C M.TW
WW .100Y.C M.T1W = Programming .1 00 appliedMto W
.TMOR
W W .C O 0 = Programming
W
W
Wvoltage Y
not
O
.Capplied W
to MOR W WW 00Y.CO .TW
Y W 0 .T
W 00
W.1 Y.EPGM
.T
OM — EPROM Programming
0
C W
W W
.1 00 M .TW W
W . 100Bit OM.T
W
W .100 O M.T
W O .C from.Tthe Wto the0EPROM. .C
WW .100Y.C M.TW
This read/write bit applies
WW the 1
voltage
00Y M
W IRQ/VPPWpin . 1 0
Y
M
To.TW
.
W bit must O W O
W write
O the EPGM bit, theW ELAT .C be set already. Reset
WWclears Y.C
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.TW
WW .100Y.C 1 =MProgramming .TW Wvoltage . 1 00Y PP pin)
(IRQ/V M .T W
applied to EPROM W . 100 O M
W O
WW (IRQ/V
W .CO .TW W 00Y
.C W
WW .100Y.C0 = M .TW
Programming voltage . 1 00YPP pin)Mnot applied to W EPROM W . 1 O M.T
W O C
W
WW .1Writing .CO .TW W 0Y.C bitsMwith .TWa single instruction WW .100Y. .TW
NOTE: 00Y logic M 1s to both the W ELAT and . 1 0EPGM W sets ELAT O M
W O
Y.C EPGM. WW
W
0Y.by CO TW instruction. WW .100Y.C M.TW
WW and 0 0clears .T WELAT must be set.1first 0 a separate
M . O
W
WW .100Y.C M.TW
WW Bits 0 0 .T W 1
W.1
[7:3] — Reserved
OM W. OM W O
W
Take
W theYfollowing .C O steps to program
W WW Y CO
a byte of .EPROM/OTPROM:
W W WW 00Y.CO .TW
W 0 .T
W
W
0
1. .10Apply OM
the .T
programming voltage,WV.1PP 0 , to the IRQ/V
.C OM PP pin. W W.1 Y.COM W
.C W W
W
W 2. .1Set 00Ythe ELAT M
W
.Tbit. W
W . 100
Y
O M .T W
W .100 O M.T
W O Y.C WW .100Y .C
WW3. Write .C
00Yto anyM .TW WWaddress. 100 .TW .T
W . 1 O
EPROM/OTPROM W .
C O M W W .C OM
Y.C W . W Y
WW . 0 EPGM
4. Set10the
Mbit .TW and wait forWa time,.t1EPGM
W
00Y .
O M.T
W
W .100 OM
W . C O W Y .C W W W 0 Y .C
5.W Clear0the Y ELAT bit. W W .100 M.T 0
W
W .1 0 O M.T W .C O W W.1
W
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M W O Mask Option Register
. 1 00Y M W O
W O
2.7.3 EPROM Erasing
W .1
O M.T W W .1
.C OM of an EPROM bitWisWlogic Y.Erase
M
CO theTW
Y .C W W The erased
0 20 Y state .T W W 1 0 00. . EPROM by exposing it to
. 1 00 M .T . 1 M W . O M
W Y.C
O
W WW
15WWs/cm .of COultraviolet
0Ylight
light with aW
TWone inch from
wavelength
W the EPROM. .Cof 2537.Tangstroms.
00Y DoMnot W Position the
1 0 0 M .T ultraviolet. 1 0 source
M . W . 1 O use a shortwave filter.
. W O
.1
WW 00Y2.8
M
.COMask WOption WW 00Y.CO .TW
Register W WW 00Y.CO .TW
W
W .1 O M. T
.C W W 00 .T that controls the
WW .100Y M.T
W W mask.1option
The 00 register M.T (MOR) is an EPROM/OTPROM W.1 Y.COMbyteW
W O W .C O W
WW .100Y.C M.TW WW options:
following
.100
Y
M.T
W W .100 M.T
W O W O W W .C O
WW .100Y.C M.TW •WW COP watchdog Y.C (enable .TW or disable) W .100
Y
M.T
W
W . 100 O M W C O
W O WW .100Yonly .
WW .100Y.C M.TW
W
• WExternal
. 1 0Y.C pin
0interrupt M
W
.Ttriggering (edge-sensitive .TW and
orMedge-
W O
W O WW 00Y.CO .TW
level-sensitive) WW .100Y.C M.TW
WW .100Y.C M.TW W . 1 M
W O • Port W CO
Y.interrupts WW 00Y.CO .TW
WW .100Y.C M.TW WWA external 0 .T W(enable or W disable)
W O W. 1 0
.C OM (enable or disable) W W.1 Y.COM W
.C • Port W
pulldown resistors W
W W
. 1 00Y M .TW W
W . 100
Y
O M .T W
W .100 O M.T
W O .C mode WW .100Y .C
WW .100Y.C M.TW
• STOP WW instruction
1 00Y
(stop
M .TWor halt mode) M .TW
W . O W O
W O
WW .C resistor W Y.C .TW
WW .100Y.C M.TW
• Crystal oscillator internal
. 1 00Y M .TW (enableWor disable) W . 100 O M
W O
WW
W (enable .CO or disable) WW .100Y.C M.TW
WW .100Y.C M.TW
• EPROM security .TW
. 1 00Y M W O
W O
WW delay
W .CO .or disable) WW 0Y.C M.TW
WW .100Y.C M.T•W Short oscillator 0 0 Y(enable T W . 1 0
W .C O W W.1 Y.COM W WW 00Y.CO .TW
W Y Take W the following W steps to 0program T
the
. mask option W register (MOR):
W
W .100 O M.T W .10
.C OM W W.1 Y.COM W
C W W, to the IRQ/V
WW .100Y. 1. W
M.T
Apply the programmingW .100
Yvoltage, .VTPP
M
W PP pin.
W .100 OM
.T
W O W C O W .C W
WW .100Y.C 2. .TW
Write to theW MOR. W Y. .TW W .100
Y
M.T
M W .100 O M W C O
W O3. Set the MPGM W
W bit and.1wait C a time,
.for tMPGM. WW Y. .TW
WW .100Y.C M.TW 00Y M .TW W . 100 O M
W O
W
WW .100Y.C M.TW
O4. Clear the MPGMW
W
bit.
00Y
. 1 M
W W .C 5.O Reset the MCU. WW
W 00 Y .T W 0 0 .1 M
W W 00 .T W
W
W .100 Address: O M.T $07F1 W.1 Y.COM W W W.1 Y.COM W
.C W 2W 1 00 Bit 0 .T
WW .100Y M.T
W7
Bit 6W 5 100
. 4
M.T 3 W.1 Y.COM W
W O W W .C O W
WW .100Y.C Read:
M .TW EPMSECW OSCRES
SOSCD
Y
.100 SWAIT OMSWPDI .TW PIRQ
W
W
LEVEL.100 COPENOM.T
W O W C W .C W
WW .100Y.C M.TW
Write:
WW .100Y. M .TW W . 1 00Y M.T
W O W C O
W
WW .100Y.C M.TW
Reset: O
WW .100Y.C M.TW
Unaffected by reset
WW .100Y. M .TW
W O Figure 2-4. Mask W Option Register O (MOR) WW W .C O
WW .100Y.C M.TW WW .100Y.C M.TW . 1 00Y M.T
W
O W O W .C O
W
WWSOSCD Y.CShort Oscillator .TW WW Bit .100Y
.C .TW WW .100Y .TW
.1 00— M Delay
W O M W O M
W
WW The.1SOSCD
O
0Y.C bitMcontrols .TW the oscillator WW stabilization 00Y
.C .TW The normal
counter. WW .100Y.C M.TW
0 . 1 M W O
W stabilization
W Y .C O
delay following reset or
W W WW exit fromY.stop
0 CO mode T W is 4064 tcyc W.W Setting
0 0 Y.C .T
10 . W.1 Y.COM
W SOSCD
W .100 enables O Ma.T128 tcyc stabilization W .delay.
.C O M W
WW 1 =.1Short .C
00Y oscillator W WW 0Y M.T
W W .100
W O M.T delay enabledWW.10 .C O W W Y.C OM
WW0 = Short .C W disabled Y W W 0 0
W .100
Yoscillator.Tdelay
O M
W
W .100 O M.T W W.1
W .C
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O Rev. 4.0 W O
WW .100Y.C —M
W O W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W
W .100
EPMSEC —OM
.T
EPROM Security Bit W W.1 Y.COM W
W Y .C W W 00 EPROM/OTPROM.
M .TW W
W 100 EPMSEC
The
. O M .Tbit controls accessW to.1the O M.T
.CO .TW .C WW .100Y. denied C
00Y WW .1010=YExternal M
W
.Taccess to EPROM/OTPROM M .TW
. 1 M W O
W Y.C
O
W
W
WW .010=0Y .CO access
External
.TW to EPROM/OTPROM WW .100Y.Cnot M .TW
denied
. 1 0 0 M .T M W O
W O .C
WW 00Y.CO .TW W
WOSCRES 1 00Y
—.C Oscillator
.TW Internal Resistor WW Bit.100Y M .TW
. 1 M The W . OSCRES O M
bit enables a 2-MΩ W
internal resistor O in the W oscillator circuit.
WW 00Y.CO .TW WW 1 =.1Oscillator 0Y.C M .T W W W 0 0 Y.C .T
0 internal resistor enabled . 1 M
W W.1 Y.COM W WW 0 = Y
Oscillator .CO internal W resistor W WW 00Y.CO .TW
disabled
W 00 .T W 0 0 . T .1 M
W W 0 .Tto logic 0 in devices W 1
W .100 T
M.NOTE: Program the
W.with10OSCRES bit
OMresistor. W.using low-speed
C OM crystal or RC
W .C O W
oscillators Y .C
external W W W 0 Y . W
WW .100Y M .TW W
W . 100 O M .T W .10 O M.T
W O .C W Y. C
WW .100Y.C M.TW SWAIT WW — Stop-to-Wait1 00Y .TW
Conversion
M Bit W . 100 M .TW
. O halt mode. When W W O
W O WW bit00enables Y.C .C
00Ybit is set, W CPU
WW .100Y.C M.TW TheW SWAIT
. 1 M .TW W the SWAIT
W . 1 O M.T
the
interprets Wthe STOP O
instruction as a WAIT instruction, andC the MCU
W
WW .100Y.C M.TW
O
W W 0 0 Y.C .T W WW .100Y. M .TW enters halt
mode. HaltW .
mode 1 is theOsame M as wait mode,W except
W that anOoscillator
W O Y.C .C
Yhalt W
WW .100Y.C M.TW stabilization WW delay . 1 0 0 of 1 to 4064
M .T W t cyc occurs W after exiting
. 1 0 0 M.T
mode.
O W O W .C O
W
WW .100Y.C M.TW 1 = Halt WWmode 0Y.C M.TW
0enabled WW .100Y M .TW
.
W not Y1 O W O
W
WW .100Y.C M.TW
O 0 = Halt W
W
mode
00
enabled
. 1 M
W W .C O SWPDI — Software
W WW Pulldown Y .COInhibit Bit
W W WW 00Y.CO .TW
W 00 Y .T W 0 0 .T 1 M
W.1 Y.COM The SWPDI bit inhibits W.1 software C OM control of the I/OW W.pulldown
port .COdevices. The
W W 0 .T W
SWPDI bit W W
overrides the
0 0 Y .
pulldown .T W
inhibit bits in W the port . 0 0 Y
pulldown
1 .
inhibit
M TW
0
W.1 Y.COM registers. .1 M WW 00Y.CO .TW
W W W WW 00Y.CO .TW W
W 00 .T 1 = Software pulldown .1 M .1 M
W W.1 Y.COM W WW 00control Y .CO inhibited W W WW 00Y.CO .TW
W 00 .T 0 = Software pulldown W T
M. inhibited .1 M
W.1 Y.COM W W W.1 control Y .C Onot
W WW 00Y.CO .TW
W W
W
W .100 PIRQ
O M.T— Port A External
W
W .100 BitOM.T
Interrupt
W W.1 Y.COM W
C W . C
WW .100Y. The.TPIRQ W bit enables
M1 = PA0–PA3 enabled
W the.1PA0–PA3 00Y .TW
pins
M to function W as external
W .100interrupt OM
.T
pins.
W O W C O W .C
WW .100Y.C M W
.=TPA0–PA3 WW as .
Y.
external
100as external M .TW pins W W.100Y OM.TW
interrupt
W O 0 not enabled
W O interrupt pins W .C
WW .100YLEVEL .C .T W WW .100Y.C M.TW W . 1 00Y M .TW
M —External Interrupt W
Sensitivity BitO W O
W
WW .100Y.C
O
.T W bit controls WW 0 Y.C
0interrupt .TW WW .100Y.C M.TW
The LEVEL external . 1 M triggering sensitivity. O
W .C O=MExternal interruptsWtriggered W Y
O
.Cactive W W WW 0 Y.C W
W W
.1 00 Y 1
M .T W W
W . 10 0 by
O M .Tedges and active levels
W .1 0
O M.T
W 0O = External interrupts W .C by active edges WW Y.C
WW .100Y.C M.TW W triggered . 1 00Y
only
M .TW . 100 M .TW
O COP Enable Bit WW O W O
W COPEN
WW .10The
—
0Y.CCOPEN .T W W 0 0Y.C M.TW WW .100Y.C M.TW
.1 W O
W OM bit enables the W COP W watchdog. Y.C
O
WW .100Y.C M.TW
WW .1001Y.=CCOP .T W
watchdog W
enabled . 1 0 0 M .T W
W =.C OMwatchdog disabled WW 00Y.CO .TW W WW 00Y.CO .TW
WW .1000Y COP
M. T W W .1 W.1 Y.COM W
W C O W W . C OM W
WW .100Y. W Y W W 00 .T
W O M.T
W
WW .100Y . C
W .100 O M.T
O W O .C
W
W O W C O W W .C OM
WW .100Y . Y
WW .100Y.C M.TW M.T
W W
W .100 OM
WW .100Y . W Y W W 0 0
W O M.T
W
W .100 O M.T W W.1
W . C
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M W O EPROM Programming Characteristics
. 1 00Y M W O
W O
2.9 EPROM Programming
W CO
WW 00Y.Characteristics W W WW 00Y.CO .TW
W .T
O M.T W .1
.C OM W W.1 Y.COM W
.C W 00Y Table .TW 2-1. EPROM W Programming 100 .T
Characteristics (1)
. 1 00Y M .TW W
W . 1 O M W . O M
W O WW Symbol .C
00 Y.C .T W WW .100Y.CCharacteristic M .TW . 1 00Y M.T Typ
Min
W
Max Unit
. 1 M W O W .C O
WW 00Y.CO .TW WW 0 Y .C .T W W W 0 0 Y .T W
.1 M Programming0
W.1 YVoltage OM WV.1PP Y.COM W
WW 00Y.CO .TW W WIRQ/V PP 00
1
.C
.T W W W
. 1 00 16.0 M.T16.5 17.0
V
W. 1 OM . O M W O
WW 00Current Y.C WW .100Y.C M.TW
WW .100Y.C M.TW WProgramming
. 1 M .TW
W O IRQ/VW O IW
WW .100Y—¦
PP .CO 3.0 mA
WW .100Y.C M.TW WW PP .100Y.C M.TW M .TW 10.0
W W .C O
W WW Time Y .CO .TW W WW 00Y.CO .TW
W 00 Y .T W
Programming
.10 0 .1 M
W.1 Y.COM W Per Array
W W Byte . C OM tEPGMWW 004Y.CO — .TW — ms
W W 0 Y .T W W
W . 1 00 M .T MOR . 1 0 M tMPGMW.1 4 O —M —
WW O
W O
WW .100Y.C M.TW 1. V W= 5.0 Vdc.1±010%, 0Y.C M.TW WW .100Y.C M.TW
W O W VSS O= 0 Vdc, TA = –40°C to W +85W °C .CO .TW
WW .100Y.C M.TW 00Y
DD
WW .100Y.C M.TW W .1 M
W W .C O W W Y .C O
W W W W
0 Y .CO .TW
Y W W .100 .T 0
W
W .100 O M.T W .C OM W W.1 Y.COM W
C W W
WW .100Y. M.T
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W .C O W
O W O W .C O
W
W
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M .1 M
W 00 .T W .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
O W O W .C O
W
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W .1
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
O W O W .C O
W
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W .100 O M .T W
W .100
W O WW
W O W O
W O Rev. 4.0 W O
WW .100Y.C —M
W O W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
OM.T
WW .100Y .C W
W O M.T
M WW 00Y.CO .TW
0 Y.CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW WW .100Y. C
. 1 M W O W O
W
0 Y.C
O
. 1 0 M W O W O
.1 M W O W O
W 00 .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100 OM
.T
W O C W .C
WW .100Y.C M.TW W W
1 00Y
.
M .TW W . 100
Y
M .TW
W . O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W .C O W
W O W O W W .C O
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100
W O W C O W W .COM
.C W Y . W W 0Y
WW .100Y M.T
W W .100 M.T W.1
0
W O W W .C O W
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O W O
Data Sheet
.TW WW .100Y.C
W O W
W O M
W Y.C W
W 00 .T
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
00
W MC68HC705KJ1 .T W.1 Y.COM W
Data Sheet —
W W.1 Y.COM W W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW WW .100Y. C
. 1 M W Section O 3. Computer Operating W O
W
0 Y.C
O
.T W WW .100Y.C M.TW WW .100Y.CProperly M .TW Module (COP)
. 1 0 M W O W O
.1 M W O
W.1 3.1 Introduction
M .1 M WW 00Y.CO .TW
W Y .C O
W W WW 00Y.CO .TW W
W 00
W.1 Y.COM W
.T W.1 operating
The computer .C OM properly (COP) W W.1 Yresets
watchdog
M
.CO the.TMCU W in case of
W W W Y
00 Software W W
.Tthat is operating properly 0
10 periodically
W . 1 00 M .T software . 1
failure. M W . O M services the COP
W W Y. C O
W W
watchdog WWand0prevents 0 Y .CO COP .T W reset. The WCOP
W
watchdog0 0 Y.C function .T W is programmable
W
W .100 O M.T W .1
.C O M W W.1 Y.COM W
W
WW .100Y.C M.TW
by the COPEN bit in the mask W option register.
W
W .100
Y
O M.T
W
W .100 OM
.T
W O C W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
3.2 Features W O W C O
W
WW .100Y.C M.TW
O
O W O W .C O
W
WW .100Y.C M.TW
The computer WW operating 00Y
.Cproperly .TW module (COP) WWincludes . 1 00Ythese features:
M.T
W
W . 1 O M W C O
W O .C WW .100Y . .TW
WW .100Y.C M.TW
• Protection WW from . 1 00Y
runaway
M
software
.TW M
O W O
W O WWand0halt 0Y.C WW .100Y.C M.TW
WW .100Y.C M.TW
• Wait W mode mode operations
.TW
. 1 M
W W .C O
W 00 Y .T W .1 M
W.1 Y.COM W
3.3 Operation W W.1 Y.COM W WW 00Y.CO .TW
W W
W
W .100 O
.T
MOperation
W .100
Wmodule O M.T W W.1 Y.COM W
.C of the COPW .Cis discussed W here.
WW .100Y M .TW W
W . 100
Y
O M .T W
W .100 O M.T
W .CO .TW WW .100Y. C
WW 00Y WW .100Y.C M.TW M .TW
3.3.1 COP . 1
Watchdog Timeout
M W O W O
W
WW .100Y.C M.TW
O
WW O
W W Y.C O counter stages atW
Four
W W
theWend ofYthe
0 .COtimer.T make
W up theW COP watchdog.
0 0 Y.C The COP .TW
W . 1 00 resets M T MCU if the timeout
.the . 1 0period occurs M before the COP . 1
watchdog
W timer
O M is
CO WW 0and O .C
W
WW .100Y.cleared .by
T WapplicationWsoftware 0Y.C the IRQ/V .TW pin voltage WWis between . 1 00Y VSS M and.TW
M W . 1 O M PP W C O
W O .C W and Y . .TW
WW .100Y.DD
V C . Periodically
.TW
clearing WWthe counter . 1 00Y starts M
a
.TnewW timeoutWperiod . 100prevents M
M O W O
W COP
Y.C
Oreset. A COP watchdog WW 00Y.Ctimeout indicates
TW
that the
WW .100Y.C M.TW
software is not executing
WW .100instructions .T Wthe correct
in Wsequence. . 1 M .
W W .C OM
Y W
W
NOTE: 00
W.1 TheYinternal
.T
OM clock drives the COP
1
W.watchdog. .C
M
OTherefore, the COP W W.1 Y
watchdog .CO .TW
cannot M
W .C W W Y W
00the internal.Tclock to stop. W 0 0
W 00
generate a reset.T for errorsW that cause
W.1 Y.COM W .1 M
W
W .100COP O
The M.T
watchdog
W
depends on aW .100 supply
power
.T
OMvoltage at or aboveWaWminimum .1 M
.CO .TW
W Y . C W W W 0 Y . C T W W 0 0 Y
W 00
specification and .Tis not guaranteed W 0
to.1protect against . brownout. .1 M
W.1 Y.COM W W .C OM WW 00Y.CO .TW
W Y W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W . C W
WW .100Y. M.T
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W .C O W
O W O W .C O
W
W O W C O W W .C OM
WW .100Y . Y
WW .100Y.C M.TW M.T
W W
W .100 OM
WW .100Y . W Y W W 0 0
W O M.T
W
W .100 O M.T W W.1
W .C
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O Rev. 4.0 W O
WW .100Y.C —M
W .C O W W
MOTOROLA WWComputer .1 00YOperating M .TW ModuleW
Properly (COP) 31
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
.TW Module WW(COP) Y.C .TW
Computer Operating Properly M W . 100 O M
. 1 00Y M W O
W O
3.3.2 COP Watchdog
W WWTimeout Y
O
.CPeriod W W WW 00Y.CO .TW
W 0 .T
O M.T W .1 0
.C OM W W.1 Y.COM W
.C W The COP
00Y
watchdog .TW timer function W implemented
is
100 by .dividing
T the output of the
. 1 00Y M .TW W
W .
real-time 1 M
O circuit (RTI) by eight.
interrupt W .The RTI O M
select bits in the timer status and
W
0 Y.C
O
.T W WW 0 0Y.C control .TWRTI output, WW . 1 0Y.C output
0selected M .TWdrives the COP
. 1 0 M control . 1 register M and W the O
WW 00Y.CO .TW WW 00Y
Wwatchdog. .COtimer.Tstatus
(See W and control WW register 0 0Y.C in Section .TW9. Multifunction
. 1 M . 1 M W . 1 O M
WWModule.) O
WW 00Y.CO .TW Timer
W 0 0Y.C M.TW WW .100Y.C M.TW
. 1
W. 1
.C OM NOTE: TheWminimum W Y .CO timeout W W WW times 0 .CORTI period.
Ythe W The COP is
W W
. 100 Y
M .T W W
W . 10 0 COP
O M .T period is seven
W .1 0
O M.T
W O cleared
WWwill .vary
asynchronously .C with the value inW the RTI divider; Y.C hence, .TWthe COP timeout
WW .100Y.C M.TW period 1 00Ybetween M TWand 8x theWRTI period.
.7x W . 100 O M
W O
W
WW .100Y.C M.TW
O
W O
W CO
.Clearing WW 00Y.CO .TW WW .100Y.C M.TW
WW 3.3.3 0 0 Y .T the
W COP WatchdogW .1 M
W 0 W .1 writeO
W .10 O M.T To clear the COP
W .1 watchdog
C OMand prevent a COP W Wreset,
.C
aMlogic 0 to bit 0
W W 00 Y .C
.TW (COPC) W of Wthe COP
1 0 0 Y .
register
M
at .T W
location $07F0 W (see Figure
.1 0 0 Y 3-1). M .TW the COP
Clearing
. 1 M . W O
W O bit disablesW the WCOP watchdog .CO .timer regardless WWof the IRQ/V .C pin voltage.
00Y PP M.TW
WW .100Y.C M.TW W . 1 00Y M TW . 1 O
W W .C O If
W the main WW executes
program Y .CO within W the COP W WW period,
timeout 0 0 Y .Cthe .TW routine
clearing
W 00 Y .T W . 1 0 0 M .T . 1 M
. 1 M W onlyYonce. O W O
W O should be executed
WWthe clearing .C If the main program WWtakes Y.C than .the
longer TWCOP
WW .100Y.C M.Ttimeout W period, . 1 00 routine M
W
.Tmust be executed W more. 100 than once. O M
W O
W
WW .100Y.C M.TW
O
W COmainTprogram WW O routine.
W NOTE:O Place 0Y.C M.TW
the clearing routine in .the and not in an interrupt
WW .100Y.C MClearing .TW the COP WWwatchdog .1 0 0 Yin an . W
interrupt routine mightW
W . 1 0
prevent COP
OM O watchdog
W .C O timeouts even though WWthe 0main Y .Cprogram W W W properly. 0Y.C W
W W
. 1 00 Y
M .T W W
W . 1 0
O M .T is not operating
W .1 0
O M.T
W O WW .100Y. C
W O W O
3.4 Interrupts W
WW .100Y.C M.TW
O
W W .C O COP watchdog does
The W WWnot generate Y .CO interrupts. W W WW 00Y.CO .TW
W 00 Y .T W 0 0 .T .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
3.5 COP Register C W . C W
WW .100Y. M.T
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W . C O W
WW .100The Y.CCOP register .TW (COPR) WW is a write-only
. 100
Y register
M .TWthat returns .100 of OM.T
W the contents
O M
W EPROM location $07F0 when W .C O W W .C
WW .100Y.C M.TW WW read. . 1 00Y M .TW W . 1 00Y M.T
W
W O W C O
W
WW .100Y .CO $07F0
Address: .TW WW .100Y.C M.TW WW .100Y. M .TW
M W O W O
W O
WW5 .100Y4.C M.3TW WW1 .100Bit Y.C W
WW .100Y.C MBit.T7 W 6 2
W
0
O M.T
W O C
W
WW .100Read: Y.C
O
.TW WW .100Y.C M.TW WW .100Y. M.TW
W Write: O M W O W .C O
WW .100Y.C M.TW WW .100Y.C M.TW WW .1COPC 00Y M.T
W
O W O W .C O
W Reset:
WW .100Y.C M.T=W
U U
WW .100Y.C M.TW
U U U U
WW .100Y
U 0
M.TW
Unimplemented U
W = Unaffected O W O
W
WW .100Y.C M.TWFigure 3-1.
O
W W .C O
W
COP
WWRegister Y .CO (COPR)
W W WW 00Y.CO .T
Y W 0 0 .T .1
W
W— .100 OM Bit
.T
W W.1 Y.COM W WW 00Y.CO
M
COPC W COP Y .C Clear W W 00 .T W
W
This W .100
write-only O
bit
.T
Mresets the COP watchdog. W.1 Reading .C OMaddress $07F0 returns W W.1 Y.COM
.C W W
W
Wundefined . 1
Y
00results. M .TW W
W .100
Y
O M .T W
W .100
W O WW
W O W O
W O W O
.TW WW .100Y.C — Rev. 4.0
W .C O W W
32 WWComputer .1 00YOperating M .TW ModuleW
Properly (COP) MOTOROLA
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.CComputer M .TW Operating Properly Module (COP)
M W O Low-Power Modes
0 Y .CO .TW W W 0 0 Y.C .T W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
3.6 Low-Power Modes W W.1 Y.COM W W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW .C WW Y. C
00Y WWThe .STOP 1 00Y and WAIT M .TWinstructions have the
. 100following M .TW on the COP watchdog.
effects
. 1 M W O W O
W
0 Y.C
O
. 1 0 M Stop Mode
3.6.1 W O W O
.1
WW 00Y.CO .TW
M TheWW Y.C
STOP instruction O clears
W the COP WW
W
watchdog .CO and
0Ycounter .TWdisables the clock to
W . 1 0 0 M .T . 1 0 M
W. 1 OM the COPW watchdog. O W O
W O NOTE: WW the
To prevent .CO instruction
STOP from disabling
WW .1the
W
0YCOP.CO watchdog, program the
.TWto logic 1.
WW .100Y.C M.TW W
stop-to-wait . 1 0 0 Y
conversion M .T
bit
W
(SWAIT) in the maskW
0 option M
register
O
W O
W
WW .100Y.C M.TW
O
W O Upon exit Wfrom stop mode O by external reset:WW .CO .TW
WW .100Y.C M.TW WW .100Y.C M.TW W . 1 00Y M
W W .C O • The W W
counter begins
Y .C O counting from $0000.
W W W W
0Y .CO .TW
Y W W .100 is cleared .T 0
W
W .100 O M.T • The W
counter . C OM again after the oscillator W W.1 stabilization
Y
M
.CO .Tdelay W and
W Y .C W W W 0 0 Y .T W W 1 0 0
W 0 0 .T 1 . M
W.1 OM begins W .
counting from OM $0000 again. W O
W W .C O Upon exit from WW stop mode
Y .Cby O external interrupt: WW
W W 0 Y .CO .TW
W 00 Y .T W W 0 0 .T 1 0 M
W.1 Y.COM W• The counter W W.1begins .C OM from $0000. WW.
counting Y .CO .TW
W W 00 Y .T W W 0 0
W
W .100 O M.T • The counter Wis.1not cleared .C OMagain after the oscillator W W.1 stabilization
Y .C OM delay and
W
.C W W
WW .100Y M .TW continues W counting
W .
Y
100 throughout O M .T the oscillator W .100 delay.
stabilization
W O M.T
W
WW .10NOTE:
O
0Y.C MImmediately
.TW WW .100Y.C M.TW WW .100Y.C M.TW
W W . CO after W exiting
W stopY.mode CO byTexternal W
interrupt,
W WWservice 0 COCOPTtoW
Y.the
Y W W 0 . 0 .
W
W .100 O M .T a full COP timeout
ensure
W .10period.OM
.C W W.1 Y.COM W
C W W
WW .100Y. M .TW W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW
3.6.2 Wait Mode WW .100Y. M .TW W .100
Y
M.T
W O W C O
W
WW .100Y.CTheM
O
.TWinstruction
WAIT Whas W no effect .C
00Y on the TW watchdog.
.COP WW .100Y. M .TW
W . 1 O M W O
W CO Y.C mode,.Texit WW .C W
WWNOTE: 0 0 Y.To prevent.T Wa COP timeout WW during . 1 0 0wait M
W wait mode . 1
periodically00Y to service M.T
.1 O M W O W .C O
W
WW .100Ythe .C COP..TW WW .100Y.C M.TW WW .100Y M .TW
M W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W .1
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
O W O W .C O
W
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W .100 O M .T W
W .100
W O WW
W O W O
W O Rev. 4.0 W O
MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1WW .100Y.C —M .TW WW .100Y.C Data Sheet
W .C O W W
MOTOROLA WWComputer .1 00YOperating M .TW ModuleW
Properly (COP) 33
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
.TW Module WW(COP) Y.C .TW
Computer Operating Properly M W . 100 O M
. 1 00Y M W O
W O
W
O M.T W .1
.C OM W W.1 Y.COM W
.C W W
00Y .TW W .100
Y
M.T
W .100 OM
.T
W.1 Y.COM W W C O W W .C W
00 .T WW .100Y. M .TW W .100
Y
M.T
. 1 M W O W .C O
. 1 M W O W O
W W. 1
.C OM
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100 OM
.T
W O C W .C
WW .100Y.C M.TW W W
1 00Y
.
M .TW W . 100
Y
M .TW
W . O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W .C O W
W O W O W W .C O
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100
W O W C O W W .COM
.C W Y . W W 0Y
WW .100Y M.T
W W .100 M.T W.1
0
W O W W .C O W
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O W O
.TW WW .100Y.C — Rev. 4.0
W .C O W W
34 WWComputer .1 00YOperating M .TW ModuleW
Properly (COP) MOTOROLA
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW WW .100Y. C
. 1 O M W O W .C O
W
0 Y.C .T W WW .100Y.C M.TW Section WW4. Central . 1 00Y Processor
M.T
W Unit (CPU)
. 1 0 M W O W .C O
W C O W .C W W Y W
W Y. W W .100
Y
M.T
W 00 .T
W .C .TW
. 1 O M W O W .C O
W
W
The central W processor O W .C O
W O W .C unit (CPU) consistsWof a CPU Ycontrol unit,W an arithmetic/logic
WW .100Y.C M.TW W(ALU),
unit . 1 00Yfive CPU
and M
W
.Tregisters. The
W
CPU W . 100 unitOfetches
control M .T
and decodes
W W Y .C O
W W WW The
instructions. 0 Y .CO executes
ALU .T W the W W
instructions. 0
The 0 .C
YCPU .T W contain data,
registers
W 00 .T .10 M .1 M
W W.1 Y.COM W addresses, W Wand .
status
Y C Obits that W reflect theW WW of0CPU
results 0 Y .CO .TW
operations.
W 00 .T W . 1 0 0 M .T . 1 M
. 1 M W O W O
W
WW .100Y.C M.TW
O
4.2 Features W O W O
W
WW .100Y.C M.TW
O
WCPU include: O W O
WW .100Y.C M.TW
W O Features ofW the
WW .100Y.C M.TW W 0 0 Y.C .T W
.1 frequency M part WW O
W W Y.C O
W
• 4.0-MHz
W WW bus
0 Y .CO on.Tstandard W W 0 0Y.C .TW
W . 1 00 M .T . 1 0 M W . 1 O M
W O
W
WW .100Y.C M.TW
O • 8-bit accumulator
W W .C O
W
• 8-bit index W
Wregister Y .CO .TW W WW 00Y.CO .TW
W 00 Y .T W 0 0 .1 M
W.1 Y.COM •W 11-bit program W W.1counter Y .C OM
W WW 00Y.CO .TW
W W 00 .T W
W
W .100 O M.T• 6-bit stack pointer W.1 Y.COM W W W.1 Y.COM W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100 O M.T
W O • Condition code register with five status flags WW Y.C
WW .100Y.C M.TW WW .100Y.C M.TW .100 M .TW
W O
W O • 62 instructionsWW .CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW W .1 00Y M
W W .C O • 8 addressing modes
Y W
W 00 .T
W.1 Y.CO• M Power-saving stop, W .1
wait, halt, .C OMdata-retention modes
and W W.1 Y.COM W
W W
W W
.1 00 M .TW W
W . 100
Y
O M .T W
W .100 O M.T
W O Y.C WW .100Y .C
WW .100YThe .C programming
.TW model WW is shown
1 00in Figure .4-1.
M TW M .TW
M W . O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W .1
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
O W O W .C O
W
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W .100 O M .T W
W .100
W O WW
W O W O
W O Rev. 4.0 W O
W O W W
MOTOROLA WW .10Central 0Y.C Processor M .TWUnit (CPU) W 35
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
Central Processor Unit (CPU) .TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
M .TW W
W . 100 O M .T W
W .100 O M.T
O WW .100Y. C
WW .100Y.C M.TW
ARITHMETIC/LOGIC UNIT
.TW
CPU CONTROL UNIT
0 0 Y.C .T W M
W
W .10 0
O M. T
W .1
.C OM W W.1 Y.COM W
W Y.C W W Y W 7 6 W5 4 3.1020 1 0 M.T
W .100 O M.T
W
W .100 O M.T WW 00Y.CO ACCUMULATOR
W Y .C W W W 0 Y .C T W W .TW (A)
1 00 .T . 1 0 M . W . 1 O M
W. OM W O
WW .100Y.C M.TW
W O W O 7 6 5 4 W 3 W2 1 0 .CO
WW .100Y.C M.TW WW .100Y.C M.TW W .
Y
100 INDEX M .TW
W O
WW 00Y.CO .TW
REGISTER (X)
W W Y . CO
W W W W 0 0 Y.C .T W
W 00 .T W13.1 12 11 OM .1 M
W W.1 Y.COM W W Y .C W W W2W1 000Y.CO .TW
W 00 .T W15 14
.10 0 10 9 8.T 7 6 5 4 3
.1 M
W.1 Y.COM W 0 W 0 W 0 0 0 Y.0C 0 0 1W1
OM WW 00STACK Y .CO W
W W POINTER
M.T
(SP)
W . 1 00 M .T W
W . 100 O M .T W .1
C O
W
WW .100Y.C M.TW
O
WW 00Y
.C TW WW .100Y. .TW
15 14 13 12.111 10 9 O8M7. 6 5 4 3 2 1 W 0 O M
W O WW Y.C WW .1PROGRAM .C
00Y COUNTER W
WW .100Y.C M.TW 0 W 0 0 0 .0100 M .TW W O M.T(PC)
O W O .C
W
W O W O
W O
WW .100Y.C 7 M6 .T5W 4 3 2 W 1 W Y.C .TW
WW .100Y.C M.TW 100
0
W O W . O M
W O 1 1 1 H I N Z CW CONDITIONY .C
WW .100Y.C M.TW WW .100Y.C M.TW 00 CODE REGISTER W
(CCR)
W .1 M.T
W O W O
W
WW .100Y.C M.TW
O
WW HALF-CARRY .C
00YFLAG M.TW WW .100Y.C M.TW
.1
W W .C O
W 00 Y .T W .1 MASK M .1 M
INTERRUPT
W W WW 00Y.CO .TW W
W 00 .T W.1 FLAGY.COM W .1 M
NEGATIVE
W W
W ZERO 0 .T W
W
W .100 O M.T W .10FLAG
.C OM W W.1 Y.COM W
C W W
WW .100Y. M.T
W W
CARRY/BORROW 100
.FLAG
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW . 0Y.
104-1. M .TW Model W .100
Y
M.T
O Figure
W Programming
O W .C O
W
W O W O
4.3 CPU W WW Unit
Control 0 Y.C
O
0
W W. 1
.C OM
W 00 Y .T unit fetches and W 1 M .1 M
W.1 TheYCPU .C OM control
W W.decodes Y.C instructions
O
W
during program WW operation. 0Y .CO .TW
W The W
.T selects theW 00 W
.T and write and coordinates 0
W 00 controlM unit memory.1locations to read
OM .1 the M
W W.1timingY.of C O
all CPUW operations. W W Y .C W W WW 00Y.CO .TW
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. TW W .100
Y
M.T
W .100 OM
.T
4.4 Arithmetic/Logic W Unit .COM. W C O W W .C W
WW .100Y .TW WW .100Y. M .TW W .100
Y
M.T
O M W O W .C O
W
0Y.C M.Tunit
WWThe arithmetic/logic W (ALU) performs WW .1the 00Y
.C
arithmetic, .Tlogic,
W and manipulation WW .100Y M .TW
.1 0 O M W O
operations
W decoded
O
Y.Cresults.Tcalled
from the instruction WW set0by Y.C
the CPU control unit. The
W WW .100Y.C M.TW
ALU
WW produces 0 0the W for by W the program. 1 0and sets M .
orTclears status and control
W W . 1
.C OM
W bits in the 00 Y
condition code
.T register W
(CCR). .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W .100 O M .T W
W .100
W O WW
W O W O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W W
36 WW .10Central 0Y.C Processor M .TWUnit (CPU) W MOTOROLA
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW Central Processor Unit (CPU)
M WW 00Y.CO .TW CPU Registers
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
4.5 CPU Registers W W.1 Y.COM W W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW .C CPU WW Y. C W monitor MCU
00Y WWThe .M68HC05
1 00Y M .TW contains five registers
. 100that control M .Tand
. 1 M W O W O
W
0 Y.C
O
.T W
operation:
. 1 0 M •W Accumulator O W O
.1 M • WIndex register O W O
W W.1 Y.COM W •WW Stack pointer
Y .CO .TW W WW 00Y.CO .TW
W 00 .T W 0 0 .1 M
W.1 Y.COM W W.1 Ycounter
• WProgram .C OM
W WW 00Y.CO .TW
W W 00 .T W
W
W .100 OM.T • W.1 Ycode
Condition .C OM register W W.1 Y.COM W
.C W W
WW .100Y M .TW W
W . 100 O M .T W
W .100 OM
.T
W O C W .C
WW .100Y.C M.TW CPU W
W
registers are
1
.
00Ynot memory M .TWmapped. W W.100 Y
M .TW
W . O O
W
WW 4.5.1 0 Y.C
O
0 O
W.1 Accumulator
OM W O W
WW .100Y.C M.TW
W O The accumulator W .CO .TW 8-bit register. WW The
W .COuses.Tthe
WW .100Y.C M.TWaccumulator WW .is10a0Y general-purpose
M . 1 0 0YCPU
M
W
O to Whold operands O and results of ALU W
operations. .C O
W
W 6 Y.C 5 O W O
W
WW .100Y.C M.TW
O BitW 7W
00 .TW 4 W3W .1020Y.C M 1 .TW Bit 0
W . 1 O M W O
W
WW .100Y.C M.TW
O Read:
W O W O
WW .100Y.C M.TW
W O Write:
WW .100Y.C M.Reset: TW WW .100Y.C M.Unaffected TW
W W .C O
W WW 00Y.CO .TW
by reset
W WW 00Y.CO .TW
W 00 Y .T W M Accumulator (A)WW.1
W.1 Y.COM W .1 Figure 4-2. OM
W W WW 00Y.CO .TW W 1 0 0 Y.C .TW
W . 1 00 M .T W . 1 O M W . O M
4.5.2W WW Register
Index 0 Y.C
O
0
W
W 00 In the
W.1 Y.determine OM
T
.indexed addressing modes,
W.1 Ythe .C OCPUM uses the byte inWthe W.1indexYregister M to
.COcan .TW
W C the conditional W address of the W
operand. The W
index register 0 also
W .100 serve M .TW W
W
00
.1location OM
.T 0
W.1 Y.COM W
W C O as a temporary storage
W .C or a counter.
W W
WW .100Y. M.T
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W
W 5 00Y 4 .C O W
WW .100Y.C MBit .TW 7 6 W
. 1 M .TW 3 2W
W
1.100 Bit 0M.T
O
W C O W W .C O W YC
. W
W .
Read:
Y W W 0 Y .T W W .1 0 0 M.T
W .1 00 M .T W . 10 O M W C O
W Write: O
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y. M .TW
W UnaffectedOby reset W O
W Reset: O
W Index O W O
W
WW .100Y.C M.TW
O FigureW4-3.
W 0 0 Y.CRegister
.T W(X) WW .100Y.C M.TW
W. 1 OM W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100
W O W C O W W .COM
.C W Y . W W 0Y
WW .100Y M.T
W W .100 M.T W.1
0
W O W W .C O W
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O Rev. 4.0 W O
WW .100Y.C —M
W O W W
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
4.5.3 Stack Pointer W W.1 Y.COM W W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW C
.pointer WW that.1contains .C TW
00Y WWThe .stack 1 00Y M .isTW a 16-bit register 00Y the .address
M
of the next location
W . 1 O M onWthe stack. O
During a reset or afterWthe reset Y W stack O
.C pointer instruction (RSP), the
0 0 Y.C .T W WW stack . 1 00Y.Cis preset
pointer M .TW to $00FF.
W address
The . 1 00 in the stack M .TW pointer decrements after
. 1 M W O WWa byte .C O
WW 00Y.CO .TW 0Y.C and
WaWbyte .is10stacked .T W
increments W
before .1 0 0 Y is unstacked.
M .T W
.1 M W OM WW 00Y.CO .TW
WW 00Y.CO .TW W W 00 Y .C
.T W W
W .1 O M W.1Bit Y.COM W W W.1 Y.COM W Bit
W Y.C W W W 15 0 14 13 .T
12 11 10 W 9 8 0
7 0 6 5 .T 4 3 2 1 0
W
W .100 O M.T W .10
. C O M W W.1 Y.COM W
W 0 000Y 0 0.TW0 0 W
WW .100Y.C M.TW W Read:
.1 M
0 0
W .100
1 1
O M.T
W O W O W .C
Write: W Y
.1001 1OM1.T 1 1 1 1
W
W O W C
O WW .100Y.
W Reset: 0 0 0 0 0 0 0 0 1
WW .100Y.C M.TW WW .=10Unimplemented0Y.C M.TW M .TW
W O W O
W
WW .100Y.C M.TW
O
W OFigure 4-4. Stack Pointer W (SP) O
W
WW .100Y.C M.TW
O
W O W O
W O
WWsignificant Y.C WW Y.C fixed W
WW .100Y.C M.TWThe 10 most . 0 0 bits of the
1 stack pointer M .T W stack pointer
W . 1 0
are permanently
0
O M.T at
O 0000000011, soW the O produces addresses from .C
$00C0 to $00FF. If
W
WW .100Y.C M.TW W W 0 0 Y.C .T W WW .100Y M .TW
subroutines and W . 1
interrupts useM more than 64 stack locations, W theOstack pointer
W O
WW .CO and WW Y.C TW data.
WW .100Y.C M.Twraps W around to address . 1 0 0 Y$00FF
M .T W
begins writing over
W
the
. 1 0 0previously
O M .stored
W O WW .CO .TWan interrupt WW Y.C W
WW .100Y.C M.TW
A subroutine W uses two stack
. 1 00Y locations; M
uses five
W .1 00locations.
O M.T
W O
W
WW Program .CO .TW WW .100Y.C M.TW WW .100Y.C M.TW
00Y Counter
4.5.4
W W . 1
.C O M
W 00 Y .T W .1
W.1 Y.COM
1
is .a 16-bit OM that contains the WW OMnext
W The program counter
W W WW 0 Y .Cregister
0fetched. M T W
. five most significantW address
0 0 Y .Cthe
of
1bits of the .TW
W . 1 00 M .T
instruction or operand to .
be1 The W . O Mprogram
W O WWappear .CO WW .100Y.C M.TW
WW .100Y.C counter .T Ware ignored Wand .1 0 0Yas 00000.
M .TW
W W .C OM
Y W
W 00 Normally,
W.1 Y.COM W
.T the address in the 1
W.program .C OM automatically W
counter W.1 Y.to
increments CO theMnext
W
W Y W W 0
W W
.1 00 sequential M .T memory location W
W . 100 time O
every anM .T
instruction or operand is.1fetched.
W
0
O M.T
Jump,
W O W an address .C
WW .100Ythan .C
branch, andWinterrupt operations
T the next sequential
.of WW .10load 0Y.Cthe program M .TW counterW with
. 100
Y other.TW
M
W W .C that
O M W W location.
Y .C O
W W W W
0 Y .CO .TW
Y W W 00 .T 0
W
.C W W 00 BitM.T
WW .100Y M
Bit.TW W .100 9 8OM7.T 6 5 4 W W.12 1Y.CO
W O 15 14 13 12 11 W 10 C 3 0
WW .100Y.C M.TW W W
1 00Y
.
M .TW W . 100 M .TW
W . O W O
W
WW .100Y.C M.TW
O
W O
W .CO WW 00Y.CO .TW WW .100Y.C M.TW
WW .1Reset: 00Y 0 M0.TW0 0 0W W.1Loaded withM vector from $07FE and $07FF
W O W .CO .TW WW 00Y.CO .TW
WW .100Y.C M.TW FigureW 4-5. Program 0 0 Y Counter W
W.1 Y.COM W
W C O W W .1
.C OM (PC) W
WW .100Y. W Y W W 00 .T
W O M.T
W
WW .100Y . C
W .100 O M.T
O W O .C
W
W O W C O W W .C OM
WW .100Y . Y
WW .100Y.C M.TW M.T
W W
W .100 OM
WW .100Y . W Y W W 0 0
W O M.T
W
W .100 O M.T W W.1
W .C
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W W
W W . C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y . C W
W O M.T
M WW 00Y.CO .TW CPU Registers
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
4.5.5 Condition Code
W 100
W.Register OM
.T W.1 Y.COM W
W . C W W
M .TW W
W . 100
Y
O M .T W
W .100 O M.T
.CO .TW .C code.Tregister W register Y. C
00Y WWThe .condition
1 00Y M
W is anW8-bit
. 100 whose M .TW most significant bits are
three
. 1 M W
permanently O at 111. The condition
fixed W codeYregister O contains
W Y.C
O
W WW Y.C that indicate
0flags .TW the results WW of .the .C
00instruction W the interrupt mask
.Tjust
. 1 0 0 M .T and 1
four
. 0 M W 1 O M executed.
W O
.1
WW 00Y.CO .TW
M W O WW .CO .T
WW .10Bit 0Y7.C M6.TW 5 W 4 .100Y3 M
2W 1 Bit 0
. 1 O M W O W .C O
W
Read: 1 1 1
WW H .100I
Y
MN.T
W Z C
W O Write: W C O W W .C O
WW .1100Y . Y W
WW .100Y.C M.TW Reset: 1 M.T
W
1
W
U W .1010 O M
U
.T U U
W Y . W W 0 Y
0 = Unimplemented .T W W 0 0
U =.1Unaffected M .T
W 00 .T W.1 Y.COM W
W 00 .T W 0
0 Figure 4-6. .T Condition CodeWRegister .1 (CCR) M
W.1 Y.COM W W W.1 Y.COM W W 0 Y .CO .TW
W W 0
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C H — Half-Carry
W Flag .C W
WW .100Y. M.T
W W
The CPU sets 00Yhalf-carry
.1the M.Tflag when a carry
W
W .100 between
occurs
.T
OM bits 3 and 4 of
W O W C O W . C
WW .100Y.C M.TW the accumulator WW .10during 0Y. an M ADD .TW or ADC operation. W Y
.100half-carry
The TWis required
M.flag
W O W O W W .C O
WW .1decimal .C Y .TW
WW .100Y.C M.TW for binary-coded 00Y (BCD) M .TW arithmetic W operations.
W . 100 O M
WW 00Y.C O
W
WW .100Y.C M.TIW
O — InterruptWMask .TW WW .100Y.C M.TW
. 1 M CO
W .C O Setting the interrupt WW 0mask Y
O
.Cdisables W interrupts.W If WanW interrupt 0 Y.request occurs
W
W W 0 0 Y .T W W 1 0 M .T .1 0 M .T
W . 1 O M while the interrupt W .
mask is logic
O 0, the CPU saves W theW CPU O
registers
.C on the
theWinterrupt
.C and.Tthen 0Yvector. W
WW .100Y.C M.Tstack, W sets W 0 0 Ymask, W fetchesWthe interrupt
. 1 0 M .
IfTan
W O W.1 while M
.COthe interrupt WW 1, the .CO .request
W Y.C interrupt
W requestW Woccurs 0 Y .T W mask W is logic 0 0 Yinterrupt
.1 request TW
W . 1 00 M .T
is latched. Normally, W . 10 CPU processes
the O M the latched W
interrupt C O Mas soon
W
WW .100Y.C Mas
O
.TW W W 0 0 Y.C .T W WW .100Y. M .TW
the interrupt maskWis.1cleared O again.
M O
W O Y.C (RTI) WW registers, Y.C restoring W
WW .100Y.C M TW from interrupt
A .return WW instruction .1 0 0 M .T W
unstacks the WCPU . 1 0 0 M.T
W O W C O
W O the interrupt mask to
WWits cleared .Cstate. After .TW any reset, Wthe W interrupt Y.mask is.T W
set
WW .100Y.C and M
W
.Tcan . 1 0a0Y M W . 100 O M
be cleared only W by software O instruction.
W
WW .100Y.N CO
W W .C— M
ONegative
W
Flag WW 00Y.CO .TW W WW 00Y.CO .TW
Y W
W 00 TheM
W.1 Y.C O
CPU.T sets the negative 1 whenOan
W.flag . C
MALU operation produces W W.1 a negative
Y .CO .TW
M
W result. W W W 00 Y .T W W 0 0
W
.C W
WW .10Z0— Y Zero Flag W
M.Tsets the zero flag
W
W .100 O M.T
W
W .100 OM
.T
W The O
CPU when an ALUC operation produces Wa result of .C
$00.
WW .100Y.C M.TW W W
1 00Y
.
M .TW W . 100
Y
M .TW
W . O W O
W C —Y
WW .10The 0 .CCPUM
O
Carry/Borrow
.T W Flag WW .100Y.C M.TW WW .100Y.C M.TW
sets the carry/borrowW flag when an
O addition operation W W
produces a O
W
WW .1carry .CO .T7Wof the accumulator WW .1or Y.C a subtraction
00when W W 0 0Y.Ca M.TW
00Y out ofMbit OM
. T operation . 1
requires O
W O
.CSome WW Y .C W W WW 0 Y.C W
WW borrow. . 1 0 0 Y
M .Tlogical
W operations W and data
W . 1 0 0 manipulation
O M .T instructions also.1clear
W
0
O M.T
Wor set the O carry/borrow flag. WW .100Y .C
WW .100Y.C M.TW WW .100Y.C M.TW M.TW
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W .100 O M .T W
W .100
W O WW
W O W O
W O Rev. 4.0 W O
W O W W
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
4.6 Instruction Set W W.1 Y.COM W W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW .C W Y. C W addressing modes.
00Y WWThe .MCU 1 00Y instruction M .TWset has 62Winstructions . 100 and uses M .Teight
. 1 M W O W O
W
0 Y.C
O
. 1 0 4.6.1 M Addressing Modes W O W O
.1 M O W O accessing data. The
WW 00Y.CO .TW W
The WW CPU uses
0 0 Y.Ceight addressing
.T W modesWW for flexibility1 0 0Y.C in M .TW
1 addressing . 1 modes M
provide eight different W .
ways for the O CPU to find the data
W W. .C OM W W Y .CO .TW W W 0Y .C .T W
W 00 Y .TW W
required to . 0
10executeOan M instruction. The eight 1 0
.addressing modes are:
M
. 1 M W W O
W
WW .100Y.C M.TW
O
W W
• Inherent 00Y
. 1 M
W W .C O
W 00 Y .T W
• Immediate .1 M
W • WDirect .10 0 .T W .1
W 00 .T OM M
W W.1 Y.COM W W W Y .C W W WW 00Y.CO .TW
W
W .100 O M.T • W Extended
W .100 OM
.T
W W.1 Y.COM W
C W . C W
WW .100Y. M.T
W W
• Indexed, Y
.100offset OM.T
no W
W .100 OM
.T
W O W Y. C W Y . C W
WW .100Y.C M.TW • Indexed, WW 8-bit . 100offset OM.T
W W .100 M.T
O W W . C O
W
WW .100Y.C M.TW • Indexed, WW 16-bit Y.C
00offset .TW WW .100Y M .TW
W . 1 O M W O
W O
WW .100Y.C M.TW• Relative WW .100Y.C M.TW WW .100Y.C M.TW
W W .C O
Y W .1
W 100
W.Inherent OM
.T W.1 Y.COM W WW 00Y.CO .TW
M
4.6.1.1
W Y .C W W W 00 .T W
W
.C W W 00
WW .100Y .TW instructions
Inherent
M
W are.those
W 100 thatOhave M .T no operand, suchW M.T
as.1return-from-interrupt
O
W O(RTI) and stop (STOP). W Some .Cthe inherent WW act.1on C
Y. in the.TCPU W
WW .100Y.C registers,
of
M .TW such asW . 1 00Y M .TW instructions W
00data
O M
W O setW W flag (SEC)
carry .CO and.Tincrement accumulator (INCA). Inherent
WWlong..100Y.C M.TW
WW .100Y.C instructions .T W requireWno operand.1 0 0Yaddress M and
W
are one byte
W W .C OM
W 00 Y .T W .1 M
W.1 Y.COM W
4.6.1.2 Immediate W W.1 Y.COM W WW 00Y.CO .TW
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
.C W .C
0Y contain W W 00operation.T
WW .100YImmediate M .TW instructionsW are those .10that M.Ta value to be used in an
W.1 Y.COM W
W O W .C O W
WW .100Y.C M.TW
with the value in the accumulator WW .1or 00Y
index register.
M .TW Immediate W instructions
100 require
.byte, M.T
W no operand
O address and are W
two bytes O
long. The opcode is the W W
first and
.COthe
WW .10immediate 0Y.C Mdata .TWvalue is the WW second . 0Y.C M.TW
10byte.
W .100
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
4.6.1.3 Direct WW
W 0 Y.C
O
0
W.1 Y.COM W WW O
Y.C256 memory W locations WW 00Y.CO .TW
Wwith
WW Direct 0 0 instructions .T can accessW any of the 1 0 0
first .T two bytes.
W.1 Y.COM W
W .1
The firstYbyte C OisMthe opcode, and the W W .
second is . C OM
the low byte of the operandW address.
W . .TWthe CPU W Y W W .100 M.T
W .100 addressing,
InWdirect M W
automatically . 100 usesO$00 M .T
as the high byte ofWthe CO
.CO .TW WW .100Y .
WWoperand 00Y address. WW .100Y.C M.TW M.TW
.1 M W O W O
W
WW .100Y.C M.TW
O
4.6.1.4 Extended W W .C O
W 00 Y .T W .1 M
W
Extended instructions use
.T three bytes Wand can 00
access any .T W
W 00
W.1is theYopcode; OM the second andW W.1bytesY.are Maddress
Othe
in memory. The
W W.1 Y.COM
first W byte . C third C high
W and low bytes
W of .100
W
the operand . 1 0
0address. M .TW W
W .100 O M .T W
W O WW
W O W O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W W
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M WW 00Y.CO .TW Instruction Set
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W
W .100 usingOthe
When M.TMotorola assembler, W W.1the programmer .CO .TW
M does not need to specify
W W Y .C W W 0 0 Y
O M.T
W whether
W .100 an instruction OM
.T is direct or extended.
W W.1 YThe M
.COassembler automatically selects
Y .C W W W the shortest0 Y .C form ofT Wthe instruction. W 0 0 .T W
00 .T 0 . .1 M
W
W .100 4.6.1.5 O M.TIndexed, No Offset
W
W .100 OM
.T
W W.1 Y.COM W
W Y.C W W Y .C W W 00 .T
W .100 O M.T
W
.C W
Indexed instructions.C with no offset are W 1-byte.1instructions that can access data with
W
100Y M .TW W . 100
Y
M .TW W
00
O M.T
. O variable W addresses O within the first 256 memory C
locations.
. TheWindex register
W
WW .100Y.C M.TW WW the 00low Y.C .TtheW WW .100Y M .T The CPU
contains W . 1 byteO M of effective address W of the operand.
C O
W O .C W Y . .TW
WW .100Y.C M.TW WW .100uses
automatically Y $00 as
M .TW the high byte, W so these . 100instructions M can address
W O W C O W W . C O
.C locations W $0000–$00FF. Y . W W 0 Y W
WW .100Y M .TW W
W . 100 O M .T W .10 O M.T
W O .C WW to move Y. C W
WW .100Y.C M.TW Indexed, WWno offset . 1 00Yinstructions M .TWare often used . 100 a pointer M .Tthrough a table or
W O W C O W W .C O
to holdW theW address Yof. a frequently used RAM W or input/output Y (I/O) Wlocation.
WW .100Y.C M.TW . 100 M .TW W .100 O M.T
W O C
W
WW 4.6.1.6 .CO .TW W 00Y
.C .TW WW .100Y. .TW
. 1 00YIndexed, M 8-Bit Offset W W . 1 O M W O M
W
WW .100Y.C M.TW
O
W W .C O Indexed, 8-bitWoffset W instructions Y .CO .are W 2-byte instructions
W WW that 0 COaccess
Y.can TW
data with
W 0 0 Y .T Wvariable W
addresses 1 0 0
within the first T 511 memory locations. . 1 0 The M .
W W.1 Y.COM unsigned W W. Y . C OM
W W W W
0 Y .CO .TWthe
CPU adds
W byteW in the.1index 00 register M.Tto the unsigned byte 0
following the opcode. The
W
W .100 O M.Tsum is the effective Waddress .C Othe
of operand. These W W.1 Y.C
instructions
OMaccess
can W
.C W W
WW .100Y M TW
.locations W
$0000–$01FE. W . 100
Y
O M .T W
W .100 O M.T
W
WW .100Y.C M.TW
O
W O useful for selecting W kth element O in an
W .C O Indexed 8-bit offsetWinstructions Y .Care W W Wthe 0 Y.C W
W W
. 1 00 Y
M .T
n-element
W
table.
W
The table
W . 0
10can begin O M .T
anywhere within the W first
0
.1 256 memory O M.T
W O .C WW The Y. C
WW .100Y.C locations .TW and could WW extend 1 0as0Yfar as locationM .TW 510 ($01FE). .10k0value O isM .TW
typically
M W . O W C
W
WW .100Y.C in the
O
T index
W register, WW and the0address 0Y.C of .TWbeginningW
the ofW the table . 1 00Yis. in theMbyte .TW
M . W . 1 O M W C O
W
WW .100Y.C M.TW
O
following the opcode. W
W 00Y
W . 1 O M W O
4.6.1.7 W WW 16-Bit
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O
Y.COffset.TW WW .100Y.C M.TW WW .100Y.C M.TW
0
W W. 1
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W 00 Y .T W .1 M
W.1 Indexed, .C OM 16-bit offset instructions W W.1 areY3-byte . C OMinstructions that can
W W Waccess
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W Y .TW Wlocation 0in0 memory. .The T CPU adds the unsigned W 0
W
W .100variable O Maddresses at any
W.1 Y.COM W W W.1 Ybyte .C OM in
WW .10the .C
0Yindex M register
.TW to the two
W
W unsigned W The 0 is theM.TW
W . 100 bytesOfollowing M .T the opcode.
W .10sum O
W effective .COaddress of the operand. W The00first Y.Cbyte after Wthe opcode WisWthe high Y.C of .TW
0byte
WW .1the 0 Y
0 16-bit offset; .T W W is.1the low byte .T . 1 0 M
W C OM the second byteW
W .C OM of the offset. W W Y.CO .TW
W Y . W W 00 Y .T W W 0 0
W
W .100
Indexed, O
16-bitM.Toffset instructions W
are .1useful
.C OM
for selecting the kth element
W W.1 in anY.COM W
C
Y. table.T W W
WW n-element .100
W
M anywhere in memory.
W
W .100
Y
O M.T
W
W .100 OM
.T
W O C W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
As with direct O and extended addressing, W the O
Motorola assembler determines W the .C O
W
WWshortest Y.C of indexed .TW addressing. WW .100Y.C M.TW WW .100Y .TW
.1 00form M W O W O M
W
WW .100Y.C M.TW
O
4.6.1.8 Relative W W . C O
W 00 Y .T W .1 M
W W instructions. 00 If theMbranch .T W
W
Relative
W 100
.addressing O M T for branch
is .only
W.1 by adding .C
condition is true,
O the signed byte following W W.1 Y.COM
.C W W
the CPU
WW .100Y finds the effective
M .TW branch destination
W
W .1 00 Y
O M .T W
W .100
the opcode
WW to00the O
contents of the program counter.Y If.C
the branch conditionW isWnot
true, Wthe CPU goesY.Cto the .next TW instruction. WW The . 1
offset00 is a signed, M .TW two’s complement
W .1 O M W O
W O Rev. 4.0 W O
W O W W
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W
W .100that gives
byte
.T
OM a branching range W
.1 to +127
W–128
of
M
.CO bytes from the address of the
W W
W next 0 Y . C W
Tthe branch instruction. W 0 0 Y .TW
.T . 1 0location after
M . W .1 O M
OM W O
WW .100Y.C M.TW
0 0 Y.C .T W WW .100Y.C M.TW
W.1 Y.COM W W using
When O Motorola assembler, WW O does not need to calculate
W Y .Cthe W W
the programmer
0Y.C W
. 1 0 0 M .T W theW offset
. 0 0
1 because O M .T
the assembler determines W . 1 0 the proper
O M.Toffset and verifies that it
WW 00Y.CO .TW .C of .the W .C
WisWwithin 1 0Yspan
0the M TWbranch. W . 100
Y
M .TW
. 1 M W . O W O
W W. 1 4.6.2
.C OM Instruction Types WW
W 00 Y .T W 0 0 .1 M
W.1 Y.COM W The MCU W W.1instructions Y . C OMfall into the following
W WW 0 Y.CO .TW
five categories:
W W 00 .T W 0
W
W .100 O M.T • W W.1 Y.COM instructions
Register/memory W W.1 Y.COM W
. C W
WW .100Y M .TW W
W . 1 00
O M .T W
W .100 OM
.T
W O • Read-modify-write C instructions W .C
WW .100Y.C M.TW W W
1 00Y
.
M .TW W . 100
Y
M .TW
W . O W O
W
WW .100Y.C M.TW
O • Jump/branch
WW .100Y.C M.TW
instructions WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O • Bit manipulation
WW .100Y.C M.TW
instructions WW .100Y.C M.TW
W instructionsO W O
W
WW .100Y.C M.TW
O • Control
W W .C O
W 4.6.2.1 0 Y .T
0Register/Memory W
Instructions .1 .1 M
W.1 Y.COM W W W .C OM WW 00Y.CO .TW
W Y W W
W
W .100 O M.TThese instructions
W
W .100 onOCPU
operate M.Tregisters and memory W W.1 locations.
.C OMMost of them
.C W .C W Y W
WW .100Y M TWtwo operands.
.use W One
W . 0Y
10operand O M
W
T either the accumulator
is .in W .100or theO M.T register.
index
W
WW .100Y.C MThe
O
.TWCPU findsW theWother 0operand 0Y.C in .TW
memory. WW .100Y.C M.TW
.1 M
W W .C O
W 00 Y .T W Table.14-1. Register/Memory M Instructions .1 M
W 00 .T W .1 M
W.1 Y.COM W W W.1 InstructionY .C OM
W WW Mnemonic 0Y .CO .TW
W W 00 Bit to M .T W 0
W
W .100 O M.T Add Memory Byte Wand.1Carry
.C O Accumulator W W.1 ADCY.COM W
C W W
WW .100Y. M.T
W Add MemoryW
.100
Byte to Accumulator Y
M.T
W
W
00
.1ADD OM
.T
W O W C O W .C W
WW .100Y.C M.TAND W Memory W Wwith Accumulator Y. .TW W 100
Y
M.T
Byte
W . 100 O M W .AND
C O
W O WW BIT .
WW .100Y.C M.TW
Bit Test Accumulator
WW .100Y.C M.TW . 100
Y
M .TW
O Compare Accumulator W O W .C O
W
WW .100Y.C MCompare .TW Index Register WW .100Y.C M.TW WW CMP . 1 00Y M .TW
W O
W O
WW
W . O .TW
with MemoryCByte
WW .100Y.C M.TW
CPX
WW .100Y.C M .TW
EXCLUSIVE OR Accumulator.1with 00YMemoryM Byte EOR
W O
O W O Y.C
W
WW .100Y.C Load .T W
Accumulator WW
with Memory.1Byte 0 0Y.C M.TW WW LDA .100 M.TW
W M
O Index Register with W W O W W .C O
WW .100Y.C Load . T W W Memory.1Byte 0 0Y.C M.TW WLDX . 1 00Y M.T
W
M W O W C O
W O
WW .100Y.C M.TW
W Y. .TW
WW .100Y.CMultiply M .TW W MUL
W . 100 O M
W O
W
WW .100Y.C M.TW
OROAccumulator with Memory
WW .100Y.C M.TW
Byte WW .100Y.C M.TW
ORA
SBC WW O
W W Y
Subtract
.C O Memory Byte and Carry
W W WW 0 Y .CO .TW
Bit from Accumulator
W 0 0 Y.C .TW
W .1 00 Store Accumulator M .T in Memory . 1 0 M STA W . 1 O M
W O
W
WW .100Store
O
Y.C Index Register .T W in Memory WW .100Y.C M.TW STX
WW .100Y.C M.TW
W W . C OM
W 00 Y
Subtract Memory .T Byte from W
Accumulator SUB .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W .100 O M .T W
W .100
W O WW
W O W O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W W
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
4.6.2.2 Read-Modify-Write W W.1 Instructions . C OM
W W
M .TW W
W . 100
Y
O M .T W
W .100 O M.T
.CO .TW .C WWlocation Y. C
00Y WWThese 1
instructions
00Y M .Tread
W a memory . 100or a register, M .TWmodify its contents, and
W . 1 O M .
W the modified
write O value back to theWmemory location W .C O or to the register.
0 0 Y.C .T W WW .100Y.C M.TW W . 1 00Y M .TW
. 1 M W O
WW 00Y.CO .TWNOTE: WDo WW 0 .CO .TW
not useYread-modify-write WW on
instructions
0 0Y.C M
registers with.TW write-only bits.
. 1 M . 1 0 M W . 1 O
W O
W W. 1
.C OM WW 00Y.COTable.T4-2. W Read-Modify-Write
W WW 00YInstructions .CO .TW
W 00 Y .T W W 1 M
W.1 Y.COM W W.1 Y.COM WInstruction WW. 0Y.COMnemonic
W W 00 .T W W
1 00 M .T W . 10 M .TW
. 1 M W . O Shift Left (Same as LSL) W O
WW .100Y.C M.TW
W O Arithmetic ASL
WW .100Y.C M.TW WW .100Arithmetic Y.C .TW
MShift Right W O ASR
W O W
WW .10Bit0Y .CO .TW WW .100Y.C M(1).TW
WW .100Y.C M.TW Clear M O
W .C O WW 00Y.CO .TW W WW 00Y.C BCLR
W
W W 0 0 Y .T W W 1Bit Set OM . 1 (1) .T
M
. 1 M W . W BSET
C O
W
WW .100Y.C M.TW
O
WW Clear 00Y
.C
Register M.T
W WW .100Y. CLR M.TW
. 1
W O W O
Y.C (One’s.TComplement)
W
WW .100YCOM .CO .TW
WW .100Y.C M.TW WW Complement 0 0 W
.1 M WW 00DEC OM
W W Y.C O
W W WW Decrement 0 Y .CO .TW W Y.C .TW
W . 1 00 M .T . 1 0 M W . 1 O M
O W O Y.C
W
WW .100Y.C M.TW WWIncrement 00Y
.C .TW WW .100INC M .TW
. 1
W Shift Y Left O M W O
O WW .100Y.C M.TW
W Logical (Same as ASL) LSL
WW .100Y.C M.TW WW . 1 0 0 .C M.TW
Logical Shift Right W LSR Y.CO
W O WW 00Y.CO .TW WW .NEG .TW
WW .100Y.C M.TW W Negate (Two’s .1 Complement) M W 100 O M
W O W
WW Left.1through .CO WW ROL 00Y
.C W
WW .100Y.C M.TW Rotate 00Y CarryMBit.TW W . 1 O M.T
O W O Y. C
W
WW .100Y.C M.TW WWRight.1through
Rotate .C
00Y CarryMBit.TW WW ROR .100 M .TW
W O
W O forW
W .CO WWTST(2).100Y.C M.TW
WW .100Y.C M.TW TestW Negative or
.1 00YZero M.TW W O
W W Y.C O
W 1. UnlikeW
W read-modify-write
Wother 0 Y .CO .Tinstructions, W BCLRW Wand 0 0Y.C .TW
W . 1 00 M .T . 1 0direct addressing.M W . 1 O M
BSET use W only O
W O
WW .100Y.C M.TW 2. TSTW is Wan exception .C .TW
00Yto the read-modify-write WW .100Y.C M.TW
sequence
. 1 M
W W .C O
W
becauseW W not write
it does
Y .CaOreplacement W value.
W WW 00Y.CO .TW
W 00 Y .T W 0 0 . T .1 M
W W 00 .T W
W
4.6.2.3 Jump/Branch
W .100InstructionsO M.T W.1 Y.COM W W W.1 Y.COM W
.C W W 100program .T
WW .10Jump 0Y instructions M.T
W
allow the CPU
W to
0
.10interrupt M.Tnormal sequence
the W.the
of OM
W O W C O W . C
WW .1counter. 00Y The
.C TW
.unconditional W W
jump instruction1
.
00Y (JMP) M
W the jump-to-subroutine
.Tand W . 100
Y
M .TW
M W . O W O
W
WW instruction 0
O
Y.C (JSR) .T W have no register WW operand. 0 0Y.CBranch . W
Tinstructions W W the 0CPU
allow
. 1 0Y.Cto M.TW
.1 0 .1 M O
Winterrupt OM
.Cthe normal sequence ofW theWprogram O
Y.Ccounter when
W a testW WW 0is0met.
condition Y.C .TW
WW If .the 1 0 0 Y
test condition M .T W W
is not met, the branch . 1 0 0 is not M .T
performed. W . 1 O M
W O
W
WW .100Y.C M.TW
O
The
W BRCLR and BRSET instructions
O WW cause a .branch CO based on the state WW of any Y.CO
W
W readable Y .C
00 bit in the W
T 256 memory locations.
.first W 1 0 Y
0 TheseM3-byte .T W
instructions
W
use . 1a00 M .TW
.1 O M W . O W .C O
WW
W
combination 0 Y.C W
of direct.Taddressing WWrelative
and 0 Y.C
0addressing. .TTheW direct address WW of.1the 00Y M .TW
1 0 . 1 M W O
.
WWto be00tested OM W O
WW signed 00Y.C
byte
Woffset Y.C is in.Tthe W byte following WW the.1opcode. 0 0Y.C The .Tthird
W byte is the .1 .T
W .1 The CPU
byte. O M finds the effectiveW branch
W destination
C O M by adding the third W W byte .C OM
W program Y.C W Y . Wbe testedWand its .100 Y
Wthe
to
W .100 counter O M.Tif the specified bit
W tests
W .100true. The O Mbit .Tto
W W .C OM
. C W Y . C W W –128 .10 0 Y
WW (set
condition
.100
or
Y clear) is.Tpart
M
W of the opcode. W The
.100
span of branching
M.T
is from
W
O W O
W
WW .100Y.C M.TW W W 0 0 Y .C
.T W WW
.1 M
W W Y . C O
W W WW 00Y.CO .TW
W 0 0 M.T .1 M
W W.1 Y.CO— W WW 00Y.CO
MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 Rev. 4.0 W Data Sheet
W
W .100 O M.T W W .1
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T .1 M
W Wto.1+127 from .C OM the address of the next W Wlocation Y CO theTbranch
.after W instruction. The CPU
.T W W also 0 0 Y . W W
Ttested bit to the carry/borrow .1 0 0 M . the
. 1 transfers the
M bit of condition code register.
.C OM
00 Y .T W .1 use BRCLR .1 M with write-only bits.
W.1 Y.COM W NOTE: W DoWnot .C OM or BRSET instructions WW 0on Y .CO .T
registers W
Y W W 0
. 1 00 M .T W
W . 100 O M .T W .1
C O M
WW 00Y.CO .TW WW .100Y .
WW .100Y.C M .TW 4-3. Jump
Table and Branch M .TW
Instructions
. 1 M W O W O
W. 1 OM Instruction WW O Mnemonic
.C WW 00Y.CO .TW W 0 Y.C W
W W
. 100 Y
M .T W W
W . 1 Branch ifOCarry M Bit Clear W .1 0
O M.T BCC
W
WW .100Y.C M.TW
O
WW .1Branch .C
00Y if Carry .TBitW Set WW .100Y.C M.TBCS W
M W O
W O W
WW .Branch .CO .TW WW .100Y.C MBEQ .TW
WW .100Y.C M.TW 1 00Y if Equal M W O
W O C
W
WW .100Y.C M.TW
O
WW Branch .C
00Yif Half-Carry .TBitW Clear WW .100Y. BHCC
M .TW
. 1
WBranch if Half-Carry O M W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
Bit Set
WW .100Y.C BHCS M .TW
W
Branch if Higher O W C O BHI
W
WW .100Y.C M.TW
O
WWBranch Y.C
0if0Higher .TW WW .100Y. M .TW
W . 1 O or MSame W O
BHS
W
WW .100Y.C M.TW
O
WW Branch.1if0IRQ 0Y.C Pin High .TW WW .100Y.C BIHM.TW
M WW 00Y.CO .TW
W W Y .C O
W W WW if IRQ 0 Y .CO T W W
W
W .100 O M.T
Branch
W .10 Pin Low
O M. W W.1 Y.COM W
BIL
W if Lower .C
WW .100Y.C M.TW WBranch
. 100
Y
M .TW W
W .100 BLOOM.T
O W O .C
W
WW .100Y.C M.TW WW if Lower
Branch
00Y
or.CSame
.TW WW .100Y BLS
M.T
W
W . 1 O M W O
W
WW .100Y.C M.TW
O Branch if Interrupt Mask Clear
WW .100Y.C M.TW WW .10BMC 0Y.C M.TW
W BMI .CO
WW 00Y.CO .TW
O Branch if Minus
W .C W W 0Y W
W W
. 1 00 Y
M .T W W
Branch if Interrupt
W . 1 Mask Set O M W
0
.1BMS O M.T
W O .C WW .BNE Y. C
WW .100Y.C M.TW Branch WifW Not Equal 1 00Y M .TW 100 M .TW
. W O
W O WW 00Y.CO .TW WW BPL 00Y
.C W
WW .100Y.C M.TW BranchW if Plus
.1 M W . 1 O M.T
O W O Y. C
W
WW .100Y.C M.TW
Branch Always WW .100Y.C M.TW WW BRA . 100 M .TW
O W O W .C O
W
WW .100Y.C M.TW Branch Never WW .100Y.C M.TW
Branch if Bit Clear
WWBRCLR . 1 00Y M.T
W
O W O BRNW .C O
W
WW .100Y.C M.TWBranch if BitW
W 0Y.C M.TW WW .100Y M.T
W
Set W.10 O BRSET W O
W O
WW .100Y.C M.TW
W Y.C .TW
WW .100Y.C M.TBranch W to Subroutine WBSR
W . 100 O M
W O W O W .C
WW .100Y.C M.T W
Unconditional WW .100Y.C M.TW
Jump WJMP . 1 00Y M.T
W
W O W C O
W
WW .100Y.C MJump
O
.TW
to Subroutine WW .100Y.C M.TW WW .100Y.
JSR
M .TW
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100
W O W C O W W .COM
.C W Y . W W 0Y
WW .100Y M.T
W W .100 M.T W.1
0
W O W W .C O W
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W W
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
4.6.2.4 Bit Manipulation W W.1Instructions .C OM
W W
M .TW W
W . 100
Y
O M .T W
W .100 O M.T
.CO .TW C set or WW bit Y. C
00Y WWThe .CPU 1 00Y
.can
M .TW clear any writable
. 10in0 the first M .TWbytes of memory, which
256
. 1 O M W
includes O
I/O registers and on-chip RAM W locations. O
.C The .CPU can also test and
W
0 Y.C .T W WW 00Y.C onM . W
Tstate WbitWin any . 1 0Ythe
0of M TWmemory locations.
. 1 0 M branchW . 1 based O the of any W first
O 256
.1
WW 00Y.CO .TW
M W O Table 4-4. Bit Manipulation W
WW .100YInstructions .CO .TW
WW .100Y.C M.TW
W .1 O M W C O W W .C OM Mnemonic
WW .100Y .C
.TW W W 0Y
10Bit
.
M .T W Instruction W . 100
Y
M .TW
M W . O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
Clear
WW .100Y.C M.T BCLR
W
W O
W O W
WW .Branch
Branch
.CO .TW
if Bit Clear
WW .100Y.C MBRSET
BRCLR
.TW
WW .100Y.C M.TW 1 00Y if Bit Set M W O
W O C
W
WW .100Y.C M.TW
O
WW Bit.1Set 00Y
.C .TW WW .100Y. MBSET.TW
W O M W O
W
WW .100Y.C M.TW
O
NOTE: Do not useWbit Wmanipulation O instructions on registers O
W with write-only bits.
W
WW .100Y.C M.TW
O
W 0 0 Y.C .T W WW .100Y.C M.TW
. 1 M
W .CO Instructions WW 00Y.CO .TW W WW 00Y.CO .TW
WW4.6.2.5 .10 0 Y
Control
M. T W W .1 W.1 Y.COM W
W C O W W .C OM W
WW .100Y. W
M.T These instructions
W act
Y
.100on CPU M .TW and control
registers
W 00
W.1 operation
CPU OM
.T
during program
W O W C O W .C
WW .100Y.C M.Texecution. W WW .100Y .
M .TW W . 100
Y
M .TW
W O W O
W
WW .100Y.C M.TW
O
W Table O 4-5. Control Instructions W O
W
WW .100Y.C M.TW
O
WW Mnemonic O
W .C O WW 00Y .CO .TW
Instruction
W 0 Y.C W
W W
. 1 00 Y
M .T W W
Clear CarryW Bit.1 O M W
0
.1CLC O M.T
W O .C WW .1CLI .C
WW .100Y.C M.TW Clear W
W
1 00Y M .TW 00Y M .TW
O
Interrupt Mask
W . O W .C O
W
WW .100Y.C M.TW No Operation WW .100Y.C M.TW WW NOP . 1 00Y M.T
W
W O W C O
W O
WW Pointer 00Y.C WW RSP Y. .TW
WW .100Y.C M.TW Reset Stack . 1 M .TW W . 100 O M
W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
Return from Interrupt WW RTI .100Y.C M.TW
W O
W W Y .C O
W
Return from Subroutine
W WW 00Y.CO .TW W WRTS
1 0 0Y.C .TW
W .1 00 M .T Set Carry Bit W . 1 O M SEC W . O M
W
WW .100Y.C M.TSet
O
W Interrupt Mask WW .100Y.C M.TW WW .100Y.C M.TW
W W .C O W W Y .CO .TW W
SEI W
W 0 Y .CO .TW
W 00 Y .T W W
Stop Oscillator and Enable 0
IRQ0 Pin STOP .1 0 M
W.1 Y.COM Software W W.1 Y.COM W WW 00Y.CO .TW
W W Interrupt W 00 .T W
SWI
W 00
W.1 Y.COMTransfer
.T W.1 Register .C OM W W.1 Y.COM W
W W
W Y W .100 M.T
Accumulator to Index TAX
W . 1 00 M .TW W
W .100 O M .T W C O
W O Transfer Index RegisterW to Accumulator .C TXAWW Y. .TW
WW .100Y.C Stop M .TCPUW W . 1 00Y M .TW W . 100 OM
W O Clock and EnableW Interrupts O WAIT W .C
WW .100Y.C M.TW WW .100Y.C M.TW W . 1 00Y M.T
W
O W O W .C O
W
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y M.TW
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W .100 O M .T W
W .100
W O WW
W O W O
W O Rev. 4.0 W O
WW .100Y.C —M
W O W W
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
4.6.3 Instruction Set
W .100
WSummary OM
.T
W W.1 Y.COM W
W .C W
M .TW W
W . 100
Y
O M .T W
W .100 O M.T
.CO .TW Y.C Instruction WW .100(Sheet Y. C TW
00Y WW Table . 1 004-6. M .TW Set Summary M1 .of 6)
.C W Y . W W 0 Y T W
00Y .TW W 100 .T .10 M. Effect
Operand
M
Address
1 . O
Opcode
. M O W
Cycles
W .C
WW 00Y.COSource .C WW .100Y
Mode
WW Operation .TW W
. 1 M
Form .TW . 1 00Y M Description
W O M
on .TCCR
W O
WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y.C H M I .N TW Z C
. 1 O M W O W .C O
W
WW .100ADC Y.C#opr TW WW .100Y.C M.TW WW .100Y M.T
W IMM A9 ii 2
ADC opr M. W O W O B9 dd 3
Y.C
DIR
W O W .C W W EXT
WW .10ADC 0Y.C opr
.T W
Add with Carry W .1 0 0 Y
M .T W W
A ← (A) + (M) + W (C) . 1 0 0 — M .T
O IX2 D9 ee ff 5
C9 hh ll 4
W ADCYopr,X .C OM WW 00Y.CO .TW W W 0 Y.C W
W W
. 1 00
ADC opr,X
M .T W W
W . 1 O M W .1 0
O M.T IX1 E9 ff 4
W ADC ,X O WW .100Y. C
WW .100Y.C M.TW WW .100Y.C M.TW .TWIX F9 3
W O W O M
WW ADD
WADD #opr
0 Y.C
O
.T W WW .100Y.C M.TW WW .100Y.C M.TW IMM AB ii
BB dd 3
2
.1 0opr
M W O W O DIR
W ADD opr .CO
WW ADD.1opr,X W Carry WW .100Y.C M.TWA ← (A) + (M) WW .100—Y.C M.TEXT W CB hh ll 4
00Y Add without
M .T
W O W .C O IX2 DB ee ff 5
W W opr,X Y.CO W Y .C W W W 0 Y T W EB ff
M.IX FB
ADD IX1 4
W ADD .,X100 M .TW W
W . 100 O M .T W .10
C O 3
W W . C O W Y .C W W W 0Y . . T W
Y W W 0 .T 0
W AND #opr
W .100 OM
.T 0
W.1 Y.COM W W W.1 Y.COM IMM
W
A4 ii 2
W .C W W 0 .T dd
.TW
AND opr DIR B4 3
WAND opr .100Y M
W
W . 100 O M .T W .10 O M C4 hh ll 4
W O WW— — .100Y— IX2M.TD4 .C EXT
WANDWopr,X 00Y
.C AND.TW
Logical
WW .100Y.C MA.T ←W (A) ∧ (M) W ee ff 5
. 1 M W O W O
WW .100Y.C IX M.F4
ff
AND opr,X
WW
AND ,X
W
0 Y .CO .TW W W 0 0 Y.C .T W IX1 E4
TW 3
4
0
W W WW 00Y.CO .TW W dd 5
ASLW opr
W .100 O M.T W .1
C OM W W.1 YDIR .C OM38
ASLA
WW .1Arithmetic .C
00Y ShiftMLeft W as LSL) W
.T(Same
W
1 00Y
.
M .TW W
— — W .10

INH
0 INH 58 48
M .TW 33
ASLX
O W . C
O 0 O
.C 68 .ffTW6
ASL opr,XWW
0 Y.C W WW .100Y.C b7
.TW b0 WW .100Y IX1
ASL ,XW 0 .T M 78M
W W.1 Y.COM W WW 00Y.CO .TW W WW 00Y.CO IX
.T
5
W
W 00 .T W .1 M
ASR opr W.1 Y.COM W W W.1 Y.COM W WW DIR 0 Y .C37O dd .T5W
W W 0
ASRA W
W .100 Shift Right O M.T
W
W .100 OM
.T
— — W W
.1INH
INH Y.57
47 M 3
CO 3TW
ASRX
W Arithmetic
Y .C W W W 0 Y . C T W
C
W 0 0 .
ASR opr,X W
W .100 O M.T W .10b7 O Mb0. W
1
W.IX1 67 O
.C ff M 6
WW .100Y .C Y 5 TW
WW .100Y.C M.TW .TW 100
ASR ,X W IX 77
M . M .
Wif Carry Bit Clear O W O W W .C O
WWPC ←.(PC) .C+ rel ? C .=T0W — — — —W— REL 0024Y rr 3 .TW
WW .100Y.C M.TW
BCC rel Branch +2
Y
W 100 OM W(b0).1 11 dd O5M
O 0Y.ddC 5 M.TW
W C WDIR
W Y . C W W W 0 Y . .T W W 0
W 0 0 .T .1 0 M DIR (b1). 1 13
O
W.1 Y.COM W WW 00Y.CO .TW W WW
DIR (b2) 15 Y
0 dd.C 5 W
W W
Clear Bit nW.10
0 M .T W
W .1 ← 0 OM — — — — — DIR (b3) W . 17 dd 5 OM.T
1 0
BCLR n opr O Mn W(b4) 19 00ddY. 5 C
WW .100Y.C M.TW WW .100Y.C M.TW WDIR
. 1 dd 5 OM.T
W
W O W O DIR (b5) W 1B
W 1D 0dd0Y5.C
WW .100Y.C M.TW WW .100Y.C M.TW W(b6)
DIR
.1dd 5 OM.T
W
O W O DIR (b7) W1F . C
BranchW
WW 00(Same Y.C as BLO).TW PC W
W
← (PC) + 2.+
.C
0rel0?YC = 1 M—.T—W— — — REL WW 25 .1rr00Y M .TW
BCS rel if Carry Bit Set
.1 M 1 O W 3 O
BEQ rel Branch ifW WW 00Y.CO .TW
Equal PC ←W W+W2 + rel0?0Y
(PC) Z=1
.C — — .TW — — — REL WW27 rr.1003 Y.C M.TW
1 . 1 M W O
BHCC rel W
Branch if Half-Carry W.Bit ClearY.COM W PC ← (PC)W W
+ 2 + rel ? H Y
0
O
= .0C — — —W — — REL WW 28 rr 300 Y.C .T
W 00 W .10 .T .1
BHCS rel Branch if Half-CarryW Bit.1Set O M.T PC ← (PC) +W 2W+ rel ? H = 1 .CO
M
— — — — — REL 29WW rr 3 Y .C OM
BHI rel Branch if HigherWW .100Y.C M.TW PC ← (PC)W + 2 + relW
00Y
? .C1∨ Z = 0 —O— M— .T— W
— REL
W
22 rrW.3
100 OM
W .C O W Y .C W W W 0Y .C
BHS rel Branch if Higher WorWSame .100Y W
M.T PC ← (PC) + 2 +WrelW
W 10= 00 — O
? .C —M —.T — — REL 24 rr
W3.1
0
W O .C W
BIH rel Branch if IRQ Pin WHigh W Y.C WPC ← (PC) + W 2 + rel ? IRQ =010Y— — — —
M.T
W REL 2FW rr 3
—
W .100 O M.T W .1
C O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W W
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y . C W
W O M.T
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W .100 4-6.
WTable OM
.T
Instruction SetW Summary W.1 Y(Sheet .CO 2.Tof
M
W W W 0 Y .C
.T W W 0 0 W6)
. T . 1 0 M W .1 O M
OM WW 00Y.CO .TW WW .100Y.C M.TEffect W
Operand
Address
Y.C
Opcode
W
Cycles
0 T W
Mode
. 1 0 M .
Source . 1 M W O on CCR
W Y .CO Form W W WWOperation 0 Y .CO .TW W W
Description
0 0 Y.C .T W
0 M. T 0 . 1 M
.10 W.1 Y.COM W WW 00Y.CO H I.TNWZ C
WW 00Y.CBILOrel .TW Branch if IRQ WW Pin Low.10
0 .T W
PC ← (PC) + 2 +W rel.1? IRQ = 0 O —M
.1 M W OM .C
— — — — REL 2E rr 3
WW 00YBIT .CO W W W 00 Y .C
.T W W W 0 0 Y .T W
W .1 BIT #opr O M.T W.1 Y.COM W W W.1 Y.COM W IMM A5 ii
B5 dd 3
2
.C opr W W 00 .T DIR
WW .100BIT Y opr
M .TWBit Test Accumulator W 100 ByteOM.T
.Memory W.1 Y.— O—M — EXT C5 ee hh ll 4
W C O
BIT .opr,X W W
with
Y . C W
(A) ∧ (M)W 0 C W ff 5
W W 0Yopr,X M.T W W 00 .T W . 10 M .T IX2 D5
. 1 0BIT . 1 M W O ff
WW 00Y.CO .TW
IX1 E5 4
W W BIT Y ,X.C
O
W W W W 0 0 Y.C .T W IX F5 3
W 00
.1BLO M.T W .1 O M W .1 OM
W O W .C ← W Y . C W
WW .100Y.C M.TW 00Y .TW W 100 .T
rel Branch if Lower (Same as BCS) PC (PC) + 2 + rel ? C = 1 — — — — — REL 25 rr 3
W . 1 M . M
WBLS relY.CO BranchWif Lower or Same WW O PC ← (PC) + 2 + rel ? CW∨ Z = 1 — Y—.C— — — W W O
W Clear .100Y.C M.TPCW← (PC) + 2 +W
REL 23 rr 3
WW BMC 0 0 .T . 1 0—0 — — —M .T
W.1 rel
OM Branch if Interrupt Mask W O
W(PC) + 2 + relW? W
rel ? I = W0
.CO — REL 2C rr 3
WW BMI.1rel00Y.C Branch .T W
if Minus WW .100Y.C MPC .T← N = 1 .1— 00—Y— — —M.TREL W
2B rr 3
W O M W C O W W O
.C— — REL
W BMS rel Y.C Branch if W SetW Y . ← W W 0 Y T W
W . 1 00 M .T Interrupt Mask W
W . 100 O M
PC .T (PC) + 2 + rel ? I = 1
W
—
.10 — —
O M. 2D rr 3
Wrel Y.CBranch O if Not Equal W=W . C
WW
BNE
00 Branch W
.TPlus WW .100Y.C PC M
← (PC)
.TW
+ 2 + rel ? Z 0 — —0
. 10
—Y— — REL
M .TW26 rr 3
rel.1 M O ← W O
BPLW
W Y .CO .TW
if
W WW 00Y.C PC (PC)
. T W
+ 2 + rel ? N
WW .100Y.C M.TW
= 0 — — — — — REL 2A rr 3
WBRA rel .10 0 .1 PCM ← (PC) + 2 + rel ? 1 = 1
WW 00Y.CO .TW
BranchM
W W .C O Always WW 00Y.CO .TW W
— — — — — REL 20 rr 3
Y W W
W
W .100 O M.T W .1
.C O M W W.1 Y.C DIR M
(b0)
O(b1) 01
W
dd rr 5
WW .100Y
DIR 03 dd rr
WW .100Y.C M.TW .TW W . 100 DIRO M T dd rr 55
.05
M W (b2)
W O
Y.Cif Bit n Clear WW .100Y
W .CO Wrel ? Mn = 0 W—W— — .— .C (b3) 07.Tdd
00 YDIR Wrr 5
WWn opr rel
BRCLR
. 1 0 0
Branch
M .T W PC ← (PC) +.T
M 2+
W 1 DIR O
(b4)M09 dd rr 5
O W O C
Y. (b5) 0B .T
W
WW .100Y.C M.TW WW .100Y.C M.TW WW .100DIR M ddW rr 5
W O W C O W W DIR . C O
(b6) 0D dd rr 5
WW .100Y.C M.TW WW .100Y. .TW W 0Y(b7) 0FMdd.TrrW5
.10DIR
WBranch Never O W O M W
W— — 0REL .CO
BRN rel W Y .C W W W PC0← Y C + 2 + rel
.(PC) T W?1=0 — — W — 0 Y 21 rr.TW 3
W 1 00 M .T . 1 0 M . W . 1 O M
. O W O Y.C00 dd rr.T5W
W
WW .100Y.C M.TW WW .100Y.C M.TW WW .DIR 1
(b0)
00(b1) Mrr 5
W O W .C O W
DIR
WDIR (b2)Y.02 C Odd rr 5TW
C W .TW
WW .100Y. 0 04 dd
M .TW W . 1 00Y M
W
W .
DIR 10(b3) 06 ddO M.5
rr
BRSET n opr rel Branch W if Bit n Set O W
PC ← (PC) + C2 O
+ rel ? Mn = 1 — — — — W .C
WW .100Y.C M.TW WW .100Y .
M .TW W DIR.1(b4) 00Y08 dd rr M5 .TW
W .C O WW 00Y.CO .TW W
W
DIR (b5)
WDIR (b6)000C Y ddCO
0A .dd rr 5
W
W W
.1 00 Y
M .T W W
W . 1 O M W .1 0E dd rrrrO55M.T
W O WW .100Y. C
WW .100Y.C M.TW
DIR (b7)
W O W O DIR W(b0)
W (b1) 1200Y10 dd
.C O5
WW .100Y.C M.TW WW .100Y.C M.TW WDIR . 1 dd 5
M.T
W
W O DIR W
(b2) 14 dd C5 O
WW 00Y.CO .TW WW Mn .C .T—W— — — — W
W Y. W
BSET n opr SetW Bit n .1 M . 1 0←01Y M DIR (b3) 16
W . 100dd 5 OM.T
W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW 18 dd
DIR (b4)
DIR (b5) 1A.10
0Y5.C M.TW
dd 5
WW O
W W Y .C O
W W WW 00Y.CO .TW DIRW (b6) 1C dd 0Y
0
1 5
5 .C
.TW
W .1 00 M .T . 1 O M DIR (b7) 1E W .dd O M
W O WW 00(PCL) Y.C WW .100Y.C M.TW
WW .100Y.C M.TW PC ←W (PC) + 2; push
. 1 M .TW
W W .C O
W
SP ← (SP)W Wpush (PCH)
– 1;
Y .CO— —.T—W— — REL WAD WWrr 600Y.CO .T
BSR rel Branch to Subroutine
W 00 Y .T W
SP ← (SP) –.110 0 .1 M
W.1 Y.COM W PC ← W W+ rel Y.COM W WW 00Y.CO
W (PC) W
W
W .100 O M.T
W
C← 0W
.100 M.T
—O— — — 0 98 WW 2
.1
.C OM
CLC Clear Carry Bit
.C W Y .C W INH
W 0Y
WW
Clear Interrupt Mask W.1
00Y M.T
W W
I ← 0 W.
100 — O 0M
.T
9A WW
.10
CLI O W .C — — — INH 2
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O Rev. 4.0 W O
W O W W
MOTOROLA WW .10Central 0Y.C ProcessorM .TWUnit (CPU) W 47
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W .100 4-6.
WTable OM
.T
Instruction SetW SummaryW.1 Y(Sheet M
.CO 3.Tof
W W W 0 Y .C
.T W W 0 0 W6)
.T . 1 0 M W .1 O M
Operand
Address
Y.C
Opcode
W
Cycles
0 T W
Mode
. 1 0 M .
Description
0 0 Y.C .T W
0 M. T 0 W. 1 OM
.10 W.1 OM H I N Z C
.1
WW 00YCLRA
CLROopr
.C
M W W Y .C O
W W
M ← $00
W W
0 Y .CO .TW DIR 3F dd 5
W W 00 .T A ← $00 .10 INH 4F
.1 CLRXOM.T Clear Byte
3
W W.1 Y.COM W X ←W $00W .C —OM — 0 1W — INH 5F 3
.C W W← $00 .100 Y .T
WW .100CLR Y opr,X .TW W . 1 0 0 M .T M M IX1 6F ff 6
W W CLR.C ,XO
M
W W W Y . C O
W MW← $00 WW 00Y.CO .TW IX 7F 5
W . 1 00Y M .T W . 1 00 M .T W . 1 O M
W O
WW .1CMP
W CMPY#opr .CO WW .100Y.C M.TW WW .100Y.C M.TW IMM A1 ddii 2
00 opr M.TW
WW 00Y.CO .TWEXT C1 hh ll 4
DIR B1 3
W CMP Y C O W W .C O
W opr. W W with Memory 0 Y .T W W
W
W.CMP100 opr,X OMCompare .T Accumulator 0 Byte
W.1 Y.COM W
(A) – (M)
W W.1 — Y—.COM W IX2 D1 ee ff 5
W CMP Y
opr,X.C W W W 0 .T W 0 0 .T ff
W . 1 0
0,X M .T W . 1 0
O M W . 1 O M IX E1 IX1 4
W CMP
C O W .C W W Y .C W F1 3
WW .100Y. .T W W 1 0 0 Y .T W .1 0 0 M .T
W opr OM W. OM M ← (M) = $FF – (M)WW Y.C
O DIR 33 dd 5
WW .100Y.C M.T
COM
WWCOMA.100Y.C M.TW AW ← (A) = $FF – W (A) . 1 0 0 .TW 43
MINH 3
W O W C O ← W W .
C O
COMX .C Complement Byte (One’s W
Complement) . X W(X) = $FF – (X) — — Y 1 INH W 53
.T 63 ff 36
WW COM opr,X
. 1 00Y M .TW W . 1 00Y M M.T ← (M) = $FF – (M)
W
W . 100 O MIX1
W,X O W O W .C IX .TW
WW .100Y.C M.TW
COM
WW .100Y.C M .TW= $FF – (M)W W.100Y OM
M ← (M) 73 5
O W O .C
CPX W
W#opr Y.C .TW WW .100Y.C M.TW WW .100Y IMMM.TA3 W ii 2
WCPX opr .100 M W O W O
DIR B3 dd 3
CPXW
W .C O W Y . C W W W 0 Y .CEXT .C3 T W
opr Y W W Byte .100 .T– (M) — —W.10 M D3 ee ffll 45
hh
W
CPX opr,X W .100CompareOIndex M.TRegister with MemoryW W .C O M(X) W

Y . C O
IX2
W
CPX W
Wopr,X . 1 0 0Y.C M.TW W . 1 00Y M .TW W
W .100 IX1OME3.T ff 4
W O C
CPX ,X W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y.IX F3 M .TW
3
W O← (M) – 1 W O
.C 3A .TW5 dd
DEC opr
DECA W
WW 00Y.CO .TW WW .100Y.C A ←M
M
(A).T–
W
1
WW .100Y DIR
INH 4AM 3
DECX W
.1
WDecrement .C OM
Byte WW 00Y.CX O ← (X) – 1 W — — W W W
— 0 Y
INH .CO 5A .T W3
W 00 Y .T W W . 1 M ←O(M) M T
–. 1 . 0
1 IX1 6AOMff 6
DEC opr,X . 1 M W W
DEC ,X W
WW .100Y.C M.TW
O
WW .100YM.C← (M)M – 1.TW WW .10IX0Y.C7A M.T5W
W W .C O WW 00Y.CO .TW W WW IMM 0 CO ii 2TW
Y.A8
EOR #opr Y W W 1 0 .
EOR opr
W
W .100 O M.T W .1
.C O M W W.DIR B8.C OddM 3
W
EOR opr WW EXCLUSIVE0OR
0 Y.CAccumulator .T Wwith Memory W
W
. 1 00←Y(A) ⊕ (M)M.TW — — W — EXT . 1 00YC8 hh ll M 4 .T
ByteW. 1 OM W A O W O
WW .100Y.C M.TW WW IX2 0D8Y.C 54M.TW
EOR opr,X ee ff
EOR opr,X WW .100Y.C M.TW IX1.10 E8 ff
W O
W O
EOR ,X W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW IX .10F80Y.C 3 M.TW
1O
W 3C Y dd.CO
INC opr W W Y .C O
W W WWM ←0(M) 0 Y +.C
.T W W W DIR
1 0 0 5
.TW
INCA W . 1 00 M .T W A.←1 (A) + 1 OM INHW.4C
C3 OM
W O .C W 5C 00Y. 3 W
INCX
WW Byte.100Y.C M.TW
Increment WW X ←.1(X) 00++Y11 M .T—W— — WINH . 1 ff 6 OM.T
W ←
.CO .TW W
WIXW 7C.100Y5.C M.TW
INC opr,X M (M) IX1 6C
W O
INC ,X WW .100Y.C M.TW WWM ← (M) . 1 0+0Y1
M
W W . C O WW 00Y.CO .TW W WW 0 Y .CO .TW
JMP opr W 00 Y .T W W DIR BC dd 0
.1 ll 2 M
JMP opr W.1 Y.COM W W.1 Y.COM W EXT W CC Whh 3 Y.CO
JMP opr,X W
W Jump .100
Unconditional .T PC
W
W← Jump Address 1 0 0 —
M .
— W
T — — — IX2 DC ee.1ff 04 0 M .TW
W OM W . O W
W ff 300Y.C O
JMP opr,X
WW .100Y.C M.TW WW .100Y.C M.TW IX1 WEC
FC W.12
.T
JMP ,X
W O W C O IX
W .C OM
WW .100Y . Y
WW .100Y.C M.TW M.T
W W
W .100 OM
WW .100Y . W Y W W 0 0
W O M.T
W
W .100 O M.T W W.1
W .C
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W W
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W .100 4-6.
WTable OM
.T
Instruction SetW Summary W.1 Y(Sheet M
.CO 4.Tof
W W W 0 Y .C
.T W W 0 0 W6)
.T . 1 0 M W .1 O M
Operand
Address
Y.C
Opcode
W
Cycles
0 T W
Mode
. 1 0 M .
W Y.CO Form W W WWOperation 0 Y .CO .TW W W
Description
0 0 Y.C .T W
.10 0 M. T .1 0 M W. 1 OM H I N Z C
.1 JSR opr M
.COopr .TW W.1 Y.COM W PC ← (PC) +W W= 1, 2, orY3).CO DIR BD dd 5
WW 00YJSR W W 00 .T W n (n
Push (PCL); SP ← (SP)
0
.10 – 1 —OM .T W EXT CD hh ll 6
. 1 JSR opr,X
O M Jump to Subroutine W.1 O M W
W ← (SP)0–01Y .C — — — — IX2 DD ee ff 7
W
WW .100JSR Y.Copr,X .TW WW .100Y.C M.TW Push (PCH); WSP
PC ← Effective Address .1 M.T
W IX1 ED ff 6
M W O W O
W
WW .10LDA
JSR ,X O
0Y.C .T W WW .100Y.C M.TW WW .100Y.C M.TW IX FD 5
M W O W O
WW .100Y.C M.TW DIR B6 dd 3
#oprO IMM A6 ii 2
W
WW .1LDA 0 0Yopr.C .T W WW .100Y.C M.TW
W LDA opr M
.CO Load W W Y.C
O
W
W
WW .100—Y.— CO —TWEXT C6 hh ll 4
WW .LDA 1 0 0 Y
opr,X
M .T W Accumulator with W Memory Byte
.1 0 0 M .T A ← (M)
W O M. IX2 D6 ee ff 5
W O W C O W .C
WW LDA
LDA opr,X.C
0 0 Y .T W WW .100Y. M .TW W . 1 00Y M .TW IX1 E6 ff 4
W . 1 ,X
O M W O W W . C O IX F6 3
W Y .C W W W 0 Y .C .T W W 0 0 Y .T W
W LDX.1#opr 00 .T 0
W.1 Y.COM W .1 M IMM AE ii 2
WW opr Y.COM W
LDX W W WW 00Y.CO DIR .TW CE BE dd 3
W LDX opr 0 0 .T W . 1 00 M .T . 1 M
1 O
.CO .TWX ← (M) WWW— —00Y.C— IX2.TWDE ee ff 5
hh ll 4
W
.
Wopr,X . C OMIndex Register with Memory
Load WW Byte
Y
EXT
LDX Y W W 0
W LDX opr,X
W .100 OM
.T 0
W.1 Y.COM W W W.1 Y.COMIX1 W EE ff 4
W . C W W 0 W 0 0 .T
WLDX ,X .100Y M. T W 0 .T . 1 IX
M FE 3
W . C O W W.1 Y.COM W W W Y .C O
W
Wopr 00Y W W .100 M.T
W 00 M.T38 dd
W M.T W.1 Y.CO
LSL DIR 5
LSLA W.1 O W W . C O W INH 48 W 3
WW .100Logical
LSLX Y.C Shift Left .TW (Same as ASL)W .1 00Y C M.TW 0 W — — .10 0
INH M.58
T 3
W O M W C Ob7 W W . C O
LSL opr,X .C W Y . W b0
W 0 Y IX1 68 T W 6
W,XW .100Y . ff
LSL M .TW W
W . 100 O M .T W .10 IX OM
C 78 5
W W . C O W Y .C W W W 0 Y . .T W
Y W W 0 .T 0
W
LSR opr
W .100 O M.T 0
W.1 Y.COM W W W.1 Y DIR .CO34 dd
M 5
LSRA W W 0 Y .C T W W W 0 0 .T W 1 0 0 INH 44 .TW3
.10 Shift Right . W.1 0 Y.COM W C 0 W
. INH O M
LSRX
W WLogical .C OM W — — W
W

0 Y .C 54 .TW 3
LSR opr,X W 0 0 Y .T W W 1 0 0 b7 . T b0 . 1 0 IX1 64 Mff 6
LSR ,X W.1 Y.COM W W W. .C OM WW 0IX0Y.C74O .T5W
W Y W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM 1 W
Y.C W X :Y .C W 0 —— W— 0 .INH 00 42 .T
MUL
WWUnsigned .100
Multiply
M.T
W W .100
A ← (X) × (A)
M.T W 1 Y.COM1 W
W O W .C O W
NEG opr WW .100Y.C M.TW WW M.1←00–(M) Y = $00 – (M)
M .TW W DIR.100 30 ddOM5 .T
O W O W W Y.C 3 .TW
NEGA WWByte0(Two’s
WNegate 0 Y.CComplement) .T W WW XA ← ← –(A)Y=.C
1 0 0 = $00$00 – (A) W
.T — — W INH . 1 0040 3M
NEGX
W.1 Y.COM W W . –(X) – M
(X)
O– (M) WW
INH 50
.ffCO6 .TW
NEG opr,X W W M ← –(M) Y
= . C
$00 W W IX1 60
0 0 Y
W 00 .T W M ←.–(M) 00 $00 – (M) .T .1 5 M
NEG ,X
W.1 Y.COM W W W1 =Y .C OM
W WIXW 7000Y.CO W
W W M.T
NOP
W
No Operation.10
0 M .T W
W .100 O M .T — — — — — INHW.9D 1
C 2 O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100iiY. M .TW
ORA #opr
W O IMM W AA
W BA 0dd0Y3.C
2 O
ORA opr
W WW 00Y.CO .TW WW .100Y.C M.TW WDIR
.1hh ll 4 OM.T
W
ORA opr . 1 O M W O EXT WCA .C
ORA opr,X
Logical ORW
W
W
Accumulator
0Y.C M.TW
with Memory
WW A ← (A) ∨ (M)Y.C
00
— —W —
.T WW DA ee
IX2 . 10ff0 5
Y
M .TW
.1 0 W . 1 O M W 4 Y.C O
W O IX1 W ff
WW .100Y.C M.TW
ORA opr,X EA
ORA ,X WW .100Y.C M.TW IXW FA . 1003 M .TW
O W O W .CO
W
WW .100Y.C M.TW WW .100Y.C M.TW WW 39 dd .15 00Y .T
ROL opr
W O W .C O
DIR
W W 3 Y.COM
ROLA
WW 00YBit
.C W WW .100Y — —M.TW INH 49
W59 .3100
ROLX Rotate Byte Left through.1
W
Carry
O M.T C
W W .C O INH
W W Y .C OM
ROL opr,X
WW .100Y .C W b7 b0 Y W IX1 W
69 6 0 0
W .100 M.T
ff
ROL ,X
W O M.T W .C O IX 79
W W5.1
W
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O Rev. 4.0 W O
W O W W
MOTOROLA WW .10Central 0Y.C ProcessorM .TWUnit (CPU) W 49
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W .100 4-6.
WTable OM
.T
Instruction SetW SummaryW.1 Y(Sheet .CO 5.Tof
M
W W W 0 Y .C
.T W W 0 0 W6)
.T . 1 0 M W .1 O M
Operand
Address
Y.C
Opcode
W
Cycles
0 T W
Mode
. 1 0 M .
Description
0 0 Y.C .T W
0 M. T 0 W. 1 OM
.10 W.1 OM H I N Z C
.1
WW 00YRORA
ROR
.CO .TW
M
opr
W W Y .C O
W W WW 00Y.CO .TW DIR 36 dd 5
W 00 .T W.1 C Y.C—OM
INH 46 3
W .1 RORXOM
.C Rotate Byte Right through
W W.1 CarryYBit .C OM
W W — W INH 56 3
WW .100ROR Y opr,X .TW W 0 0 .T b7 W b0 .100 M .T
. 1 M IX1 66 ff 6
W W ROR.C ,XO
M
W W W Y . C O
W W WW 00Y.CO .TW IX 76 5
W . 1 00Y M .T W . 1 00 M .T W . 1 O M
W RSP O Reset Stack Pointer WW .CO .TW SP ← W W .C
00Y— — —M . —W INH 9C
WW .100Y.C M.TW
$00FF —T 2
W . 1 00Y M W .1 O
W O W O ← W Y. C
WW .100Y.C M.TWSP ← (SP) + W
SP (SP) + 1; Pull (CCR)
WW .100Y.C M.TW 1; Pull (A) .100 M .TW
W O
WRTI O Return from Interrupt WW .CO .TW SP ← (SP) + 1; Pull
WW(X) .100Y.C M .TW
WW .100Y.C M.TW
INH 80 9
W . 1 00Y M SP ← (SP) + 1; Pull (PCH)
W O W O WW 00Y.CO .TW
WW .100Y.C M.TW WW .100Y.C MSP .TW ← (SP) + 1; Pull W(PCL)
W OReturn from Subroutine WW . CO SP ← (SP) + 1; Pull (PCH) W W.1 Y.COM W
.C W
W W RTS
. 1 00Y M .TW W
W . 100
Y
O M SP.T ← (SP) + 1; Pull (PCL)
W
W .1 —0 — — —
—0
O MINH.T 81 6
W O WW .100Y .C
WW SBC #opr 0Y.C
0 .TW WW .100Y.C M.TW MIMM .TWA2 ii 2
. 1 M O W O
SBCW opr
W opr 00Y.C O
W W WBitWfrom 00Y.C .T W W W
1 0 0 Y.C EXT DIR W
.T B2 dd 3
WSBC M. T . M hh ll 4
W.1 Y.COM
Subtract Memory Byte and Carry C2
W .1 O A ← (A) – (M) – (C)
W —W— Y.COIX2 D2 W
SBC opr,X C
Accumulator
. W W W 00
ee ff 5
W W
SBC opr,X.100Y M.T
W W
W .100 O M.T W.1 Y.CO IX1 M.TE2 ff 4
W O .C W TW 3
W ,X .100Y.C M.TW
SBCW WW .100Y M .TW W . 100 IX
M .F2
O W O W .C O
SEC WW
W 0 Y.C Bit .TW
Set Carry
WW .100Y.C MC.T ←W 1 W—W— — .— 1 001 Y INH M99.TW 2
0 .CO 9B .TW 2
W.1 Set Interrupt
OM W O I←1 — W 1 W
WW .100Y.C M.TW
SEI Mask — — — YINH
WW .100Y.C M.TW W .1 00 M
STA opr W O W C O W W DIR.COB7 .dd 4
STA opr W W 0 0 Y. C
.T W W W
.1 0 0 Y .
M .T W W . 1 0 EXT C7MhhTllW5
0Y
.1 AccumulatorOMin Memory W O W O
STA opr,X WStore
WW .100Y.C M.TW
M ← (A) — — W
W —.100IX2 Y.C D7 ee.ffTW 6
STA opr,X WW .100Y.C M.TW W IX1 E7
O M ff 5
W C O W W .C O W Y .CF7 4W
STA ,X W . .TW Y W W .10
IX0 M. T
W .1 00Y M
W
W . 100 O M .T W C O
O
W Oscillator and Enable IRQ Pin WW— .INH .
WW .100Y.C M.TW WW .100Y.C M.TW Y8E .2TW
STOP Stop — 0 — —
W 100 O M
O W O .C
W WW EXT
dd
WW .100Y.C M.TW
STX opr DIR Y BF 4 W
STX opr WW .100Y.C M.TW W . 100 CF hhOll M5 .T
StoreWIndex Register O W O W IX2 00DFY.C
WW .10M0Y←.C — — W—
.TW
ee ff 6
WW .100Y.C M.TW
STX opr,X In Memory (X)
STX opr,X M .TW IX1
W . 1 EF ff O5M
W O C
STX ,X W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW IX .10FF0Y. 4 M.TW
W A0 Yii.CO
SUB #opr W W Y .C O
W W WW 00Y.CO .TW W WIMM
00 2
.TW
SUB opr W . 1 00 M .T .1 O M DIRW.1 B0 dd 3 OM
W COAccumulator W .C W C0 0hh Y. C W
SUB opr
WWMemory
Subtract 0Y.from
0Byte .TW WW A ←.(A) 1 00– Y (M) M .T—W— WEXT . 1 ee0 ffll 45 OM.T
SUB opr,X
W .1 O M W O IX2 W
W E0 0ff0Y4.C
D0
SUB opr,X WW .100Y.C M.TW WW .100Y.C M.TW WIX1 .1 M.T
W
O W O W .C O
W
WW .100Y.C M.TW WW .100Y
SUB ,X IX F0 3
WW .100Y.C M.TW M.TW
PC ← (PC) + O W O
W–W
1; Push (PCL)
W
WW .100Y.C M.TW
O SP ←W (SP) 1; Push Y.C
00(PCH) .TW WW .100Y.C M.TW
. 1 M
W W .C O
W
SP ← (SP) –W
W– 1;1; Push (X) CO
Y . W W WW 00Y.CO .T
Y ← W 0
.10(CCR) O .T 83 W.1
W .100 M.T M
SP (SP) Push (A) 1
—M
SWI Software Interrupt
W W .C O SP ← (SP) –W 1; WPush
Y .C 1 — — —
W
INH
W W 0
0 Y.CO
Y W ←W 1010 .T 0
W
W .100 O M.T PCH ←SPInterrupt (SP) – 1; I .←
W High .C OM W W.1 Y.COM
.C W W
WW .100Y Y W .100
Vector Byte
M .TWPCL ← Interrupt W Vector Low
W .10Byte0
O M .T W
W O WW
W O W O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W W
50 WW .10Central 0Y.C Processor
M .TWUnit (CPU) W MOTOROLA
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M WW 00Y.CO .TW Opcode Map
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W .100 4-6.
WTable OM
.T
Instruction SetW Summary W.1 Y(Sheet .CO 6.Tof
M
W W W 0 Y .C
.T W W 0 0 W6)
.T . 1 0 M W .1 O M
Operand
Address
Y.C
Opcode
W
Cycles
0 T W
Mode
. 1 0 M .
W Y.CO Form W W WWOperation 0 Y .CO .TW W W
Description
0 0Y.C .T W
.10 0 M. T .1 0 M W. 1 OM H I N Z C
.1 TAX M Transfer Accumulator .to
W 1 IndexYRegister .CO .TW
M X ←W (A) O— — — — — INH 97 2
WW 00Y.CO .TW W W 0 0 WW .100Y.C M.TW
W.1 TST oprM .1 M WW 00Y.CO .TW DIR 3D dd 4
W Y .C
TSTA
O
W W WW 00Y.CO .TW W INH 4D 3
W
W .100TSTX OM.T Test Memory Byte W W .1 or ZeroOM
for Negative
. C (M) – $00
W W.1 Y.— C O—M — INH 5D
W 3
WW .10TST 0Y.C opr,X .T W W 0 0 Y .T W W . 1 0 0 M . T IX1 6D ff 5
W TST ,X OM
. C W W.1 Y.COM W W W
0 Y .C O
W IX 7D 4
WW .100Y .T W W 0 0 .T W .1 0 M .T
. 1 M A ← (X) WW CO
W TXA Y.COM Transfer Index RegisterW toW Accumulator.CO
Y W W 0—Y.— — — — WINH
.T
9F 2
WW .WAIT 1 0 0 M .T W W . 1 0 0 M .T
W . 1 0
O M
W O
O Stop CPU Clock and Enable WW .100Y.C M.TW
W Interrupts — 0 — — — INH 8F 2
WW .10A0Y.CAccumulator .T W WW .100Y.C M.TW
OM W O opr WOperand (one O
or two bytes)
W Y.C WW .100Y.C M.TW WW Program Y.C
00counter .TW
WW .CCCR 1 0 0 Carry/borrowW
M .T flag PC
W .1 O M
W O
0Y.Clow byte
Condition code register PCH Program counter high byte
W
WW dd.100YDirect .COaddress .T W
of operand WW .100Y.C M.TW PCL WWProgram . 1 0counter M.T
W
O M W O W . C O
W dd rr
WW DIR.100Direct
Direct address
Y.C addressing
of
.TW
operand
mode
and
WW .100Y.C M.TW
relative offset of branch instruction REL
rel
WW Relative addressing
Y
100 counter
Relative.program
mode
M .TWbyte
offset
W M
Olow bytes of offset in indexed, W O W
W program O
.C offset
WW16-bit.offset .C 00Ycounter M .TW
0Y C addressing TW
ee ff High.and
WW EXT .10Extended .T Wmode 1 0 0Yaddressing M .
rr WRelative . 1
byte
M W O SP Stack W
pointer
.C O
W COin indexed,
Y.byte WW .100Y.C M.TW X WWregister 00Y W
WWffH .1Offset 0 0 M .T W8-bit offset addressing
W O
Index
W .1 O M.T
Y.C
Half-carry flag O Z Zero flag
Whh WllW High Y.C
0and low bytes of
. W
Toperand address WinW 0Y.C M.TW #
extended0addressing WW value
Immediate . 100 M .TW
. 1 0 M W .1 O W O
W OR .100Y.C M.TW
WInterruptYmask O ∧ LogicalW
WW .100Y.C M.TW ∨
I AND
W ii W Immediate 0 .Coperand byte .T W Logical
.1 0 M W O
IMM W Immediate .CO .mode
addressing WW 00Y.CO .TW⊕ WW
Logical EXCLUSIVE
0Y.C M.TW
OR
WW Inherent 0 0 Y T W W .1 M .1 0
O
W.1 noYoffset
INH addressing mode ( ) Contents of
M
.COaddressing WW 00Y.CO .TW W WWcomplement) 0Y.C W
WIndexed, M.T
IX W mode –( ) Negation (two’s
W 0
08-bit offset addressing .T W .1 M . 1 0
IX1 Indexed,. 1 M mode W O ← Loaded with W C O
WW
W .CO .TW mode WW .100Y.C M.T? W If WW .100Y. .TW
IX2 Indexed, 16-bit
. 1 00Yoffset addressing
M W O W O M
WW flag00Y.CO .TW WW .100Y.C M.TW
M Memory location : Concatenated with
N WNegative WW .100Y.C M.TW Set or cleared
Any bitW. 1 OM W O
n
W Y . C W W WW 00Y.CO —.TWNot affected WW 1 0 0Y.C .TW
W .1 00 M .T W . 1 O M W . O M
W
WW .100Y.C M.TW
O
4.7 Opcode W Map W .C O
W 00 Y .T W .1 M
W.1 SeeYTable . C OM4-7. W W.1 Y.COM W WW 00Y.CO .TW
W W W 00 .T W .1
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
O W O W .C O
W
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W .100 O M .T W
W .100
W O WW
W O W O
W O Rev. 4.0 W O
W O W W
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
. W O
W W WW 00Y.CO .TW WW .100Y.C M.TW
M .T .1 M W O
Y.CO .TW W WW 00Y.CO .TW WW .100Y.C M.TW
0 0 .1 M
W 00 .T W .1 M
W.1 Y.COM W W.1 Y.COM W WW 00Y.CO .TW
Central Processor Unit (CPU)

52
Data Sheet W W W
W .100 M.T
W 00 M.T 4-7. Opcode Map W.1 Y.COM W
W .C O W W.1 Y.CO Table
W W
WW Bit Manipulation
.100
Y
M .TW W .100 M.T
W
Control W.
100 .T
OM Register/Memory
W O Branch
W W
Read-Modify-Write
.C O W Y .C W
WW DIR.100YDIR .C REL .TW DIR WINH INH00Y IX1 .TIXW INH WINH W.1IMM 00 DIRM.T EXT IX2 IX1 IX
M W .1 O M C O
W O C W . .TCW
4WW 0Y.6 A00Y B
MSB MSB
W0 1 .C
Y 2 W3 5 .7TW 8 W9 D E F
LSB W 0 0 .T .1 0 M .1 M LSB
W W.51 Y.5COM 3 W 5 3WW 3
Y .CO 6 5W 9
W WW 020Y.CO 3 .TW4 5 4 3
W NEGX 10 NEG 0 .T .1
.100 DIR 2 OM
0 WBRSET0 BSET0 BRA .T NEG
3 DIR 2
W REL 2 DIR 1
NEGA
INH 1 WINH . 2 IX1 O
C
NEG
1 M IX 1
RTI
INH W
SUB
2 W IMM 2
SUB
.CDIROM 3
SUB
EXT 3
SUB
IX2 2
SUB
IX1 1
SUB
IX
0
W .C W W Y . W W 0 Y T
. 4 W
1 W 5 Y5
.100DIR 2 BRN M.T
3 W
W .100 .T
OM 1 RTSINH
6
WIMM.120 CMP 3OM 5 4 3
1
3
BRCLR0
W
DIRW2
BCLR0
.C O REL W Y .C W W W
2
CMP
2 0 Y .C
DIR 3
CMP
T
EXT W 3
CMP
IX2 2
CMP
IX1 1
CMP
IX
Y W W 0 .T 0 .
W 5 .1005
BRSET1 W OM
3 .T 11 0
W.1 Y.COM W W W.21 SBCY.3COSBC M 4
W
5 4 3
2 W BSET1
. C
BHI MUL W W SBC
0 .T SBC SBC SBC 2
3 WDIR 2 .DIR 1 0 02Y REL M.TW1 INH W .1 00 M .T 2 IMM .210 DIR 3
W O MEXT 3 IX2 2 IX1 1 IX
5 W 5 BLS
BRCLR1 WBCLR1 Y .CO 3 5
COM W COMA
3
W W3 WCOM060Y.COM CO 5 SWI T W10 WCPX W 2 CPX 0 0Y3.C CPX M4 .TCPX W 5 CPX 4 CPX 3 3
3 W 0 0 .T COMX
1
INH 2 W. IX1 1 M . . 1
3 DIR 2
5 WW 5
.1 2 REL O
DIR
.C3
2 M DIR 1
5 W
INH 1
W 6 0Y.C 5
O
IX 1 INH
W
2
W
IMMW
W 2 DIR 3
03Y
.COEXT4 3 .TWIX25 2 IX1 1 IX
4 W BSET2 10BCC 0 Y .T 3 W 3
LSR.1 0 M .T 2
. 1 0 ANDO M 4 3
3
BRSET2
DIR 2 DIR. 2
W RELC 2 OM
LSR
DIR 1
LSRA
INH 1
LSRX
INH W2 W IX1 1
LSR
.CIXO 2
AND
W
IMM 2
W AND
DIR 3Y .C EXT 3
AND
W
IX2 2
AND
IX1 1
AND
IX
4
W Y . W W 0 0 Y .T W W 0 0
.1 3 BIT O .T
5W 5
.100 3 OM.T W.1 Y.COM W BIT WW
2 4 M 5 4 3
Central Processor Unit (CPU)
5 BRCLR2 BCLR2WBCS/BLO
W .C W W
BIT
0 Y .C BIT
.T W BIT BIT 5
3 DIR 2
W DIR 2 REL
0 Y .T W W .1 0 0 .T 2 IMM 2 DIR
. 103 EXT 3
M IX2 2 IX1 1 IX
W.BNE 10 3 OM M W 3 Y.C4 O
6 BRSET3
5
BSET3W
5
Y .C
ROR
5
RORA W
3
RORX W
3
WW6 ROR
ROR 0 Y
5
.CO .TW LDA WW
2
LDA 0 0
LDA
5
LDA .TWLDA
4
LDA
3
6
3 DIR 2 WDIR 2
. 1
REL 0
0 2 DIRM 1 .T INH 1 INH 2 IX1 1 .1 0 IX M 2 IMM 2 DIR. 3
W 1 EXT 3 OMIX2 2 IX1 1 IX
W O . C
5 5 W
WW BEQ.100YASR
3 .CO5 ASRA 3
TW ASRX W
3 W6 ASR005Y.C W2 WW 4
00Y5 STAM6.TW 5 4
MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0
7 BRCLR3 BCLR3
M . ASR .1 M .TTAX STA
W . 1STA O STA STA 7
3 DIR 2 DIR 2 WREL 2 DIRO
C 1 INH 1 INH 2 IX1 1W
W IX
. C O 1 INH 2 W DIR 3 EXT 3
Y .C IX2 2.TWIX1 1 IX
W . 3W Y W W 3 .10 4 0
8 BRSET4
5
BSET4
W5 BHCC .310ASL/LSL 0Y 5 ASLA/LSLA
O M.T ASLX/LSLX ASL/LSL WASL/LSL
3 W6
W .1050 .T 2
O1MCLCINH 2 EORIMM 2 EORW
2
WEOR Y.EOR C OM 5
EOR
4
EOR
3
8
DIR 2 WW . C W Y . C W W 0 0 .T W
3 DIR 2
W REL 2
0 0 YDIR 1 INH
.T 1 INH 2
W IX1 1 IX
1 0 0 . T DIR 3
. 1EXT 3 IX2
M
2 IX1 1 IX
5 5 3 .1 5
OM 3 ROLX 3 ROL 6 WROL W. 5 Y.COM 2 2 3 W 4
.CO5 ADC 4 3
9 BRCLR4 BCLR4 WW ROL Y.C
BHCS
DIR 2W REL 2 00DIR
ROLA
INH .1TW INH 2 W1 IX100
SEC
.T W ADC ADCWDIRW3 ADCEXT . 1 0 03 YADC TW ADC IX 9
IX2 2M. IX1 1
3 DIR 2
W.1DEC 5Y.C
1
OM3
IX1
W5.
1
M INH 2 IMM 2
W 4 Y.C5O
5 5
W 3
W
3 6
W W 0 Y .COCLI 2.TW 2
W 3W
00ORA .T4W ORA 3 A
A BRSET5 BSET5 WBPL
0 0 DECA
.T
DECX DEC DEC
.1 0 M ORA ORA ORA . 1 M
ORA
3 DIR 2 DIR 2 REL 2 .1 DIR 1
W W .CO .TW
INH M1 INH 2 IX1 1
WW 00Y.CO 2 .TW 2
IX 1 INH 2 IMM 2 DIR 3
W WW EXT 3
4 00Y 5
.C2O IX1
IX2
.
1
TW 3
IX
5 5
W 3
0 Y W .1
3
. 1 M 4
B BRCLR5 BCLR5 BMI
REL W
.10 OM WW 00Y OM ADDIMM 2 ADDDIR 3 ADD
SEI
1 .C INH 2 WEXT W 3 ADDIX2 Y.C
O ADD ADD
IX1 1 W IX
B
3 DIR 2 DIR 2
W Y . C W W .T W W 0 0 2
.T
3 .1
C
5 5 W3
WDIR.1500INCA 3OM .T 3 6
INC WW
5 .1 O2M
.CINH
2
W W JMP Y.C
4 OM3 JMP 2 C
W IX
BRSET6 BSET6 BMC
W W INC
0 Y .C INCX
T W
INC
W 0 0 Y RSP
.T W JMP
WJMP
1 0 0 JMP
1 .T
3 DIR 2 DIR 2 REL 2
.
1
1 0 INH 1
M
INH
. 2 IX1 1 IX
W . 1 1
O M 2 DIR 3 EXT 3
W . IX2 2
O M
IX1
5 5 3 W4 TSTAY.3COTSTX 3 W 5 4
Y.C BSR.TW JSR
2 6 5
WW JSR
6 7 .C 6 JSR .TWIX D
5
D BRCLR6 BCLR6 BMS
RELW
W TST
DIR 1.100 INH 1 .T TST TSTWW
.1 0 0NOP M
JSR
. 1 002Y JSRIX1 M
3 DIR 2 DIR 2 2
W OM INH 2 IX1 1 IX
W2 1 INH 2
O
Y.C LDX .T
REL 2 DIR 3 EXT 3 W
W4W LDX.1500YLDX
IX2
.CO4 1
.TW
E
5 5 3
WW .100Y.C M.TW WW STOP .100 M
2 W 3
M
3
E
BRSET7 BSET7 BIL
W O W C O LDX LDX
EXT 3W W C1
.IX1O LDX
IX W
3 DIR 2 DIR 2 REL
W . C 1 WINH
Y . 2 IMM 2
W DIR 3
W IX2 2
0 Y T
F
5 5 3 W 5 Y
.1003 CLRXO3M.CLR TW6 CLR 5 WWAIT 2 .1TXA
W
00 2
OM STX
.T 4 5 0
W.61 STXY.5COSTX M. 4 F
BRCLR7 BCLR7 BIH CLR W CLRA
W1 INH001 Y. INH 2 .TIX1 C W .C 2 TW
STX WSTX
IX2 2 00 IX1 1 .TW
3 DIR 2 DIR 2 REL 2
WDIR W1 IX 1 W INH 1
.1 0Y
0INH M . DIR 3 EXTW 3
. 1 M IX
REL = Relative W
. 1 O M W O W
W in Hexadecimal .C O
INH = Inherent
Y.C WW .100Y .CMSB .T 0W MSB ofW 00Y .TW
WWNo Offset 0 T W Opcode 1
MOTOROLA
IMM = Immediate IX = Indexed, 1 0 . LSB M W . O M

DIR = Direct IX1 = Indexed,W 8-BitW.Offset Y.COM W WW 00Y0.CO BRSET0 W5 Number of CyclesW
W 0 0Y.C M.TW
W 0 0 LSB .of T Opcode in HexadecimalW .1 M .T Opcode Mnemonic . 1
EXT = Extended IX2 = Indexed, 16-Bit Offset
W.1 OM W O3 DIR Number of Bytes/Addressing W Mode O
W W .C O
Y W
W
W .100 O M.T W .1
.C OM W W.1 Y.COM
C W W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100
W O W C O W
WW .100Y.C M.TW WW .100Y. .TW W
W OM
O
0 Y.C W
W . 1 0
O M.T
WW .100Y . C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW WW .100Y. C
0 0 Y.C .T W WW .100Y.C M.TWSectionW5. External . 1 00Y Interrupt M.T
W Module (IRQ)
. 1 M W O W .C O
. 1 M W O W O
W. 1 5.1 Introduction
OM WW 00Y.CO .TW
W 00 .T W.1 interrupt OM(IRQ) module provides .1 M
W W.1 Y.COM W The external
W Y .C W W WW asynchronous 0 Y .CO .external TW interrupts to
W . 1 00 M .T theWCPU.WThe . 100following M .T
sources can generate W . 10
external M
interrupts:
O
O
W
WW .100Y.C M.TW
O
WW 0 Y.C
0pin .TW WW .100Y.C M.TW
• IRQ/V . 1 M W O
W O WW PP00Y.CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW W .1 pins M
W W .C O
W
• PA0–PA3
Y W
W
W .10 0
O M.T W .1
. C OM W W.1 Y.COM W
C W W
0Y.
WW 5.2.10Features M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TWThe external WWinterrupt Y. .TW includesW .100
Y
M.T
W . 100 module O M (IRQ) these W features: C O
W O .C WW .100Y . .TW
WW .100Y.C M.TW • Dedicated WW external . 1 00Y interrupt M .TW M
W O pin (IRQ/V ) W O
WW .100Y.C M.TW
W O .C PP
WW .100Y.C M.TW• Selectable WW interrupt . 1 00Y on four M .T W
input/output (I/O) Wpins
W (PA0–PA3) O
W .C O WW 00Y.CO .TW W 0 Y.C W
W W
. 1 00 Y
M
W
.T • Programmable W
W . 1edge-onlyOor M edge- and level-interrupt W
0
.1 sensitivity O M.T
W
WW .100Y.C M.TW
O
W O W O
WW 00Y.CO .TW
5.3WOperation WW .100Y.C M.TW WW .100Y.C M.TW
W.1 OM W O
WW .100Y.C The .T W W .1 M O 0–3
W OM interrupt request/programming WW 0interrupts. .CO The
voltage pin (IRQ/VPPW ) and
W port YA.Cpins W
WW .100Y.C (PA0–PA3) M .T W provide W external .1 0 Y
M .T WPIRQ bit W
in the mask
W . 1 0 0
option O M.T
register
O W O C
Y. into .aTW
W
WW .100Y.C(MOR) Tenables
W PA0–PA3 WW as.1IRQ .C
00Y interrupt .Tsources,
W WWare combined
which
100
W single M .
O OR’ing function toWbe W latched C O M
by the IRQ latch. Figure W W .
5-1 shows OM
.Cthe
. C Y . W W 0 Y W
W W
.1 00Y structure M
Wthe IRQ module.
.Tof W
W . 100 O M .T W .10 O M.T
W O WW .100Y .C
W O W O
WW .100Y.C M.TW
After completing its current instruction, the CPU tests the IRQ latch. If the IRQ latch
W
WW .100isYset, .CO .TW WW 0 0Y .C .TWcode register
the CPU then tests the I bit
. 1 in the condition
M and the IRQE bit
W W in Y . C OM W
Wregister. Y COI bit isTclear
.the W W WW bit0is 0 .CO .TW
Yset,
W 00 the IRQ status
.T W and controlW 0 0 If . and the IRQE 1 theM
W.1 CPUY.then OMbegins the interruptWsequence. W.1 Y.C OMinterrupt is serviced
This Wby W.the .CO .TW
interrupt
Y
W C W W 0 .T W W 0 0
W 00
W.1service
.T
OM located at $07FA
routine Wand .10$07FB.
.C OM W W.1 Y.COM W
. C W W
W W
. 1 00Y M .TW W
W .100
Y
O M .T W
W .100 O M.T
WThe CPU O
.Cclears the Y.C the interrupt Wthat another Y.C
WW external 00Y interrupt WIRQ latchWwhile
.Trequest
W it fetches
. 1 00during M .T W vector,Wso . 100As OM.T
W
.1 M can be latched the interrupt service W
routine.
W .COI bit is.Tcleared WW
W .CO .TW
0Yfrom WcanW 00Y
.C W
WW soon . 1 0as0 Ythe
M
W during the
W
return
. 1 0
O interrupt,
M the CPU W . 1
recognize O M.T
W O request. Figure 5-3 Y.Csequence W by00an .C
WWthe new 0 Y.C
0interrupt .TW WW shows 1 00the M .TWof eventsW caused . 1
Y
M.TW
.1 M W . O W O
interrupt.
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W .100 O M .T W
W .100
W O WW
W O W O
W O Rev. 4.0 W O
W .C O W W
MOTOROLA WW .1External 00Y Interrupt M .TW Module (IRQ)W 53
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
External Interrupt Module W
.T(IRQ) WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W TO BIH & BIL
M .TW IRQ W W.100 O M .T W
W .100 O M.T INSTRUCTION
.C O W Y .C W W W 0 Y .C T W PROCESSING
00 Y .T W W 1 0 0 M T
. LEVEL-SENSITIVE TRIGGER . 1 0 M .
W . 1 O M W . O W W .C O
0 0 Y.C .T W WW .100Y.C M.TW (MOR LEVEL WBIT) . 1 00Y M.T
W
. 1 M W O W .C O
WW 00Y.CO .TW WW .100Y.C M.TWVDD WW .100YIRQF M.TW
. 1 M W O W O
WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y.C M.TWEXTERNAL
W W.1 Y.COM PA3 W WW 00Y.CO .TWD LATCH IRQ Q
W WW 00Y.CO .TW INTERRUPT
W 00 .TPA2 W . 1 M .1 M REQUEST
. 1 M W O W O
W
WW .100Y.C MPA1
O
TW
.PA0 WW .100Y.C M.TW
CK
WW .100Y.C M.TW
WW IRQE O
W . C O WW 00Y.CO .TWCLR W 0 Y.C W
W W
. 1 00 Y
M .T W W
W . 1 O M W .1 0
O M.T
W O PIRQ
.C WW .100Y. C
WW .100Y.C M.TW (MOR) W
W
1 00Y M .TW M .TW
W . O W O
W
WW .100Y.C M.TW
O
W O
W O
WW .100Y
W .CO WW .100Y.C M.TW
WW .100Y.C M.TW RESET M.T
W
W O
IRQW
O
W
WW .100Y.C M.TW
O
WW VECTOR FETCH
0 0 Y.C .T W WW .100Y.C M.TW
.1 M WW 00Y.CO .TW
W W Y .C O
W W WW IRQR 0 Y .CO .TW W
W 00 .T .10 1 M
W.1 Y.COM W Figure W W5-1. IRQ .C OM Block DiagramWW.
Module Y .CO .TW
W W 00 Y .T W W 0 0
W
.C W W 00 .T
WW .100Y M.T
W O W7 W .C O W
W Y.C Name.TW WBit .1006
Y 5 .TW 4 W .12 00 1 M.T Bit 0
W .100
Addr. Register M 3
W O M W O W W .C O
.C and Control W 00Y.C 0 .TW0 W 0 100Y 0 W
WW .10IRQ 0YStatus M .TW Read: W IRQE W.10 O M
IRQF
W . O M.T 0
$000A WW CO (ISCR) WW .100YIRQR .C
W .Register
00Y See page .T57.W
Write: WW .100Y.C M.TW R
M .TW
. 1 M 1 WW 0 O W O
W
WW .100Y.C M.TW
O Reset:
W 0 0Y.C M.TW
0 0 0
WW 0 .100Y0.C M.T0 W
.1 O
W W Y.C O
W W W=W Unimplemented
0 Y .CO .RTW = ReservedWWW 00Y.C .TW
W . 1 00 M .T . 1 0 M W . 1 O M
WW I/O O
W
WW .100Y.C Figure
O
.T W 5-2. IRQW Module 0
.C
0YRegister .T W
Summary WW .100Y.C M.TW
. 1 M
W W .C OM
W PP Pin 00 Y .T W .1 M
5.3.1 IRQ/V
W W 0 .T W .1
W
W .100An interrupt O M.Tsignal on the IRQ/V WPP .10pin latchesOM an external interrupt W Wrequest. .C OM
The
.C W Y .C W W 0 Y W
WW .10LEVEL 0Y bitMin.Tthe W mask option W register
W . 100 provides O M T
.negative edge-sensitive W .10triggering O M.T
W O C WWfor the 0Y. C
WW .1or00both Y.C negative .TWedge-sensitive WW and.10low 0Y.level-sensitive
M .TW triggering . 10interrupt M .TW
M W O W O
W function. O
W CO level-sensitive W O WW 0on .CO .TW
WW If edge- 0 0 Y.and . T W WW is.1selected,
triggering 0 0Y.C aMfalling . TW edge or W a low level . 1 0Ythe M
W W .1
IRQ/V PP pin
.C
M
Olatches an external W
interrupt
W .C
request.
Y
O Edge- and level-sensitive
W W W W
0 Y .CO .TW
W triggering Y
.100 allows M.the TWuse of multiple W .100 external .T
OM interrupt sources. .10 M
W W .C O W wired-OR
W Y .C W W W WAn
0 Y.CO .TW
Y W W 0 .T 0
W external .100interrupt
Wlow. OM
.T
request is latched as long 0 as any source
W.1 Y.COM W
is holding the IRQ/V
W W.1 PPY.COM W
.C W
W W
pin
. 1 00Y M .TW W
W . 100 O M .T W
W .100 O M.T
W O Y.C WW .100Y .C
WIfW level-sensitive .C
00Y triggering .TW is selected, WWthe IRQ/V 100 PP input
W
.Trequires an external .T
W . 1 O M W .
C O M W W .C OM
Y.C WWIf the.1IRQ/V . is W must be100 Y
WW to
resistor VDD for wired-OR
.10V0DD supply. M.T
W operation. 00Y PP pin M.T
not used, itW
W. OM
tied W to W the C O W W .C O W Y .C
. W Y W W 0 0
W
W .100
Y
O M.T
W
W .100 O M.T W W.1
W .C
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O W O
.TW WW .100Y.C — Rev. 4.0
W .C O W W
54 WW .1External 00Y Interrupt M .TW Module (IRQ)W MOTOROLA
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW External Interrupt Module (IRQ)
M WW 00Y.CO .TW Operation
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM FROM W W
M .TW W
W . 100 O M .T RESET W
W .100 O M.T
.CO .TW WW .100Y. C
. 1 M W O W O
W
0 Y.C
O
. 1 0 M W YES O W O
WW 00Y.CO .TW WW .100Y.C M I BIT.T W
SET? WW .100Y.C M.TW
.1 M W O W O
W W.1 Y.COM W WW 00Y.CO .TW
NO
W WW 00Y.CO .TW
W 00 .T W .1 M
W W 00 .T YES W
W
W .100 O M.T W.1 Y.EXTERNAL C OM W W.1IRQ LATCH. Y .C OM
W
.C W W W CLEAR 0
WW .100Y M .TW W
W . 100 INTERRUPT? O M .T W .10 O M.T
W O WW .100Y. C
W O W O
WW .100Y.C M.TW
NO
W O
W O W O
W
WW .100Y.C M.TW
O
WW .100TIMER Y.C .T W WW .100Y.C M.TW
W OM YES W O
W
WW .100Y.C M.TW
O
WW INTERRUPT? 0 0 Y.C .T W WW .100Y.C M.TW
.1 M WW 00Y.CO .TW
W W Y.C O
W W WW 00NO Y .CO .TW STACK PCL,WPCH,
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INSTRUCTION.
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WW .100Y.C M.TW
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WW .100EXECUTE Y.C INSTRUCTION..TW WW .100Y.C M.TW
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WW .100Y.C M.TW
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W O WW 00Y.CFlowchart WW .100Y.C M.TW
WW .100Y.C M.TW FigureW5-3. Interrupt .1 M .T W
W W .C O
00 Y
W If edge-sensitive-only W
.T triggering is selected, .1 M
W.1 Y.COM W W W.1 a Y falling
.C OMedge on the IRQ/VW
W
PPW pin
0Y .CO .TW
W W 0
W latches.10an
W
0 external
O M.T
interrupt request. W A subsequent
W .100 OpinM.T interrupt request
external
W W.1can Y.COM
be latched only .C after the voltage level W
on the IRQ/V Y .C returns
W to logic
W 1 and then 00 .T
WW .100Y M.T
W W .100 PP OM.T W.1 Y.COM
falls again
W to logic O 0. W .C W
W W .100
W O W C O W W .COM
TheW IRQ/VPP pin .C contains Wan internal W
Schmitt trigger Y . as part ofWits input to Wimprove 0Y
W
noise immunity.
W
Y
.100 TheOvoltage M.T on this pin can
W
W .100 the mode
affect O M.Tof operation andWW.10
Y.C . .TW W Y . C W W
WWnot exceed
should .100 VDD M
W .100 M.T
W O W C O
W O Rev. 4.0 W O
WW .100Y.C —M
W .C O W W
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
5.3.2 Optional External W W.1 Interrupts .C OM
W W
M .TW W
W . 100
Y
O M .T W
W .100 O M.T
.CO .TW .Cfor the .lower W .C
00Y WWThe .inputs 1 00Y M TW four bitsWof port A.1(PA0–PA3) 00Y M .TWbe connected to the IRQ
can
. 1 M pin Winput of COCPUTifWenabled by W O
W Y.C
O
W WW 0Y .the .
the PIRQ bit
WW .100where Y.C in the mask
TW
option register. This
.transitions
. 1 00 M .T capability. 1 0 allows keyboard
M scan applications
W O M
the or levels on the
WW 00Y.CO .TW WI/OWW pins1will 0 Y .CO the
behave T W same as W
the
W IRQ/V 0 0 Y
pin
.C
except .T W
for the inverted phase
W .1 O M W . 0 O M. W W .1PP
.C Opin M
W Y.C W (logic
WW .100Y 1, rising . C
edge). The
TW active stateW of the IRQ/V
00Y PP M.T is a W logic 0 (falling edge).
100 .T M . W . 1 O
W. OM W .CO .T W to function .C as IRQ W
WW .100Y.C M.TW WWPA0–PA3
The
. 1 00Ypins are M
W
selected as aW group . 1 00Y M.T interrupts and are
W O W O
W O enabled
WW by.1the .C bit in
IRQE the IRQ statusWand control Y.Cregister. .TTheW PA0–PA3 pins
WW .100Y.C M.TW can be 00Y
positive-edge M .TW only orW
triggered W
positive-edge . 100 andOhigh-level M
W W Y .C O
W W WW 00Y.CO .TW W W 0 0 Y.C .T W triggered.
W 00 .T 1
W.level-sensitive OM triggering is selected, .1 OM or a high level on a
W W.1 Y.COM W If edge-W and
0 Y . C W W WW a 0rising 0 Y .Cedge .TW
W 00 .T W . 1 0 M .T . 1 Edge- and M
. 1 M PA0–PA3 pin latches an external interrupt request.W O level-sensitive
W W Y .C O
W W
W
Wallows 0 Y .CO .TW W W 0 0 .C
Yinterrupt .TW
W . 1 0 0 M .T triggering . 1 0the use of
M multiple wired-OR external
W . 1 O Msources. As long
W CO W W .C O W Y .C W
WW .100Y. W as any source W is holding
00Y a PA0–PA3 W pin high, W an external .100 interrupt .Trequest is
W O M.T latched, andWthe W .1CPU O
continuesM.T to execute theW W
interrupt .C
service OMroutine.
Y. C Y W
WW .100Y.C M.TW W . 100 M .TW W
W .100 O M.T
W O W O W edge00on .C
WW .100Y.C M.TW If edge-sensitive WW only Y.C
00triggering is
.Tselected,
W aW rising
. 1
Y a PA0–PA3
M .TW pin
. 1
W interrupt O M W O
W O latches an external
Y.C request. A subsequent
WWexternal .C
Yinterrupt request can
.TW to logic
WW .100Y.C M.Tbe Wlatched only WWafter .the 1 00voltage M
level.TW of the previous .
interrupt 100 signalOreturns M
W O W
W
WW .100Y.C M.0TW
O
and then rises WWagain.1to Y.C 1. .TW
00logic WW .100Y.C M.TW
W O W O M WW 00Y.CO .TW
WW .10NOTE: 0Y.C MThe .TWBIH and BIL WW 0 Y.C . T Wto the level Won
W O
instructions 0
W.1 Y.COM W apply only
W W.1IRQ/VYPP
the
.C OpinMitself and
W
.C W W 0
WW .100Y not.Tto
M
Wthe outputWof the logic
W . 100 OR function O M .T with the PA0–PA3 W .pins.
10 TheOstate M.Tof the
W Oindividual port A pins W C
. A pins
WW .100Y.C M.TW
can be checked by reading theW appropriate port
Y .TasW
WW .100Y.C inputs. M .TW W .100 O M
W O
W
WW .100Y.C M.TW
O
W O
Enabled PA0–PA3 pins W CO interrupt WofWwhether .C O pins
W Y .C W W Wcause 0
anY.IRQ
0 .T W regardless W 1 0 0Y these
.TW
W . 1 00 are configured
M .T as inputs or
W . 1
outputs. O M W . O M
W
WW .100Y.C M.TW
O
W W The
.C OIRQ pin has an internal WWSchmitt Y CO The
.trigger. W optional external W WW interrupts 0 Y.CO .TW
Y W W 0 M. T 0
W 00
W.1 (PA0–PA3)
.T
OM do not have internal
0
W.1Schmitt .C Otriggers.
W W.1 Y.COM W
.C W W
W W
. 1
Y
00The M .TW W
W .
Y
100 code O M .T W
W .100 O M.T
W interrupt
O mask bit (I) in the condition
Y.C register (CCR) disables
W all C
maskable
Y . W
WW .10interrupt 0Y.C requests, .TW including WW external . 100interrupt M .TW
requests.
W .100 M.T
M W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100
W O W C O W W .COM
.C W Y . W W 0Y
WW .100Y M.T
W W .100 M.T W.1
0
W O W W .C O W
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O W O
.TW WW .100Y.C — Rev. 4.0
W .C O W W
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW External Interrupt Module (IRQ)
M WW 00Y.CO .TW IRQ Status and Control Register
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
5.4 IRQ Status and
W .100
WControl OM
Register
.T
W W.1 Y.COM W
W .C W
M .TW W
W . 100
Y
O M .T W
W .100 O M.T
.CO .TW .C and WW(ISCR) Y. C
00Y WWThe .IRQ 1 00Ystatus M .TW control register
. 100controls M
and.TWmonitors operation of the
W . 1 O M IRQ W module. C O
All unused bits in the ISCR
W W read as.C O
logic 0s. The IRQF bit is cleared
00 Y.C .T W WW 1 0 0Y. bitM .TWby reset. W . 1 00Y M .TW
. 1 M and W .
the IRQE O is set W O
.1 M W O
WW 00Y.CO .TW
W
WWAddress: 0 Y .CO .TW
$000A WW .100Y.C M.TW
.1 0 M
W W.1 Y.COM W WW 00Bit Y .7CO .6TW 5
W W4W 00Y3.CO .2TW 1 Bit 0
W 00 .T W . 1 M . 1 M
W.1 OM W O 0 0W IRQF O 0
WW .100Y.C M.TW
Read: 0 0 0
WW .100Y.C M.TW WW 0 0
IRQEY.C .T W
Write: .1 M R W O IRQR
W W Y .C O
W 00 .T Reset: .1 1
O0M 0 0 .1 0 M
0 0 0
W W.1 Y.COM W W W Y . C W W WW 00Y.CO .TW
W 00 .T W 0 0 = .T
Unimplemented R = .1
Reserved M
W W
W
W .100 O M.T
W
W .100 5-4.
Figure
OM
IRQ.T Status and Control
W
Register (ISCR)
W.1 Y.COM W
C W .C W
WW .100Y. W
M.T IRQR — Interrupt
W 0Y
.10Request M.T Bit
W
W .100 OM
.T
W O W C O Reset W .C W
WW .100Y.C M.TW This write-only WW .1bit Y.
00clears .T W W Y
.100 flag. OM.T
O W O M
the external interrupt request W .C
W
WW .100Y.C M.TW WW external
1 = Clears .C
00Y interrupt .TandW IRQF bit WW .100Y M .TW
. 1 O M W O
W O WW on0external 0Y.C interrupt WWbit .100Y.C M.TW
WW .100Y.C M.TW
0 = NoWeffect
. 1 M .TW and IRQF
W W .C O IRQFW — External WW Interrupt Y .CO .TFlag
Request W W WW 00Y.CO .TW
Y W 0
W 00
W.1 Y.COM The
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0
W.1 request C OM flag is a clearable, W W.1 bit
read-only OMis set when
.Cthat
W W 00 W
.Tan externalW
W
interrupt 1 00
request
Y .
is .T
pending.
M
W
Reset
Wclears .
the
0 Y
10IRQF bit. M .TW
. 1 M W . O W O
W O
WW .100Y.C M.TW1 = External WW interrupt Y.C pending
00request .TW WW .100Y.C M.TW
. 1 M W O
W O 0 = No external W
WW interrupt .CO .pending
Yrequest WW .100Y.C M.TW
WW .100Y.C M.TW .1 0 0 M T W
W OIRQE — External Interrupt WW Request .COEnable Bit WW 00Y.CO .TW
WW .100Y.C M T W
. read/write bit enables W 0 0 Y
.1 external .T W W .1 IRQE bit. M
W C O This
W W .C OM interrupts. Reset sets W W the
Y .CO .TW
W Y . W W 0 Y .T W W 0 0
W 00
W.1 Y.COM0 = External
1.T= External interrupt requests 0
W.1 Y.Cenabled OM W W.1 Y.COM W
W W
W W
.1 00 M .TW interrupt
W
W
requests
. 100 disabled
O M .T W
W .100 O M.T
W O W .C
WW .100YThe .C STOP .TandW WAIT instructions WW .10set 0Y.C the IRQE M .TW bit so that an Wexternal . 0Y
10interrupt M
can.TW
O M W O W .C O
W
WW .100bring Y.C the MCU .T Wout of these WW low-power 0
C
0Y.modes. TW
In
. addition, reset WWsets .the 1 00IYbit which M .TW
Minterrupt sources.WW . 1 M W O
W masksOall .CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW W . 1 00Y M W O
W O
W
WW .100Y.C M.TW
O
W W .C O
Y W
W
W .100 O M.T W .1
.C OM W W.1 Y.COM W
C W W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
O W O W .C O
W
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W .100 OM .T W
W .100
W O WW
W O W O
W O Rev. 4.0 W O
W .C O W W
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y . C W
W O M.T
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
5.5 Timing W W.1 Y.COM W W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW WW t .100Y. C
. 1 M W O W O
WW .100Y.C M.TW
ILIL
W O
0 0 Y.C .T W WW IRQ/V . 1 00YPIN.C M.TWtILIH
. 1 M W PP O W O
.1
WW 00Y.CO .TW
M W O WW 00Y.CO .TW
WW .1IRQ 01Y.C M.TW tILIHW
W .1 O M 0
W . Y.CO W W.1 Y.COM W
.C W W W 00 .T
WW .100Y M.T
W W .1. 00
.
M.T W.1 Y.COM W
W O W .C O W
WW .100Y.C M.TW WW IRQ.1n 00Y M.T
W W .100 M.T
W O W O W W .C O
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
IRQ (INTERNAL) WW .100Y. M .TW
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C Figure TW ExternalWInterrupt
.5-5.
W
. 1 0Y.C M.TW
0Timing
W O M W O
W
WW .100Y.C M.TW
O
W O W 5-1. External O W
WW (V.DD .COVdc).(1)
WW .100Y.C M.TW
Table Interrupt Timing = 5.0 W
WW .100Y.C M.TW 1 00Y MT
O W O W .C O
W
WW .100Y.C M.TW WW Characteristic
00Y
.C .TW Symbol WW Min . 100
Y Max.TW Unit
M
. 1
WWidth Low O M W O
W W .C O IRQ Interrupt Pulse W Y .C W t W W 0 Y .C — .TW t (2)
Y W W 0 .T 1.5 0
W .100 M.T (Edge-Triggered) WW.10 W.1 Y.COM W
ILIH cyc
W C O .C OM W
WW .100Y . W Interrupt Pulse W Width.100Y W W 00 .T
W OM.T(Edge- and Level-Triggered)
IRQ
W O M.T tILIH
W W.1 YNote
1.5 .C O(3)M tcyc
W .C W W Y .C W W 0 0 .T W
W
W .100
Y
O
T
M.PA0–PA3
W
Interrupt Pulse .100 High OM.T
WWidth W W.1 Y.COM W
.C W .C W
WW .100Y Y W .100 M.T cyc
t 1.5 — t
M .TW
(Edge-Triggered) W
W . 100 O M .T ILIL W C O
W
WW .100Y.C PA0–PA3
O
.TW Interrupt Pulse WW Width .C
00Y (Edge-M.TWtILIH
High WW .100Y. (3) M.T W
M . 1 1.5 W Note O tcyc
W Oand Level-Triggered) WW .CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW W .1 00Y M
W W .C O1. VDD = 5.0 Vdc ± 10%, W VSSW = 0 Vdc, T.AC=O–40°C to + 85°C, unless W
Y W W
W noted.
otherwise
0 Y .CO .TW
Y W W 0 M. T 0
W 00
W.1 Y.C3.OThe M T1/fOP; fOP = fOSC/2.WW.10
2. tcyc.=
.C Othe W W.1 Y.COM W
W minimum
.T. W
t should not be less Y than numberW of interruptW service
.100
routine cycles plus
M.T
W .1 00 19M tcyc
ILIL W
W . 100 O M .T W C O
W O WW .1(1)00Y .
WW .100Y.C M.TWTable 5-2.W
W
. 1 0Y.C M.TW
0Interrupt M .TW
External W O Timing (V = 3.3 W
Vdc) O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
DD
WW .100Y.C M.TW
W .C O Characteristic
WW 00Y.CSymbol O
W
Min
W WMaxW
0 CO
Y.Unit W
W W
.1
Y
00IRQ Interrupt M .T W
Pulse Width Low
W
W . 1 O M .T
W .1 0
O M.T
W O WW— .100Y .C(2)
WW .100Y.C ILIHM.TW
t
0Y.C M.TW
WW .10(Edge-Triggered)
1.5 tcyc
M .TW
W O W .C O
W
WW .1IRQ 0 .CO Pulse
Interrupt
Y .T W Width WW .100Y.CtILIH M.TW1.5 W W(3)
. 1 00tY M.T
W
0
(Edge- and M
Level-Triggered) W O Note W cyc
CO
W
WW PA0–PA3 .CO .TW WW .100Y.C M.TW WW .100Y. .TW
.1 00Y Interrupt M Pulse Width High
W t .CO W tcyc Y.C O M
W O 1.5 — W W
WW (Edge-Triggered)
0 0 Y.C .T W WW .100YILIL M .TW W . 1 00 M.T
. 1 M W O W .C O
WPA0–PA3 Interrupt
WW and .Level-Triggered).CO Pulse .TW
Width High (Edge-
WW .10t0ILIH Y.C TW NoteW
W t 00Y .TW
1 00Y M W O M .1.5 (3)
W . 1
cyc
O M
W
WW1. VDD.1=003.3 Y.VdcCO
.TW WW .1to .C
00+Y85°C, unless .TW WW .100Y.C M.TW
±M M
2. tW
W = 1/fOP ;.fC
10%,
O= f /2. VSS = 0 Vdc, TA = –40°C
W WW 00Y.CO .TW
otherwise noted.
W WW 00Y.CO .T
Y W .1
W 100 .T M
cyc OP OSC
3. The W.minimum OM
tILIL should not be less thanW the .1
Wnumber of.C OM service routine cycles
interrupt WW plus .CO
W . C W Y W W 0 0 Y
W 19 tcyc..100Y M.T
W 00 .T W.1 Y.COM
W . C O W W.1 Y.COM W W
WW .100Y M .TW W
W .100 O M .T W
W .100
W O WW
W O W O
W O W O
.TW WW .100Y.C — Rev. 4.0
W .C O W W
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW WW .100Y. C
. 1 O M W O W .C O
W
0 Y.C .T W WW .100Y.C M.TW WW Section . 1 00Y 6. TW
M.Low-Power Modes
. 1 0 M W O W .C O
W C O W .C W W Y W
W Y. W W .100
Y
M.T
W 00 .T
W .C .TW
. 1 O M W O W .C O
W
W
W O W O
W O The MCU can enter the following low-power
WW .100Y.C M.TW WW standby Y.Cmodes:.TW
WW .100Y.C M.TW W . 100 OM
W C O • W W mode
Stop .—
C OThe STOP instruction W puts the Y .C
MCU in itsTlowest
W
WW .100Y . .T W 0 0
W power-consumption Y . W
Tmode. W .1 0 0 M.
M W . 1 O M W C O
W
WW .100Y.C M.TW
O W
WWait .C
00Y— TheM .TW instruction WW .100Y. M .TW
• mode. 1 WAIT puts W the MCU inO an intermediate
W .C O WW 00Y.CO mode. W W W 0 Y.C W
W W
. 1 0 0 Y
M .T W W
power-consumption
W . 1 O M .T
W . 1 0
O M.T
W O .C W Y. C
WW .100Y.C M.TW • Halt WWmode.1— 00Y Halt mode M .TisWidentical to Wwait mode,
.100 except M .TW
that an oscillator
W O W delay C O 1 to 4064 internal clock W W .C O
W .C W
stabilization Y . of W W cycles 0Y occurs when
T W the MCU
W . 1 00Y M .TW W
W . 100 TheO M .T W .10 O M.
W O exits halt mode.
Y.C stop-to-wait conversion
WW .100Y bit, SWAIT, .C in the
Tmask
W option
WW .100Y.C M.TW WW enables 1 0 0 .T W M .
register, W. halt OM
mode. W O
W
WW .100Y.C M.TW Enabling
O
WWhalt .mode 0 0 Y.C .T W WW .100Y.C M.TW
W .C O WfromW 1 Yprevents OM the computer operating
.Cinadvertently W WW 00Y.CO .TW
properly (COP)
W Y W watchdog W being0 . T turned Woff by a STOP instruction.
W
W .100 O M.T W .10
. C O M W W.1 Y.COM W
WW .100Y.C M.T•W Data-retention WW mode Y
.100 — InOdata-retention
M.T
W W the.MCU
mode, 100 retains M.RAM T
W O W W W .C O
WW .100Y.C M.TW
contents W and WCPU register Y.C contents .TW at VDD voltages W as 0low Y
1 0 as 2.0 M.T
Vdc. WThe
data-retention W .
feature 100 allows O Mthe MCU to remain in Wa
.low
C O
W O
WW .1state .C WW Y. .TW
WW .100Y.C M.TW power-consumption 00Y during M TW it retains
.which data,W .100the CPU
but O M cannot
W O
W
WW .100Y.C M.Texecute
O
W WW .100Y.C M.TW
instructions. WW .100Y.C M.TW
W W .C O
Y W
W
6.2 Exiting .100 andOWait
WStop M.T Modes W.1 Y.COM W W W.1 Y.COM W
.C W
W W
.1 00Y M .TW W
W . 100 O M .T W
W .100 O M.T
W O .C WW .C
WW .100YThe .C following.TWevents bring WWthe MCU 1 00Yout of stop M
W and load
.Tmode the program
.
Y
100 counter M .TW
M W . O W O
W
WW .100Y.C M.TW
with theO reset vector or with
WWan interrupt 00Y
.C vector: .TW WW .100Y.C M.TW
. 1 M
W W Exiting .C OStop Mode
W 00 Y .T W .1 M
W.1 •Y.CExternal OM reset — A logic W.1 Y.COM W WW CO
.CPU
W W 00 .T W W W 0 on the
1 00 RESET
M
pin.T resets the W
MCU, starts
. 1 0 0
theY
M .TW
. 1 M W . O W O
W
WW .100Y.and CO and
clock,
.T W loads the program
WW .counter 0 0Y.C withMthe .TW contents ofWlocations W
. 1 0Y.C M.TW
0$07FE
M
$07FF. W 1 O W O
W
WW .1•00YExternal .CO .TW WW .100Y.C M.TW WW .100Y.C M.TW
OMinterrupt — A high-to-low transition on the IRQ/VPP pin WW or a O
W Y.C WW 00Y.CO .TW W 0 Y.C W
WW .100low-to-high M .T W
transition on W an enabled
W . 1 port A
O external
M interrupt pin starts
W . 1 0 the O M.T
W O .C WW .C
WW .10CPU 0Y.CclockMand .TWloads theW
W
program
1 00Y with
counter
M TWcontents of
.the locations . 100
Y
M.TW
W . O W O
W $07FA and
WW .100Y.C M.TW
O $07FB.
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W .100 O M .T W
W .100
W O WW
W O W O
W O Rev. 4.0 W O
W O W
MOTOROLA WW .100Y.C Low-Power .TW Modes WW 59
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
Low-Power Modes .TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W
W .100 WaitOMode
Exiting M.T W W.1 Y.COM W
W .C W
M .TW W
W .
Y
100External O M .T W
W .100 O M.T
O • reset — A logic 0 on
WW .100Y. the RESET C pin resets
TWthe MCU, starts the CPU
0 0 Y.C .T W WW .10clock, 0Y.C and .T W
Mloads the programWcounter with M .
the contents of locations $07FE
W.1 Y.COM W W O
WW and Y .CO .TW W 0 Y.C W
. 1 0 0 M .T W
W . 1 0 0 $07FF.
O M W . 1 0
O M.T
WW 00Y.CO .TW .C WW transition .C
Y on the W
WW• .External 1 00Y interrupt M .TW— A high-to-low . 100 M .TIRQ/V PP pin or a
.C WW low-to-high . transition
.TW on an enabled port Y W
A external.Tinterrupt pin starts the
W
. 100Y M .TW W .
CPU
Y
100clock O and M loads the
W
program W .100 withOthe
counter M contents of locations
W .C O W .C W W Y .C W
WW .100Y M .TW W $07FA
W .
Y
100 and $07FB. O M .T W
W .100 O M.T
W O .C WWof the.1COP .C .TWresets the MCU,
WW .100Y.C M.TW W W
• COP . 1 00Y
watchdog M .TW— A timeout
reset 00Y watchdog M
W O
W O
WW
W .COclock, WWprogram 00Y
.C .TWthe contents of
WW .100Y.C M.TW starts 1the
. 00Y CPU
M .TW and loads the
W .1 counterM
O
with
O W O C
Y. timer interrupts
W
WW .100Y.C M.TW Wlocations
W $07FE
00Y
.C and .$07FF. TW Software WWcan enable . 100the COP M .TW so that the
MCU W . 1
periodically O M
can exit wait mode to W
reset O watchdog.
W
WW .100Y.C M.TW
O
• TimerW interrupt .— COReal-time interrupt requests W and O overflow interrupt
timer
W
WW .100Y.C M.TW
O
WW .start
requests 00Ythe MCU .T W and load
clock WW the .1 0
program 0Y.Ccounter M
W
.Twith the
W 1 O M W O
W W .C O contents W of Y
locations .C $07F8 W and $07F9. W W 0Y .C .T W
Y W W .100 .T 0
W
C W W
WW .100Y. W
M.T and Wait Modes
W .100
Y
M.T
W 00
W.1 Y.COM W
.T
6.3 W Effects O
of Stop W .C O W
O W O W .C O
W
WW .100Y.C M.The TW STOP and WW WAIT instructions Y.C .TWthe following
have WWeffects Y
.100on MCU .TW
modules.
W . 100 O M W O M
W WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y.C M.TW
6.3.1 Clock
W
. 1
W Generation
.C OM
W 00 Y .T W .1 M
W.1 Y.COM EffectsWof STOP and WWAIT W.1 onYclock M
.CO generation W are discussedWW here. 0 Y .CO .TW
W W 0 0 .T W .1 0
6.3.1.1W STOP.100
W O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M .TW instruction W Y
.100the internal M.Toscillator, stopping
W
W
0
.10CPU .T
OM and
W The
C O STOP W W
disables .C O W the Y .Cclock W
WW .100Y.all .TW clocks. W W.100Y OM.TW
peripheral
M
W
W .100
C O M.T
W O WW .100Y .
WW .100YAfter .C .TWstop mode, WW .100Y.C M.TW M .TW
M
exiting the CPU
W clock O
and all enabled peripheral W clocks O
begin
W
WW .100running
O
Y.C after .T W WW 0 0Y.Cdelay. .TW WW .100Y.C M.TW
the oscillator 1
stabilization
. M
W W .C OM
W 00 Y .T W .1 the MCU .1 internal M
NOTE: W.1 TheYoscillator
C OM stabilization delay W Wholds .C OM in reset for the first WW 4064
Y .CO .TW
W . W W 00 Y .T W W .1 0 0
W 00 cycles. .T
clock
W.1 Y.COM W M
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
6.3.1.2 WAIT C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW The.1WAIT .C .TW disables W
WCPU clock. Y. .TW W .100
Y
M.T
00Y instruction M
the
W . 100 O M W .C O
W
WWAfter.1exiting .CO .TW the CPUWclock W 00all Y.C W WW .100Y .TW
00Y waitMmode, W and
. 1 enabled
O M .Tperipheral clocks W O M
WW
W
immediately 0 Y.C
O running.
begin .T W WW .100Y.C M.TW WW .100Y.C M.TW
0
W W. 1
.C OM
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W .100 O M .T W
W .100
W O WW
W O W O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W
60 WW .100Y.C Low-Power .TW Modes WW MOTOROLA
W O M
W Y . C W
W 00 .T
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW Low-Power Modes
M W O Effects of Stop and Wait Modes
0 Y .CO .TW W W 0 0 Y.C .T W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
6.3.2 CPU W W.1 Y.COM W W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW C
of .STOP WW Y. C W
00Y WWEffects . 1 00Y M
and
.TWWAIT on the CPU are
. 100 discussed M .There.
. 1 M W O W O
W
0
O
Y.C6.3.2.1.TW WW .100Y.C M.TW WW .100Y.C M.TW
. 1 0 M STOP W O W O
.1 M The W O W O
WW 00Y.CO .TW STOP instruction:
W.1 Y.COM W W condition O
W W
•WW Clears Y
0
the.CO interruptW
.T
mask (I bit) W in
Wthe 0 0 Y.C code.Tregister, W enabling
W 00 .T . 1 0
external interrupts M . 1 O M
W.1 OM WW 00Y.CO .TW
W
WW .100Y.C M.TW
WW .100Y.C M.TW W .1 the CPU M clock
W W .C O
W
• Disables
W 00 Y .T W 1 mode, .1 M
W.1 Y.COM W After exiting W.stop C OM the CPU clock begins WWrunning CO theToscillator
.after
W W 00 .T W W
1 0 0 Y .
M .T W W . 1 0 0 Y
M . W
. 1 M stabilization W .
delay. O W O
W
WW .100Y.C M.TW
O
W O After exit from Wstop modeOby external interrupt,Wthe W I bit remains .CO clear.
WW .100Y.C M.TW WW .100Y.C M.TW W .1 00Y M .TW
W O
W O WW .CO reset, W
.TWthe I bit isWset. W.100Y OM.TW
.C
WW .100Y.C M.TWAfter exitW from stop mode
. 1 00Y by M
W Y.C
O WW 00Y.CO .TW WW .100Y.C M.TW
WW 0 0 .T W W 1
W.1 WAIT OM
6.3.2.2 W. OM W O
W W .C O The WAIT instruction:
Y W
W 00 .T
W.1 Y.COM •W Clears theW W.1 mask
interrupt C O(IMbit) in the condition W.1 register,
Wcode
M
.CO enabling
W W 00 .T interrupts W 1 00 Y .
M .T W W . 10 0Y
M .TW
. 1 M . W O
WW .100Y.C M.T W W . 1 M W O
W O • Disables the W CPU
W clockY.CO
WW .100Y.C M.TW
WW .100Y.C M.TW W 0 0
1 interrupt, .T W
W.by OMthe I bit remains clear. W O
W
WW .100Y.C M.TW
OAfter exit from wait mode
W W .C O exit from wait mode
After W WWby reset, Y
O I bit is set.
.Cthe W W WW 00Y.CO .TW
W 00 Y .T W 0 0 . T .1 M
W W
6.3.3 COP W Watchdog
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M .TW W 100
.the
Y
M.T are discussed
W
W .100 OM
.T
W Effects O of STOP and WAIT W
on COP C O
watchdog W here. .C
WW .100Y.C M.TW WW .100Y .
M .TW W . 100
Y
M .TW
W O W O
6.3.3.1 STOP
W
WW .100Y.C M.TW
O
W O
W .CO .TW WW 00Y.CO .TW WW .100Y.C M.TW
WW .1The 0 Y
0 STOPM W .1 M
W W .C O instruction:
Y W
W
W .10•0 Clears O Mthe .T COP watchdog counter W .1
.C OM W W.1 Y.COM W
C W W
WW .100Y. M.the TW W .100
Y
M.T
W
W .100 OM
.T
W • Disables O COP watchdog W
clock C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
Wprevent O STOP instruction from W O W W .C O
NOTE: WTo
W stop-to-wait .Cthe
00Y conversion .TW bit (SWAIT) WW disabling . 1 0Y.Cthe M
0mask
COPW watchdog,W
.Tregister to logic
program
.
theY
100 M .TW
.1 M in W the option
O 1. W O
W
WW .100Y.C M.TW
O
After
W Wexit from .C O mode by externalW
stop
W
W
interrupt, Y .CO
the COP watchdog W counter
W WW 00Y.CO .T
Wimmediately 00 Y .T W 0
.10continues .T .1 M
W.1 begins C OMcounting from $0000 W W and
.C OMcounting throughout WW the
Y .CO
W . W 00 Y W W 0 0
W
oscillator 00Y
.1stabilization .T
Mdelay.
W
W.1 Y.COM W
.T W.1 Y.COM
W .C O W W W 0
NOTE: WW .10after
Immediately 0Y exiting M
W mode by
.Tstop W external . 0
10interrupt, M .T
service the COP to W.10
W O
W
WWa full.1COP .CO .Tperiod. W WW .100Y.C M.TW WW
ensure 00Y timeout M W O
W O
W O Rev. 4.0 W O
W O W
W O M
W Y.C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W
W .100exit from
After
.T
OMstop mode by reset: W W.1 Y.COM W
W .C W
M .TW W
W .
Y
100The COP O M .T W
W .100 O M.T
O • watchdog counter immediately
WW .100Y. C begins counting from $0000.
0 0 Y.C .T W WW .100Y.C M.TW M .TW
W.1 Y.COM W CO watchdog is W O end of the oscillator
WW• The Y .COP W counter W
W cleared Y
0 at.Cthe W
. 1 0 0 M .T W
W . 0 0
1stabilizationO M .T
delay and begins counting W . 1 0 from O M.T again.
$0000
WW 00Y.CO .TW WW .100Y .C
. 1 M W O W O
WW 00Y6.3.3.2 .CO WAIT .T W WW .100Y.C M.TW WW .100Y.C M.TW
W W. 1
.C OM
W 00 Y .T W
The WAIT.1instruction 0 0 has no effect on the COP .1 watchdog. M
W.1 Y.COM W W W .C OM WW 00Y.CO .TW
W Y
00 timeout W W
W .100 T
M.NOTE: ToW prevent W.1a COP
.T
OM during wait mode, W .1 wait mode
exit C OMperiodically to service
W . C O W Y . C W W W 0 Y . W
WW .100Y M .TW the W COP. .100
W O M .T W .10 O M.T
W O WW .100Y. C
W O W O
W6.3.4 Timer
WW .100Y.C M.TW
O
WW 00here. O
W O of W W andYWAIT .CO on.Tthe Y.C .TW
WW .100Y.C M.TW Effects W STOP
. 1 0 0 M
W timer areW discussed
W .1 O M
W O
W
WW6.3.4.1 0 Y.C
O
0
W
1
W. STOP .C OM
Y W
W 00
W.1 Y.COM The
.T
STOP instruction: W.1 Y.COM W W W.1 Y.COM W
W
W W
. 1 00 M .TW W
W . 100 O M .T W
W .100 O M.T
W O • Clears the Y.C RTIF, and TOF bitsW .C
WW .100Y.C M.TW register, WWRTIE, .
TOFE,
100timer interrupt M .TWrequests W
in the timer Y status and
.100 anyOpending M.T timer
Wcontrol
disabling
W O and W
removing
W O
WW .100Y.C M.TW interruptWrequests
W 00Y
.1 M
W W .C O
W 00 Y .T W
• Disables the clock.1to the timer M .1 M
W
W 00
W.1 Y.CO M.Texiting stop mode
After Wby.1external
.C
M
Ointerrupt, the timer immediately
W W.1 Yresumes .CO .TW
M
W W W Y W W 0
W .100 M.T from the last W
counting W value.1before
W
00 theM
O
.T instruction andWcontinues
STOP .10 counting
O M
W O C W .C
W W 00 Y.Cthroughout
.T W the oscillator
W stabilization
1 0 0 Y . delay.
M .T W W . 1 0 0Y
M .TW
. 1 M . O W O
W CO exiting WW C
0Y.after W WW .1delay, .C
00Y the timer W
WW .100Y.After M .T Wstop mode Wby reset . 1 0and the
M .Toscillator stabilization
W O M.T
O W O .C
W
WW .100Yresumes .C operation from
.TW WitsW reset0state. 0Y.C M.TW WW .100Y M .TW
M W . 1 O W O
W
WW .100Y.C M.TW
O
6.3.4.2 WAIT
W W .C O
W 00 Y .T W .1 M
W.1 TheYWAIT .C OMinstruction has no W W.1 on the
effect Y . C OM
timer. W WW 00Y.CO .TW
W W W 00 .T W .1
6.3.5 EPROM/OTPROM W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
Y. C W . C W
WW Effects .100 of STOP
W W
M.Tand WAIT on theWEPROM/OTPROM W .100
Y
O M.T are discussed W
W
W
here. .100 OM
.T
W O Y. C Y .C W
WW .100Y.C M.TW W . 100 M .TW W
W .100 O M.T
O W O .C
6.3.5.1 STOP
W
W O W .C O
WW
W
0 .CO .TW
Yinstruction WW programming 0 0Y.C clears .TWthe EPGMWbit in the
W
. 100Y M .TW
The STOP 1 0 during EPROM . 1 M W O
.
WW programming OM W O
WW .C
WEPROM 0 Y.C T W
register, WW the
removing 0 0Y.C M.TW
programming voltage from the .100Y .T
W .1 0
O M . W . 1
C O W W .C OM
EPROM. WW .100Y . Y
WW .100Y.C M.TW M.T
W W
W .100 OM
WW .100Y . W Y W W 0 0
W O M.T
W
W .100 O M.T W W.1
W .C
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW Low-Power Modes
M W O Data-Retention Mode
0 Y .CO .TW W W 0 0 Y.C .T W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
6.3.5.2 WAIT W W.1 Y.COM W W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW .C WWon EPROM/OTPROM Y. C
00Y WWThe .WAIT 1 00Y
instruction
M .TWhas no effect . 100 M .TW operation.
. 1 M W O W O
W
0 Y.C
O
0
. 1
WW 00Y.CO .TW
6.4 MData-Retention W ModeW Y .CO .TW W WW 00Y.CO .TW
W 0 0 .1 M
.1 M W.1 Y.COmode, M WW .CO and
WW 00Y.CO .TW WIn W
data-retention
1 0 0 .T the
W MCU retains
W RAM
. 1 0 0 Y
contents
M
W register contents
.TCPU
W. 1 OM at VW .
voltages.C as M
Olow as 2.0 Vdc. TheW W
data-retention O
DDW Y.C feature allows the MCU to
.TW data, but the CPU
WW .100Y.C M.TW W
remain in .a10low0Y power-consumption
M .TW W during
state W . 1 00which
Oit M
retains
W O
WW execute
WW .100Y.C M.TW cannot
.1 0 0 Yinstructions.
M
W W .C O
W 00 Y .T W
To put the MCU .1 M
W.1 Y.COM W W W.1 inYdata-retention
.C OM
W
mode:
WW 00Y.CO .TW
W 1. WDrive the 0
0RESET pin.Tto logic 0. W
W 00
W.1 Y.COM W
W W W 0 T
W . 1 00 M .T 2. W Lower the
W . 10V0DD voltage. O M .TThe RESET pin must W .10remain O M.continuously
low
W O .C WW .100Y. C
WW .100Y.C M.TW
during
WW data-retention 1 00Y M
mode.
.TW M .TW
W O W . O W W .C O
WW .100Y.C M.TWTo take the WW MCU out 00ofY.C .TW mode:W W.100Y OM.TW
data-retention
. 1 M
W O
WWVDD .to
W normal .CO operating W voltage.WW .100Y.C M.TW
WW .100Y.C M.TW 1. Return 1 00Y M .T
W O
W O
WW theWRESET COto logic
Y.pin WW .100Y.C M.TW
WW .100Y.C M.TW
2. Return 0 T W1.
.1 0 M .
W W .C O
W 00 Y .T W .1 M
W.1 Y.COM W
6.5 Timing W W.1 Y.COM W WW 00Y.CO .TW
W W 00 .T W
W
.C W
WW .100Y M .TWOSC W
W . 100 O M .T W
W .100 O M.T
W O (NOTE 1) WW .100Y. C
W O
W O tRL WW
WW .100Y.C M.TW .1 00Y M
W W .C O RESET
W 00 Y .T W .1 M
W.1 Y.COM W tILIH W W.1 Y.COM W WW 00Y.CO .TW
W W
W
W .100 O M2)T
IRQ/V.PP W
W .100 OM
.T
W W.1 Y.COM W
C (NOTE W .C W
WW .100Y. M.T
W W OSCILLATOR Y
.100 STABILIZATION M.TDELAY(5)
W 00
W.1 Y.COM W
.T
W O W .C O W
WW .100Y.CIRQ/VPPM.TW WW .100Y M .TW W .100 M.T
W O W O W W .C O
WW .100Y.C M.TW
(NOTE 3) W
Y
WW .100Y.C M.TW W
W .100 O M.T
W O C
W
WW .100INTERNAL Y.C
O
TW WW .100Y.C M.TW WW .100Y. M .TW
CLOCKOM. W O W O
W
W O
W INTERNAL .CO .TW WW 00Y.CO .TW WW $07FF 0Y.C M.TW
WW .1ADDRESS 00Y W(NOTE
$07FE
1 . 10
BUS OM 4)W. $07FE
OM
$07FE $07FE $07FE
W O
W
W W Notes:Y.CO W WW 00Y.CO .TW RESET OR W WW 00Y.CO .TW
W INTERRUPT
W
W.1.
0
10Internal .Tfrom OSC1 pin
OMexternal
clocking W.1 Y.COM W VECTOR FETCH
W W.1 Y.COM W
.C W
W W
3..1 00Yand level-triggered
2. Edge-triggered
Edge- M .TW external interrupt
interrupt maskW mask.1option
option
W
00
O M .T W
W .100 O M.T
W Reset Y O Y.C WW .100Y .C
WW 4. .C shown.T
vector
00cycles or 128
asW example WW 100 bit inOMOR .TW .T
W . 1
5. 4064
O M cycles, depending on state of .SOSCD
W C
M W W .C OM
WW Recovery . Y
WW .100Y.C Figure W
M.T 6-1. Stop Mode .100
Y
M.T
Timing
W W
W .100 OM
WW .100Y . W Y W W 0 0
W O M.T
W
W .100 O M.T W W.1
W .C
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O Rev. 4.0 W O
WW .100Y.C —M
W O W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1STOP Y.COM W W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW WW .100Y. C
. 1 M W O W O
W
0 Y.C
O
.T W WW SWAIT 0 0Y.CYES M.TW WW .100Y.C M.TW
. 1 0 M W . 1 O W O
WW 00Y.CO .TW WWBIT SET?.100Y.C M.TW WWHALT .100Y.C M.TW WAIT
.1 M W O W O
WW 00Y.CO .TW WW NO .100Y.C M.TW WW .100Y.C M.TW
W
W 00
W.1 Y.COM W
.T .1
CLEAR I BIT IN CCR.
WISCR. C OM W.1 Y.COSET
CLEAR I BIT IN CCR.
BITW
M
CLEAR I BIT IN CCR.
W W 00
W
SET IRQE BIT IN
WAND RTIE.1BITS
T TOF, RTIF, TOIE,
.CLEAR Y .
00IN TSCR. M.T W SET IRQEW IN ISCR.
TURN OFF CPU CLOCK. . 10 0 TURNM .TW
IRQE BIT IN ISCR.
OFF CPU CLOCK.
. 1 M W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
TURN OFF INTERNAL OSCILLATOR. TIMER CLOCK W
WACTIVE. .100Y.CTIMERMCLOCK .TWACTIVE.
W O W O
W
WW .100Y.C M.TW
O
W W .C O
Y W
W
W .10 0
O M.T W .1
C OM YES EXTERNAL W W.1 YESY.CEXTERNAL OM
W Y .C W
EXTERNAL YES
W W 0 Y . T W RESET? W 0 0 RESET?.TW
W 00 .T . 1 0 M . .1 M
W W . 1
.C O MRESET?
W W Y .C O
W W W W
0 Y .CO .TW
W .100
Y
M.NOTW W .100 OM
.T NO 0
W.1 Y.CONO M
W O W C W
W W 00 Y .C
.T W W W
1 00 Y .
M .T W W . 1 0 0 M .TW
. 1 M W . O W O
W O
WW .100Y.C YESM.TINTERRUPT? WW YES.100EXTERNAL Y.C .TW
WW .100Y.C M .T WYES W
EXTERNAL
W INTERRUPT?O M
EXTERNAL W O
W
WW .100YINTERRUPT? .CO .TW WW .100Y.C M.TW WW .100Y.C M.TW
W OM W O W
WW .100YNO .CO .TW
WW .100Y.C M.TW
NO
WW .100Y.C NO M.TW W OM
W C O W W . C O W Y .C W
WW .100Y . .TW Y W W 0 0 M.T
M
W
W . 100 YES OMTIMER .T YES W.1TIMER
C O
W .COON INTERNAL W .C INTERRUPT? WW INTERRUPT? Y. W
WW .100YTURN M .TW OSCILLATOR.W W.100Y OM.TW W .100 O M.T
W O STABILIZATION TIMER. WW .1NO .C
WW .100Y.C M.TW WW .100Y.C MNO 00Y W
RESET
.TW W O M.T
W O C
W
WW .100Y.C M.TW
O
O W YES O W .C O
W
WW .100Y.C END . T W WW .100Y.CRESET? COP
.TW
YES
WWRESET? COP
. 1 00Y M.T
W
O M OF YES W O M W .C O
W
WW .100Y.C DELAY?
STABILIZATION
.TW WW .100Y.C M.TW WW .100Y M .TW
M W O W O
WW .100Y.C M.TW
W O NO
WW .100Y.C M.TW
NO
WW .100Y.C NO .T W
W W .C OM
W 00 Y .T W .1 M
W .T TURN ON CPUWCLOCK.W.100 .T W .1
W 00 OM M
W W.1 Y.COM W W Y .C W W WW 00Y.CO .TW
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W . C W
WW .100Y. 1. LOADMPC.TWITH W RESET VECTOR W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y. Y
OR
WW .100Y.2.CSERVICE M .TW
INTERRUPT. M .TW W
W .100 OM.T
O CPU REGISTERS ON STACK.W W O .C
W
WW .100Y.b.CSET I BIT
a. SAVE W
.INTCCR. W 00Y
M . 1 O M W O
W O PC WITH INTERRUPT VECTOR.WW .C WW .100Y.C M.TW
WW .100Y.C M.TW
c. LOAD
W . 1 00Y M .TW
W W .C O
W WWFlowchart Y.CO .TW W WW 00Y.CO .T
W 00 Y
Figure 6-2. STOP/HALT/WAIT
.T W 0 0 .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W .100 O M .T W
W .100
W O WW
W O W O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW WW .100Y. C
. 1 M W O W O
W Y.C
O
WW .100Y.C M.TW WW .17.00Parallel
Section Y.C W
. 1 0 0 M .T W
W O W O M.TI/O Ports (PORTS)
. 1 M W O W O
OM WW 00Y.CO .TW
W 00 .T W.1 Y.C OMform one 8-bit input/output .1 OM and one 2-bit I/O port.
W W.1 Y.COM W Ten bidirectional
W pins W W WW 0(I/O) 0 Y .Cport .TW
W . 1 00 M .T AllW . 1
the bidirectional 00 portM .T are programmable
pins W . 1 as inputs O Mor outputs.
W W
. 1 00 Y
M .T
NOTE:
W
Connect
W
W
any . 1unused I/O O M pins to an appropriate W 1 0
.logic level, O M.T V or V
either
W O Y.C do not WW .for Y. C
WW .100Y.C M.TW Although WWthe I/O 1 00ports M .TWrequire termination 100properOoperation, M .TWDD termination SS.
. W
W O
WW
W .CO .TW W .C
00Yof electrostatic W damage.
WW .100Y.C M.TW reduces excess1current
. 00Y consumptionM and W the possibility
W . 1 O M.T
W O C
W
WW .100Y.C M.TW
O
W O W O
W O
WWBit 7 .100Y.6C M.T5 W
W Y.C W
WW Addr..100Y.CRegister M .T
Name:W 4 W 3 .100 2 OM.T1
W Bit 0
WW .100Y. Port A M Data W
.TRegister Read: W
PA7 W.1 PA6
00Y MPA5.TW PA4 W PA3W.100PA2 OMPA1 .T
W O Write: WW .C O W Y .C W PA0
WW $0000
0 Y .C (PORTA)
T W
. 66. 0 0 Y .T W W . 1 0 0 M .T
0
W.1 Y.COSee Mpage .1 M WW 00Y.CO .TW
W W Reset:
W WW 00Y.CO .TWUnaffected byW reset
W 00 .T W.1 0 Y.COM W .1 M
W W.1 Port . OMRegister Read:
BCData W
0
W W WW PB200Y.CO See.T W
W
$0001 . 1 00Y M .T Write:
(PORTB)
W .1 00 See
M .T
Note PB3
W . 1 O M Note
W O
W
WW .100Y.See COpage 69.TW
. Reset: WW .100Y.C M.TUnaffected W by
WW .100Y.C M.TW
reset
M W O
W .CO .TRead: WW 00Y.CO .TW WW .100Y.C M.TW
WW Data.Direction
0 Y W W
10 Register
OMA Write: DDRA7 W W.1 DDRA5
DDRA6
.CO DDRA4
M DDRA3 W W
DDRA2
Y.C
DDRA1 O DDRA0
$0004WWW .C(DDRA) Y W W 0 W
. 1 0 Y
0 See page 66. M .T W W
W .1 0 0
O M .T
W . 1 0
O M.T
W O Reset: WW0 .100Y 0. C
WW .100Y.C M.TW
0
WW0 .1000Y.C M0.TW 0 M
0.TW
O Read: 0 W O W W .C O
W WW
Data Y.C B .TW
Direction Register
0 0
0
WW .100Y .C
See Note .TW DDRB3 WDDRB2 . 1 00YSee Note M.TW
W. 1 (DDRB)OM M WW 00Y.CO .TW
$0005
W Y .C
Write:
W W WW 00Y.CO .TW W
W See 00page 69. Reset:.T
W.10 Y.CO0 M W0 .10 0M
0 0 0
W W W 00 .T W
WA Pulldown
Port
W
00
.1Register Read: .T
O M W.1 Y.COM W W W.1 Y.COM W
.C W W PDIA1 00 PDIA0 .T
$0010 WW .1(PDRA) 00Y Write:M.TPDIA7 W PDIA6 W PDIA5 .100 PDIA4OM.TPDIA3 PDIA2
W.1 Y.COM W
W
See page 68. Reset: O W W . C W
WW .100Y.C M.T0W 0 W 0
.100
Y0
M.T
0W 0 W 0
W .100
0
OM
.T
W O W C O W . C W
WW .100Y. 00Y
Read:
.C
WW Register
Port B Pulldown
1 00YWrite: M.TW M .TW W
W .1Note OM.T
. W O C
WW .100Y.
$0011 W(PDRB) O See Note PDIB3 PDIB2 See
WSeeWpage Y.C
71.00Reset: .TW WW 0 W.10 0
0Y.C M0 .TW 0 M .TW
.1 M O 0 W 0 O
W
WW .100Y.C M.TW
O
= Unimplemented WW .100Y.C M.TW WW .100Y.C M.TW
W W .C O
W W W Y .CO W W WW 00Y.CO .TW
Y W 0 M. T
Note:
PB5, PB4, PB1, and PB0
W
W .100be configured
should
.T
OM as inputs at all times. W .10
These bits . C
are Oavailable for read/write W
but W.1not Y.COM W
are
.C W Y W W 0
available externally.W
W
Configuring . 1 0Y as inputs
0them M
W ensure thatWthe pulldown
.Twill W . 100devicesOare M T
.enabled, thus properly W.10 O M.T
W O WW .100Y .C
terminating them.
W O W C O W W .C OM
Y.C WW .Summary . W Y
WWFigure .1007-1. Parallel
W
M.T I/O Port Register W 100
Y
O M.T
W
W .100 OM
W .C O W Y .C W W W 0 Y .C
WW .100Y M.T
W W .100 M.T W.1
0
W O W W .C O W
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O Rev. 4.0 W O
W O W W
MOTOROLA WW .100Parallel Y.C I/O Ports .TW(PORTS) W 65
W O M
W Y.C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
Parallel I/O Ports (PORTS) .TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
7.2 Port A W W.1 Y.COM W W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW .C 8-bit bidirectional WW .100Y. C
00Y WWPort.1A0is 0Yan M .TW port.
M .TW
. 1 M W O W O
W
0 Y.C
O
. 1 0 M Port A Data Register
7.2.1 W O W O
.1
WW 00Y.CO .TW
M The W port A data O WW CO A pin.
.port
WW .100Y.C M.TW
register contains a W latch for each
. 1 00Y M .TW
W. 1 OM W O
WW .100Y.C M.TW WAddress: . 1 $0000 M
W O W O
WW
W .CO .TW
WW .100Y.C M.TW WW .10Bit07Y.C M 6 .TW 5 4 . 1 003 Y 2
M 1 Bit 0
W O W O W W .C O
W .C 00Y PA2M.TW PA1
WW .100Y.C M.TW WRead: . 00Y PA6M.TW PA5
1PA7
W .1PA3
W W . CO W
Write: W Y .C O
W
PA4
W W W
0 Y .CO .TW PA0
W 00 Y .TW W 10 0 .T .1 0 M
W.1 Y.COM W Reset: W.
W .C OM UnaffectedWby Wreset Y .CO .TW
W Y W W 0 0
W
W .100 O M.T
W
W .100Figure OM
.T
7-2. Port A Data Register
W W.1 (PORTA) M
.CO .TW
W Y .C W W W 0 Y .C T W W 0 0 Y
W 00 .T 0 . .1 M
W W
W .100 M.T
PA[7:0] — WPort A.Data
W 100 BitsOM.T W.1 Y.COM W
W C O These W
read/write bits .C
are software programmable. W Data
WW .100Y. M .TW pin is under W . 1 00Y M .TW W
W . 100directionOM
of
.Teach port A
W O Wthe W control O
of the corresponding bitWin data direction Y.C register A.
WW .100Y.C M.TWReset has Wno Y.C
00on .TW W . 100 M .TW
effect
W . 1 port O A M data. W O
W
WW .100Y.C M.TW
O
W O W O
7.2.2 W Direction
WW Data 0 Y.CO Register.T W A WW 0 0 Y.C .T W WW .100Y.C M.TW
0
W Data direction W WWA determines
register 0 Y .CO whether .T W each W
port A pin
W
W .100 O M.T W .10
C O M W W.1is anY.input
C OMor an
WW .100Y. output. C
.TW W W
1 00Y
.
M .TW W .100 M .TW
M . W O
W O WW .CO WW .100Y.C M.TW
WW .100Y.C M .TW $0004 W W.100Y OM.TW
W W .C O Address:
W W Y .C W W WW 00Y.CO .TW
W 00 Y .T W 05 0 4. T 2 W.1 1 M
W.1 Y.COM W
Bit 7 6 3 Bit 0
W W.1 Y.COMRead: W W W W 0 Y .CO .TW
W .100 M.T DDRA7 DDRA6WW.DDRA5
W 100 .T DDRA3 DDRA2 W.DDRA1 10 OM
W O C OM
DDRA4 W .CDDRA0
W W 00 Y . C Write:
.T W W 1 0 0 Y .
M .T W W . 1 0 0Y
M .TW
.1 M . O W O
W O 0 WW 0 .C 0 0WW 0 0Y.C 0
WW .100Y.C M.TW
Reset: 0
W 1 00Y M .TW
0
. 10 M .TW
. W O
W O Figure 7-3. W
WWData.1Direction .CO Register .TW A (DDRA) WW .100Y.C M.TW
WW .100Y.C M.TW 00Y M W O
WW .1DDRA[7:0] 0 Y W
0
W These .C OM
— Data Direction Register
Wport W.1 A Y BitsOM
.Cdirection. W
W
WDDRA[7:0], 0 Y.C
O
W
W Y read/write W bits W
control A 0 0
data .T Reset W
clears 1 0 M.T
W . 1 00 M .T W .1 O M W .
C O
W configuring
WW .1001Y.=CCorresponding
O all port A pins asW
.TW W inputs. .C
00Y asMoutput .TW WW .100Y. M .TW
M port A pin . 1
configured W O
W .CO .TW port AWpin WW 00Y.CO .TW WW .100Y.C M.TW
WW .1000Y = Corresponding configured
. 1 as input
M
W W .C OM
Y W
NOTE:W Avoid 00
W.1glitches OonMport .T A pins by writingWto.1the port O
.C AM data register beforeW W.1 Y.COM W
changing
.C W W
W
W data direction
. 1 00Y register M .TW A bits fromW 0 to 1. .100
W
Y
O M .T W
W .100 O M.T
WW 00Y.C O WW .100Y .C
WFigure W logic of port
.TI/O WWA. .100Y.C M.TW .T
W .7-4
1 shows O the
M W C O W W .C OM
WW .100Y . Y
WW .100Y.C M.TW M.T
W W
W .100 OM
WW .100Y . W Y W W 0 0
W O M.T
W
W .100 O M.T W W.1
W .C
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W W
66 WW .100Parallel Y.C I/O Ports .TW(PORTS) W MOTOROLA
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW Parallel I/O Ports (PORTS)
M W O Port A
0 Y .CO .TW W W 0 0 Y.C .T W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
M .TW W
W . 100 READ O DDRA .T
M
W
W .100 O M.T
.CO .TW WW .100Y. C
W . 1 OM W WRITE DDRA O W W .C O
0 0 Y.C .T W WW .100Y.C M.TW WDDRAx . 1 00Y W
M.T 10-mA SINK CAPABILITY
. 1 M W O W .C O
WW 00Y.CO .TW WW .1WRITE .C
00Y PORTA M.TW WW .100Y .TW (PINS PA4–PA7 ONLY)
INTERNAL DATA BUS
. 1 M W O W O M
WW 00Y.CO .TW
PAx W .C
WW .100Y.C M.TW
PAx
W . 1 00Y M .TW (PA0–PA3 TO
W . 1 O M W C O W W .C O IRQ MODULE)
.C W 0Y . W W 00 Y .T W
WW .100Y .T W W .
READ 1 0PORTA M .T
W . 1 O M
W OM W O
WW .100Y.C M.TW
W W .C O
W
W PDRAY.CO
WWRITE W W WW 00Y.CO .TW
Y W 0 .T
W
W .100 O M.T W .10
.C O M PDRAx
W W.1 Y.COM W 100-µA
PULLDOWN
W
WW .100Y.C M.TW W . 1 00Y RESETM.TW W
W . 100 O M .T
O W O .C
W
WW .100Y.C M.TW WW .100Y.C M.TW WW .SWPDI 1 00Y M.T
W
W O W C O
W O
WW .100Y.C Figure
W Y. .TW
WW .100Y.C M.TW M .TW 7-4. Port AW I/O Circuitry
W .100 O M
W O
W
WW .100Y.C M.TW
O
W W .C O Writing a logic W1Wto a DDRA Y .CO bit enables the outputW
W W
W for Y
buffer
0
the.COcorresponding
.TW
port
W 0 0 Y .T W A pin; a logicW 0 1 0
disables 0 the output .T buffer. . 1 0 M
W.1 OM W. OM W O
WW .100Y.C M.TWhen W WW .100Y.C M.TW WW .100Y.C M.TW
bit DDRAx CO WW O data latch.
W W Y.C O
W W WisWa logicY.1,
0
reading address $0000
. T W W
reads the
0 0 Y.C PAx
.TWon the
W . 1 00 M T
.When bit DDRAx is a logic
W . 10 0, reading O M address $0000 reads W .1the voltage O Mlevel
W O .C written, WWof the.1state .C .TW
WW .100Y.C Mpin. .TW The data latch WW can.1always 00Y be M .TW regardless 00Y of itsMdata
W O
W O direction bit. TableW7-1 W summarizes .CO the operation ofWthe W port A00pins. Y.C W
WW .100Y.C M.TW W . 1 00Y M .TW W . 1 O M.T
W O C
W
WW .100Y.C M.TW
O
WW Table .C
00Y7-1. Port .TAWPin Operation WW .100Y. M .TW
W . 1 O M W O
W O
WW .100Y.C M.TW WW Y.C W
WW .100Y.C M.TW Accesses
W . 1 00to DataOBitM.T
W O Data Direction Bit W W O
.C Pin Mode W Y. C
WW .100Y.C M.TW W 1 00Y
I/O
M .TW WRead . 100 Write M .TW
W . O W O
W
WW .100Y.C M.TW 0
O
WW .Input, .C
00Yhigh-impedance .TW W W
Pin W.10 Latch(1)
0Y.C M.TW
1 M O
W W Y .C O
W W WW 00Y.CO .TW W W 0 0Y.C
1 Latch OM.T
W
W .1 00 M .T 1 . 1 Output M
O Latch W .
W O WW 00Y.C WW .100Y.C M.TW
WW .100Y.C 1. Writing .T W the dataWregister
affects .
but1 does not M
affect . W
Tinput.
W W .C OM
W 00 Y .T W .1 M
W W 00 .T W .1
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
O W O W .C O
W
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W .100 O M .T W
W .100
W O WW
W O W O
W O Rev. 4.0 W O
WW .100Y.C —M
W O W W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
7.2.3 Pulldown Register W W.1 A Y.COM W W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW C W C
. on port
00Y WWPulldown 1 00Y
.register
M .ATW inhibits theW pulldown
. 00Y
1devices M .TWA pins programmed as
. 1 M W
inputs.. O W O
W
0 Y.C
O
1 0 .CO .TWto logic 1, reset
. M
WW 00Y.CO .TWNOTE: WIfWthe SWPDI
W Y .CbitOin the Wmask option W WW 0is0programmed
register Y
0
0 port AMpins T
. as inputs with disabled .1 M
.1 M W.1 all Y
initializes O WW 00pulldown .CO devices.
WW 00Y.CO .TW W W
1 0 0 .C
.T W W . 1
Y
M .TW
W. 1 OM . O M W O
WW 0$0010 0Y.C M.TW WW .100Y.C M.TW
WW .100Y.C M.TW WAddress: . 1
O W Bit 7 O 6 4 W 3 .CO 2
W
5
WW . 1 00Y M .TW
1 Bit 0
W O
WW 00Y.CO .TW
Read:
W O WW Y.C W
WW .100Y.C M.TW WWrite: . 1
PDIA7 PDIA6M PDIA5 PDIA4 W.PDIA3 100 M.T PDIA1
PDIA2
O PDIA0
W CO W W .C O W Y .C W
W Y. W W 0 Y .T 0 W W 0 0 .T
W 00
W.1 Y.COM W
.T Reset: 00
W.1 Y.COM W
0 0
W W.01 Y.C0OM W 0 0
W W W 0 0 .T
W .100 .T
= Unimplemented
W
W .100 O M.T W . C OM W W.1 Y.COM W
C W W
WW .100Y. M.T
W W .100
Y
Figure 7-5.
M.T
Pulldown W
Register
W .A 0
10(PDRA) OM
.T
W O W C O W .C W
WW .100Y.C M.TWPDIA[7:0]W— Pulldown
W Y. W W .100
Y
M.T
W . 100 Inhibit O M A
.TBits W C O
W O C WWReset . .TW
WW .100Y.C M.TW PDIA[7:0] WW disable . 1 0Y.port
0the .TW
AMpulldown devices. . 0Y PDIA[7:0].
10clears M
W O W O
W O
WW .100Yport .C A pulldown W Y.C .TW
WW .100Y.C M.TW 1 = Corresponding M .TW deviceWdisabled W . 100 O M
W O 0 = Corresponding W port O A pulldown device W notWdisabled0Y.C
WW .100Y.C M.TW WW .100Y.C M.TW .10 M.T
W
W O W O
W
WW Port
7.2.4
O
0Y.CDrive .TW WW .100Y.C M.TW WW .100Y.C M.TW
0LED Capability
W W . 1
.C O M
Y W
W 00
W.1 Y.COM All.Toutputs can drive light-emitting .1 M W.1 canYsink M
.CO .TW
W W W WW 00Y.COdiodes T W
(LEDs). These
W Wpins 0 0
W 00 .T
approximately 10 mA of current to V M.. .1 M
W.1 Y.COM W W W.1 Y.COSS W WW 00Y.CO .TW
W W
W
W 100
.I/O O M.T
W
W .100 OM
.T
W W.1 Y.COM W
7.2.5 Port A Pin Interrupts
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C
WW .100Y.IfCthe M .TWbit in the mask
PIRQ WW option Y.
100register M TW
is .programmed W
to logic 1, 0Y
.10PA0–PA3 M .TW
pins
O W . O W .C O
W
WW .100Y(IRQ).)
function
.C as W
.T
external interrupt
WW pins. 00Y
.C Section
(See
.TW
5. External WW Interrupt
. 100
YModule .TW
M
. 1 M
W W .C O M W W Y.C O
W W W W
0 Y .CO .TW
Y W W 00 .T 0
W
.C W W 00 .T
WW .100Y M.T
W O W W .C O W
WW .100Y.C M.TW W .100
Y
M.T
W W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100
W O W C O W W .C OM
.C W Y . W W 0Y
WW .100Y M.T
W W .100 M.T W.1
0
W O W W .C O W
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M W O Port B
0 Y .CO .TW W W 0 0 Y.C .T W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
7.3 Port B W W.1 Y.COM W W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW WW .100Y. C
00Y WWPort.1B0is 0Ya.C2-bitM .TW
bidirectional port.
M .TW
. 1 M W O W O
W
0 Y.C
O
. 1 0 7.3.1M Port B Data Register W O W O
.1
WW 00Y.CO .TW
M The W port B data O WW CO B pin.
.port
WW .100Y.C M.TW
register contains a W latch for each
. 1 00Y M .TW
W. 1 OM W O
WW .100Y.C M.TW WAddress: . 1 $0001 M
W O W O
WW
W .CO .TW
WW .100Y.C M.TW WW .10Bit07Y.C M 6 .TW 5 4 . 1 003 Y M2 1 Bit 0
W O W O W W .C O
W 0 Y.C 0 .TW 00Y PB2M.TW See Note
WW .100Y.C M.TW WRead: . 100 M See Note
W
W .1PB3 O
W O
W
WW .100Y.C M.TW
O
W W
Write:
0 0 Y.C .T W WW .100Y.C M.TW
Reset: W.
1 M Wreset Y.CO
W .C O W .CO .TW Unaffected Wby W
W W
. 1 0 0 Y
M .T W W
W . 0 0 Y
1 = UnimplementedO M
W
W .100 O M.T
W O .C WW .100Y. C
WW .100Y.C M.TW Note: W
W
1 00Y M .TW M .TW
. W O
W O WPB1, W and Y .CO W at all00times. Y.C These.T Ware
WW .100Y.C M.TW . beWconfigured asWinputsW
PB5, W PB4, PB0 should T bits
available forW . 100 butO
read/write are M not available externally. Configuring .1 O
them
C
Mas inputs will
W O Wthe pulldown .C W Y . .TW
WW .100Y.C M.TW ensureW that
. 1 00Y devices M TWenabled, thusWproperly.terminating
.are W 100 O
them.
M
O W O Y.C
W
WW .100Y.C M.TW WW Figure .C
00Y 7-6. Port .TW B Data Register WW (PORTB) . 100 M .TW
W . 1 O M W O
W
WW .100Y.C M.PB[3:2]
O
TW — Port WW .100Y.C M.TW WW .100Y.C M.TW
B Data W Bits O W O
W
WW .100Y.C M.TW
O
W O
W W Y .C O These read/write bits
W W WW are software
0 Y .COprogrammable.
.T W Data
W Wdirection 0 0Yof.Ceach port .TW B pin
W . 1 00 M
is .T
under the control of Wthe. 0
1corresponding O M bit in data direction W .1register B. O MReset has
W O W .C WW .100Y. C TW
WW .100Y.C noMeffect .TW on port W B data. .100Y M .T W
W O M .
WW NOTE: 0 0 Y W .1 be configured M
W W.1 Y.CPB4–PB5 OM and PB0–PB1W
W
should
Y .CO W
as inputs at allW
W W times. 0 Y .CO bits.T
These are
W
W 00 available W
.T for read/write butW W are. 0
10not available M T
. externally. Configuring 0
.1 them as inputs
M
. 1 M O W O
.C them.
W
WW .100Y.will COensure Wthat the pulldown WW devices 0Y.Care M enabled,
TW thus properly WW terminating 00Y W
M .T
W . 1 0
O
. W . 1 O M.T
W O WW .100Y .C
WW .C
00YRegister .T W WW .100Y.C M.TW M .TW
7.3.2 Data Direction.1 M B W O W O
W
WW .100Y.C M.TW
O
W Data .C O
direction register B determines WW 00whether Y .CO each W port B pinW isWanWinput 0or Y.an CO W
W W
.1 0 Y
0output. M .T W W
W . 1 O M .T
W .1 0
O M.T
W O WW .100Y. C
W O W O
W
WW .10Address: 0Y.C M
O $0005
5 W 4 Y.CO 3
W Bit Y O
W
WW .100Y.C M.TW
O Bit 7 6
WW 0 0 .T W 2 WW 1
. 1 0 0 0 .C M.TW
W. 1 M W O
W Read: O0 0
WW CO
See Notes 00Y. DDRB3.TW WW Y.C W
WW .10Write: 0Y.C M.TW . 1 M DDRB2 See Note
W . 1 0 0
O M.T
W O .C
W
WW .Reset: .CO W Y.C 0 .TW0 W W 0Y .TW
1 00Y 0 M.TW0 0W
W .0100
O M 0 W .010 O M
W
WW .100Y.C M=.T
O
W
Unimplemented WW .100Y.C M.TW WW .100Y.C M.TW
W W .C O
Note:
W DDRB5, 00 Y .T W 1 configured .1 M
W.1 DDRB4, C OM DDRB1, and DDRB0 should
W W.be .C OM as inputs at all times. These WW 00Y.CO
W Y . W but areW Y
00externally.MConfiguring
.T W W
them as inputs 1
W bits are .100 that the .T
available for read/write not available
W
will ensure O Mpulldown devices are enabled, W.1 thusYproperly C O terminating them. WW. .COM
.C W . W W 0Y
WW .100Y M.T
W W .100 M .T W.1
0
W FigureO 7-7. Data Direction W W Register .C O
B (DDRB) W
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O Rev. 4.0 W O
W O W W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W
W .100
DDRB[3:2]
.T
O—MData Direction Register W W.1B Bits .CO .TW
M
W W Y .C W W 0 Y
M.T
W 100 read/write
.These .T bits control portW 10 direction.
B.data M
.CO W W Y .C OM
W W W 0 Y .CO .Reset T W
clears DDRB[3:2],
Y W W 0
configuring all T
port
. B pins as inputs. 0
00
W.1 Y.COM W
.T 0
W.1 1 = Y .C OM
Corresponding port B pin W W.1 Y.as
configured
M
COoutputTW
W W W 0 0 .
W .100 O M.T
W
W .010=0 CorrespondingOM
.T
port B pin configured W W.1 Y as.C OM
input
C W .C .TW
W
100Y
.
M .TW W . 1 00Y M .TW W
W . 100 O M
. O
Wglitches on port B pins by writingWto the port C data register
.B
WW 00Y.CO .TW NOTE:
WW .100Y.C M.TW
Avoid W . 1 00Y M .TW before changing
W. 1 OM data direction
W register
O B bits from 0 to 1. W O
W O Figure W7-8 shows the O I/O logic of port B.WW .CO .TW
WW .100Y.C M.TW WW .100Y.C M.TW W 1 00Y
W O W C O W W .
.C OM
.C W Y . W W 0 Y W
WW .100Y M .TW W
W . 100 O M .T W .10 O M.T
W O READ DDRB
WW .100Y. C
W O
W O WWDDRB00Y.CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW WWRITE . 1 M W O
W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
DDRBx
WW .100Y.C M.TW
W O
INTERNAL DATA BUS
W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TWPBx
WRITE PORTB
WW .100Y.C M.TWPBx
W W .C O
W 00 Y .T W .1 M
W.1 Y.COM W READ PORTB W W.1 Y.COM W WW 00Y.CO .TW
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W W .100 M.T W.1 Y.C100-µA OM
W O WRITE PDRB W C O W
WW .100Y.C M.TW WW .100Y . PDRBx
M .TW W . 100 PULLDOWN M .TW
W O
W O
WW RESET
WW .100Y.C M.TW . 1 00Y M
W O W O SWPDIWW .CO .TW
WW .100Y.C M.TW WW .100Y.C M.TW W .1 00Y M
W W .C O W WFigureY7-8. .C OPort B I/O CircuitryWW
W W 0Y .CO .TW
Y W W .100 .T 0
W
C W W bufferW
WW .100Y. Writing M.T
aW logic 1 to aW DDRB bit 0Y
.10enables M.T
the output .100
for the corresponding
W
.T
OMport
W O W .C O W Y .C W
WW .100Y.BCpin;Ma.T logic
W 0 disables WW the output
. 100
Ybuffer.
M .TW W .100 M.T
W O W O W W .C O
.C bit.T WW 1, reading .C W 0Y latch.M.TW
WW .100YWhen M
W
DDRBx is a logic . 1 00Y address M .T$0001 reads Wthe PBx
W . 10data O
W O 0, W
W .C O W Y.Con the.TW
WW .100pin. Y.C bit DDRBx
When
T W is a logic W reading
0 0 Yaddress $0001
.T W reads the W voltage0level
1 0
W TheO M . latch can alwaysWbe
data .1 written,Oregardless
C
M of the state W W .
of its data .C OM
.C W . W Y W
WW .10direction
0Y bit.
M
W 7-2 summarizes
.TTable W
W . 10the0Y operation
O M .T of the port W B pins. W .100 O M.T
W O WW .100Y. C
W Port B O Operation W O
W
WW .100Y.C M.TW
O TableW
W
7-2.
00Y
.CPin
.TW WW .100Y.C M.TW
W .1 O M W O
W
WW .100Data
O
Y.C Direction .T W WWI/O Pin 0 0 Y.C .T W AccessesWtoWData .Bit 10 0Y.C M.TW
Bit
W. 1 Mode
OM W O
W OM WWWrite.100Y.C M.TW
WW .100Y.C M.TW WW .100Y.C M.TWRead
W W .C O0
W Input,W W
high-impedance Y .CO .TWPin W WW(1) 00Y.CO .TW
Latch
W 00 Y .T W 0 0 .1 M
W.1 Y.C1OM W W W.1 Y.COM Latch
Output W WW 00Y.CO .TW
Latch
W W 00 .T W
W
. C W W 00 .T
WW1. Writing Y
.100 affectsOthe .TWregister, butW
Mdata 100 input.OM.T
does not .affect
W.1 Y.COM
W W .C W
W W .100
W O W C O W W .COM
. C W Y . W W 0Y
WW .100Y M.T
W W .100 M.T W.1
0
W O W W .C O W
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M W O Port B
0 Y .CO .TW W W 0 0 Y.C .T W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
7.3.3 Pulldown RegisterW W.1 B Y.COM W W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW C W C
. on port
00Y WWPulldown 1 00Y
.register
M .BTWinhibits theW pulldown
. 00Y
1devices M .TWB pins programmed as
. 1 M W
inputs.. O W O
W
0 Y.C
O
1 0 .CO .TWto logic 1, reset
. M
WW 00Y.CO .TWNOTE: WIfWthe SWPDI
W Y .CbitOin the Wmask option W WW 0is0programmed
register Y
0
0 port BMpins T
. as inputs with disabled .1 M
.1 M W.1 all Y
initializes O WW 00pulldown .CO devices.
WW 00Y.CO .TW W W
1 0 0 .C
.T W W . 1
Y
M .TW
W. 1 OM W . O M W O
Address:W $0011 O W O
W
WW .100Y.C M.TW
O
WW .10Bit07Y.C M . T W WW .100Y.C M.TW
W W .C O W W Y .CO .TW
6 5
W
4 W
W
3
0 Y .CO 2 .TW 1 Bit 0
W 00 Y .TW W 0 0 .1 0
W.1 Y.COM W
Read:
W.1 Y.COM W WWPDIB3 OM
.CPDIB2
W W 00 .T W W
Write:
1 0 0 M .T See Note W . 1 0 0 Y
M .TW See Note
. 1 M W . O W C O
W O
WW .100Y.C M.TW 0 WW 0 00Y. 0 W
WW .100Y.C M.TW Reset: 0
W . 1 O M.T
0 0
W O C
W O
WW .100Y.C M.TW Note: W
W 00Y
.C
= Unimplemented
.TW WW .100Y. M .TW
. 1 M W O
W O WW devices .CO .TW enabledWwhen W 0Y.CPB1 and W
WW .100Y.C M.TW These Wpulldown . 1 00Y are permanently
M WPB5,. 1 0PB4,
O M.TPB0 are
O W O .C
W
WW .100Y.C M.TW
configured
WW .100Y.C M.TW
as inputs.
WW .100Y M .TW
O
W Figure 7-9. Pulldown Register W O
W O
WW .100Y.C M.TW WW B (PDRB) Y.C .TW
WW .100Y.C M.TW W . 100 O M
WW .100Y.C M.PDIB[3:2] TW —W Pulldown.1Inhibit B BitsM
W O W Y.C
O WWclears .CO .TW
0YPDIB[3:2].
WW .100Y.C M.TPDIB[3:2] W WW the
disable 0port
0 B pulldown .T Wdevices. W Reset 1 0
W O 1 = Corresponding W.1 portYB C OM
pulldown device disabled W W .
.C OM
.C W . W W 0Y W
WW .100Y M .TW0 = Corresponding W
W . 00 B pulldown
1port O M .T device not disabled W .10 O M.T
W O WW .100Y. C
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W . C W
WW .100Y. M.T
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W .C O W
W O W O W W .C O
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100
W O W C O W W .COM
.C W Y . W W 0Y
WW .100Y M.T
W W .100 M.T W.1
0
W O W W .C O W
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O Rev. 4.0 W O
WW .100Y.C —M
W O W W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
7.4 I/O Port Electrical W W.1 Characteristics.C OM
W W
M .TW W
W . 100
Y
O M .T W
W .100 O M.T
.CO .TW W Y.C W WW .100Y. (V M=.T5.0 C W (1)
. 1 00Y M
WTable 7-3. . 1 00I/O Port M DC .TElectrical CharacteristicsW O DD V)
. W Y W W 0 0 T
M.(2)
W .100
Y
O M.T
W
CharacteristicW .100 OM
.T Symbol
W W.1Min Y.COTyp Max Unit
W Y .C W W W 0 Y .C T W W 0 0 .T W
0 . 1
.100 Current M.T Drain Per Pin
W.1 Y.COM W I W.— .CO .TW
M
— 25 mA
WW 00Y.Output CO High W W W 0 Y
.1 M–2.5.TW Voltage W 00
W.1 Y.COM W VOH
.T 10
W.–0.8 C OM
W (I.C O = mA) PA4–PA7 W W V Y . — W — V
WW .100Y(I = M W .100 M.T —
Load W DD
–5.5.TmA) PB2–PB3,
W
PA0–PA3 W . 100 O M .T V W –0.8 —O
W O
Load DD
WW .100Output Y.C Low Voltage .TW
W (I Y.C=O10.0 mA)W M WW 00Y.CO .TWVOL W W—
W
0 Y.— CO W0.8 V
W W
. 1 00 Load
M .T PA0–PA7, W
PB2–PB3
W . 1 O M W .1 0
O M.T
W .COVoltage WxWV .100Y. C
WW .1Input 0 0 YHigh .T W WW .100Y.C M.TWVIH 0.7 M .TVW V
W PA0–PA7, M
PB2–PB3
O W C O W
DD W — .C O DD
W .C W Y . W W 0Y T W
W Y
.100 Low Voltage
Input M.T
W W
W .100 OM VIL
.T 0
W.1 Y.CO0.2 M.
W C O W .C W .TW
x VDD V
WW PA0–PA7, 1
.
00Y PB2–PB3 M .TW W . 1 00Y M .TW VWSS
W .10—0 O M
. W O
W
WW I/O .Ports .COLeakage
0YHi-Z .T WCurrent WW .100Y.C M.TW WW .100Y.C M.TW
0
W
PA0–PA7,
W 1
.C OM (Without Individual WW
PB2–PB3
W Y .CO IIL.TW —
W WW0.2 00Y.CO ±1 .TW µA
Y W 0
W Pulldown
W .100Activated) O M.T 0
.C W
W
W Input Pulldown. 1 0Y Current
0PB2–PB3 M .TW W
W . 100 O M .T W
W .100 O M.T
WW Activated) O I
WW .100Y . C µA
WW .100Y.C ILM.TW
PA0–PA7, (With Individual 35 80 200
WPulldown 0 0 Y.C .T W M .TW
.1 OM W O
WW 0Vdc Y.±C10%, V.SS W W WW 00Y.CO .TW WW .100Y.C M.TW
W1. VDD = 5.0 0 T = 0 Vdc, T = –40°C to .1
+85°C, unless otherwise noted.
2. Typical
1
W.values C
reflectOM average measurementsW
A
at Wmidpoint Y of.C OM range, 25°C.
voltage WW 00Y.CO .TW
W Y . W W 0 .T W W .1
W 00
W.1 Y.COM W
.T .10 M WW 00Y.CO .TW
M
W W WW 00Y.CO .TW W 1
W 00 .T W.1 Characteristics OM V).(1) M
.CO .TW
W W.1 YTable .C OM7-4. I/O Port DC Electrical
W W 0 Y .C W
(VDD = 3.3
W W W
0 0 Y
W .T
W
W .100 CharacteristicO M.T W .10Symbol
.C OM Min Typ (2)
W W.1Max Y.COMUnit W
.C W Y W W 00 .T
WW Per.1Pin 00Y M.T
W W .100I M.T— W .125 OM
Current Drain W O W C O — W .C mA
W
WWVoltage 00Y
.C .TW WW .100Y. M .TW W .100
Y
M.T
Output High
W .1 O M W O W W .C O
.C WW V.1OH .C .TW —.100
Y V .TW
(ILoad = –0.8 WW mA) PA4–PA7
00Y .TW 00Y VDD M
–0.3 — W M
(ILoad = –1.5 mA)W
W
.1
PA0–PA3, PB2–PB3 .C O M W W Y . C O
VDD –0.3 W — W W W— 0 Y .CO .TW
00Y W W 00 .T 0
W
Output Low VoltageW.1 O M.T W.1 Y.COM W W W.1 Y.COM W
.C W W 00 V M.T
(ILoad = 5.0 mA) WW PA4–PA7 .100
Y
M.T
W W V .100 —M.
T — 0.5W.1 O
W O
W 0.5 .100Y.C M.TW
OL
W W .C O W .C
Y — .TW — W
(ILoad = 3.5 mA) WPA0–PA3, Y
PB2–PB3
0 .T W W 0 0
Input High Voltage WW
.10
.C OM W W.1 Y.COM W WW 00Y.CO .TW
W 0 Y W W 0 0 .T W DD W.1
PA0–PA7, PB2–PB3 W.10 O M.T V
W
IH
W .1 0.7 x
.C
V DDM
O — V
W
V
Y
M
.CO .TW
W Y .C W W 0 Y T W W 0 0
Input Low VoltageW 00
W.1 Y.COM W
.T
VILWW
.10 V OM. — .1
WW 0V0Y.CO .TW
M
PA0–PA7, PB2–PB3WW Y SS.C W 0.2 x VDD
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C
I/O Ports Hi-Z Leakage Current
WW .100Y. Pulldown M.T
W W
IIL .10— 0Y .TW
M0.1 ±1
W 100
W.µA OM
.T
PA0–PA7, PB2–PB3 (Without Individual
W O W C O W .C
Activated) WW .100Y.C M.TW WW .100Y .
M .TW W . 100
Y
M .TW
W O W .CO
Input Pulldown Current
W WW 00Y.CO .TW I WW .12 1 0 0Y.C 30 .
W
TW 100 W µA .100Y OM.T
.1 Pulldown Activated) M IL
W O M W
WW .100Y.C M
PA0–PA7, PB2–PB3 (With Individual
W WW 00Y.CO .TW WW .100Y.C M.TW
1. VDD = 3.3 Vdc ± 10%, VSS= 0 Vdc,
W W.1TA = Y –40°C
.C OM to +85°C, unless otherwiseW
W
noted.
W 25°C. Y .CO .TW W WW 00Y.CO
2. Typical values reflect average W measurements00 at midpoint
.T of voltage W
range, 0 0 .1
W.1 Y.COM W W W.1 Y.COM W WW
W W 0 0 .T W
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
W
W .100 O M.T
W
W .100 OM
.T
C W .C
Data Sheet WW .100Y. W W
M.T .100
Y — Rev. 4.0
W O W W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y.CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW WW .100Y. C
. 1 O M W O W .C O
W
0 Y.C .T W WW .100Y.C M.TW WWSection . 1 00Y 8. Resets M.T
W and Interrupts
. 1 0 M W O W .C O
. 1 M W O W O
OM WW 00Y.CO .TW
W 00
W.1 Y.COM W
.T
Reset W.1 Ythe
initializes .C OMCU M by returning theW W.1 counter
program Y
M
.CO to.aTknown W address and
W W 00 and M W W 10 0
W . 1 00 M .T byW forcing W . 1
control O
.T bits to known states.
status W . O M
W
WW .100Y.C M.TW
O
O the sequenceWofWprogram O
W O Interrupts WW temporarily
Y.C change 0Y.Cexecution TWto respond to
WW .100Y.C M.TW events Wthat 0 0
.1 during M
occur .T W
processing.
W . 1 0 M .
W W .C O
Y W
W
W .10 0
O M.T W .1
.C OM W W.1 Y.COM W
C W W
WW 8.2.10Resets 0Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TWA reset immediately WW .100stops Y. the operation
.TW of the Winstruction Y
.100 beingOexecuted,
M.T
O W O M W .C
W
WW .100Y.C M.TW WW control
initializes certain .C
00Yand status .TW bits, and loads WW the.1program 00Y counter M .TWwith a
user-defined reset W . 1
vector O M
address. The following W O
WW .100Y.C M.TW
W O sources can generate a reset:
W W .C O
W
• Power-onWreset W (POR) Y.CO circuit
W W WW 00Y.CO .TW
W 00 Y .T W 10 0 .T .1 M
W W.1 Y.COM •W RESET pinWW. 0Y.COM W W WW 00Y.CO .TW
W 0 .T 1
W
W .100 O M.T• Computer operating W W.1 properly .C OM(COP) watchdog WW. Y .C OM
W
.C Y W W 0
WW .100Y M .TW W
W . 100 O M .T W .10 O M.T
W O • Illegal address
WW .100Y. C
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W WW 00Y.CO .TW
ILLEGAL ADDRESS
W WW 00Y.CO .TW
W 00 Y .T W .1 M
W.1 Y.COM W COPW W.1 Y.COM W
WATCHDOG WW 00Y.CO .TW
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. VDD W
M.T
POWER-ON
W RESET
.100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W .C O W
WW .100Y.CRESETMPIN .TW WW .100Y M .TW D S QWRST WPERIPHERAL .100 AND OM.T
TO CPU
W O W O W .C
WW .100Y.C M.TW WW .10INTERNAL 0Y.C CLOCK M .TW CK W MODULES
. 1 00Y M.T
W
W O W C O
W O
WW .100Y.C M.TW RESET W
W Y. .TW
WW .100Y.C M.TW W . 100 O M
W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
LATCH
WW .100Y.C M.TW
W O
W O Figure W
WW 8-1..1Reset .CO Sources WW .100Y.C M.TW
WW .100Y.C M.TW 00Y M .T W
W O
W
8.2.1 Power-On Reset .1 .1 M
W W .C OM
Y W
W
W.1 Y
00 transition
A positive .T
OM on the VDD pin W W.1 Ya.C
generates OM
power-on reset. W W.1 Y.COM W
.C W
W W
. 1 00 M .TW W
W . 100 O M .T W
W .100 O M.T
NOTE: WW
The O
power-on.Creset is strictly Y.C and.cannot WW .C
00Y supply W for power-up WW conditions 100 TW be used to detect0Y
0 .T
Wdrops
W in. 1power O M .Tvoltage. W .
.C O M W W.1 Y.COM
W W .100
W O W C O W W .COM
.C W Y . W W 0 Y
WW .100Y M.T
W W .100 M.T W.1
0
W O W W .C O W
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O Rev. 4.0 W O
WW .100Y.C —M
W O W
MOTOROLA WW .100YResets .C
and
W
.TInterrupts WW 73
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y . C W
W O M.T
Resets and Interrupts M.TW WW .100Y.C M.TW
00 .1 M
W 00 W
A.14064-t.cyc
W M.T clock cycle)W
O(internal W.1 afterY.the
delay
M
COoscillator becomes active allows
W W
W the.1clock Y C
0 generator W W
T to stabilize. If any reset 0
0 source M TW
.active
.T 0 . .1
.COM WtheW Y .CO .in
M
W W WW until 0 Yall.CO .TW at the end of this delay,
is
00 Y .T W W MCU
.10 0 remains T the reset condition .1 0 reset sources are inactive.
W.1 Y.COM W W C O M W W .C OM
WW .100Y. .TW Y W
. 1 00 M .T W O M
W
W .100 O M.T
WW 00Y.CO .TW Y.C WW .100Y .C
WW .100VDD M .TW M .TW
. 1 M W O W C
.DELAYO
WW 00Y.CO .TW
(2)
WW .100Y.C M.TW
(NOTE 1) OSCILLATOR
WWSTABILIZATION . 1 00Y M .TW
W. 1 OM W O W O
OSC1 PIN
WW .100Y.C M.TW
W O
W O
WW
WW .100Y.C M.TW INTERNAL00Y
.1 M
W W .C O
W WW 00Y.CO .TW
CLOCK
W WW 00Y.CO .TW
W 00 Y .T W .1
W.1 Y.COM W W.1 Y.COM W WW $07FE OM
.C$07FE
W W
INTERNAL
W 0 .T
$07FE $07FE W $07FE 0 0 Y W
.T$07FE $07FF
W . 1 00 M .T ADDRESS BUS
. 1 0 M W . 1 O M
W O W C O W .C
WW .100Y.C M.TW WW .100Y. .TW W .100
Y TW
M.NEW
INTERNAL
W O M W C O
WW .100Y.
W O PCH NEW PCL
WW .100Y.C M.TW .TW
DATA BUS
WW .100Y.C M.TW W O M
O W O Y.C
W
WW .100Y.C M.TW 1. Power-on
Notes:
WWreset .threshold0 0 W 1 V andW2 W
Y.Cis typically.Tbetween V. W. 1 0 0 M.T
W
W 1 O M C O
W O Wor 128 cycles, Y.C WW bit in MOR 0Y . .TW
WW .100Y.C M.TW 3. InternalWclock, internal
2. 4064 cycles depending on state of SOSCD
. 1 00address M
bus, .TW
and internal data bus are not available
W . 10 externally.O M
O W O Y.C
W
WW .100Y.C M.TW WW .10Figure 0Y.C 8-2. TW
.Power-On WW Timing
Reset . 100 M .TW
W O M W O
W
WW .100Y.C M.TW
O
W O W O
8.2.2 WExternal Reset
WW .100Y.C M.TW
O
W O WW an0external O
W .C O A logic 0 applied toWthe Y .Cpin W W 0 Y.C reset. W
W W
. 1 00 Y
M .T W W
W
RESET
. 10 0
O
for
M .T1 1/2 tcyc generates
W .1 O M.T A
W OSchmitt trigger senses .C WW .100Y. C
WW .100Y.C M.TW WW the.1logic 00Y
level at the
M .TW
RESET pin.
M .TW
W O W O
W
WW .100Y.C M.TW
O
W W .C O INTERNAL
W 00 Y .TCLOCK W .1 M
W W 0 W
W
W .100 O M.T
INTERNAL W .10$07FE O M.T $07FE $07FF NEW W W .1
PC.CO
M
W Y.CADDRESS BUS W W
$07FE
W 0 Y .C $07FE
T W W PC NEWY
0 0 .TW
W 1 00 M .T . 1 0 M . W . 1 O M
. W O
W
WW .100Y.C INTERNAL
O
.T W WW .100Y.C M.TNEW W NEW
WW .10OP 0Y.C M.TW
OMBUS W O
WW 00Y.CO .T
DUMMY
W .C DATA PCH
W
PCL
W W CODE 0 Y.C W
W W
.1 00 Y
M .T W W
W . 1 O M W .1 0
O M.T
W O t
WW .100Y. C
WW .100Y.C RESET WW .100Y.C M.TW .TW
RL
M .TW W O W O M
W
WW .1Notes: .CO .TW WW .100Y.C M.TW WW .100Y.C M.TW
00Y M internal address bus, W Oare not available externally.WW O
W 1. Internal Oclock, andW .Cbus 0Y.C M.TW
WW .12.00The Y.Cnext rising.T W of the internal
edge Wclock internal data
.
after 1 00
the
Y
rising edge M .
of T W initiates the
RESET
Wreset sequence.
. 10
OM W O
W WW 00Y.CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW Figure W 8-3. External .1 ResetMTiming
W W . C O
W 00 Y .T W .1 M
W.1 Y.COM WTable 8-1. External W W.1 Reset Y .C
M
OTiming
W WW 00Y.CO .TW
W W 00 .T W
W
W .100 O M.T W.1 Symbol .C OM Min W W.1 Y.COM
.C W Y W W Unit.100 .T
WW .100Y Characteristic
M .TW W . 100 M .T Max
W OM
W O W . C O W Y .C
W Pulse
RESET .C
Width
Y W WW .100tRL Y
M.T
1.5 W — W tcyc
.100
W
W .100 O M.T W W . C O W W Y .C OM
WW .100Y .C W Y W W 0 0
W O M.T
W
W .100 O M.T W W.1
W .C
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W
74 WW .100YResets .C
and
W
.TInterrupts WW MOTOROLA
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y . C W
W O M.T
.TW WW .100Y.C M.TW Resets and Interrupts
M W O Interrupts
0 Y .CO .TW W W 0 0 Y.C .T W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
8.2.3 COP Watchdog
W .100
WReset OM
.T
W W.1 Y.COM W
W .C W
M .TW W
W . 100
Y
O M .T W
W .100 O M.T
.CO .TW Cthe COP
.of W C
Y. reset. W COP watchdog is part
00Y WWA timeout . 1 00Y M .TWwatchdogW generates
. 10a0COP O M .TThe
W . 1 O M ofW a software O detection systemW
error W
and must Y be .Ccleared.Tperiodically to start a new
0 0 Y.C .T W WW timeout . 1 0 0Y.C To
period. M .TW the COPWwatchdog
clear . 1 00and prevent M
W
a COP reset, write a
. 1 M O WW at00location O
WW 00Y.CO .TW WW0 to0bit
Wlogic 0 Y.0C(COPC) .T W of the COP W register Y .C .T
$07F0. W
W.1 Y.COM W .1 M
.1
WW 00Y.CO .TW
M W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W .1 8.2.4OM
.C Illegal Address Reset W W.1 Y.COM W W
WW .100Y W W .100 M.T
W 00 .T
W O M.T W .C O W W.1 Y.COM W
W
WW .100Y.C M.TW
AnW opcode fetchY from an.T address
W not W in RAM or 0EPROM generates a reset.
W .100 O M W .1 0 O M.T
W O W .C
Y
M.T
W
8.3 Interrupts W O W C O
W
WW .100Y.C M.TW
O
W O generate interrupts: W O
W
WW .100Y.C M.TW
O The following WW sources 00Y
.Ccan .TW WW .100Y.C M.TW
W . 1 O M W O
W
WW .100Y.C M.TW
O • SWI WWinstruction 0 0 Y.C .T W WW .100Y.C M.TW
W. 1 OM W O
W O
WW .100Y.C M.TW • External WW interrupt 0 0 Y.Cpins .TW WW .100Y.C M.TW
.1 M WW 00Y.CO .TW
W W Y.C O
W – IRQ/V
W WWPP pin 0 Y .CO .TW W
W 00 .T 0
W.1 pinsY.COM W .1 M
W W.1 Y.COM W – PA0–PA3 W W WW 00Y.CO .TW
W 0 .T
W
W .100 OM.T • Timer WW.10 .C OM W W.1 Y.COM W
WW .100Y .C W Y W W 00 .T
W O M.T
W
– Real-timeWinterrupt .100 flag
O
.T
M(RTIF) W W.1 Y.COM W
WW .C
WW .100Y.C M.TW – Timer overflow Y
.100flag (TOF) M.T
W W
W .100 O M.T
W O W O W .C
WW .100Y.C M W
.Tinterrupt WW .100Y.C M.TW W Y
.100a particular
W
M.Tevent.
O An temporarily W stops the program
O sequence to W
process .C O
W
WW .100Y.C An .TW doesW
interrupt
W
not stop .the Y.C
00operation TW
.of the instruction WW being . 00Y
1executed, M
but
W
.Ttakes
M W 1 O M W O
W O WW Interrupt .C
WW .100Y.C effect .T when
W the current WW instruction .1 0 0Y.Ccompletes M .TW its execution. . 1 00Y processing M.T
W
M W O W C O
W O
automatically saves the WCPU registers .C on the stack and W loadsW the program Y. counter .TW
WW .100Y.CwithM a TW
.user-defined Winterrupt . 1 00Y address.
vector M .TW W . 100 O M
W O
W
WW .100Y.C M.TW
O
8.3.1 SoftwareW W Interrupt .C O
W 00 Y .T W .1 M
W W 00 causes W
.Ta non-maskable interrupt.
W
W .100The software O M.T interrupt (SWI)Winstruction W.1 Y.COM W W W.1 Y.COM W
WW .100Y .C W W 00 .T
W O M.T
W
8.3.2 External W Interrupt Y.C W . C W
W .100 M.T
W W
W .100
Y
O M.T
W
W .100 OM
.T
W O C W .C W
WW An 0Y.C M
0interrupt .TWon the IRQ/V
signal WWPP pin . 0Y. anMexternal
10latches .TW interrupt W request. Y
.100WhenOM.T
. 1
Wthe CPU O W it.C O W
W IRQ latch .C
WW set, 0Y.CPU
0the
Ccompletes
.TW
its currentWinstruction,
W
. 1 00Y
tests theTIRQ
M . W
latch. IfW the
. 00Y is M.TW
1clear,
.1 M
then tests the I bit in the condition code register. If the I W
bit is O
W CO
.then WW 00Y.CO .TW W W 0 Y.C W
WW the.CPU 1 0 0 Y begins
M .T W W
the interrupt sequence.
W . 1 O M W . 1 0
O M.T
W .CO .TW WW .100Y .C
WWThe CPU 00Yclears M WW .100Y.C M.TW M .TW
W .1 O the IRQ latch during interrupt
W processing,
O so that another W W
interrupt .C O
WW signal.1 on00theY.CIRQ/V.PP T W pin can WW
latch another . 1 0 0Y.C M
interrupt .TW during W
request the interrupt. 1 00Y M .TW
OM W O W .C O
WW routine.
Wservice 0 Y.C As soon T Was the I bitWisWcleared 0 Y.C the .return
0during TW from interrupt, WW the 1 00Y .T
CPU Wcan
0
.1 recognize O
.
Mthe new interrupt request. W . 1
Figure
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8-4 shows the IRQ/V W Wpin Y.COM
.
WW .logic. Y.C W WW .100Y M.T
W W PP .100
interrupt
W 100 O M.T W C O W W .C OM
.C W Y . W W 0Y
WW .100Y M.T
W W .100 M.T W.1
0
W O W W .C O W
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O Rev. 4.0 W O
WW .100Y.C —M
W O W
and
W
.TInterrupts WW 75
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
0 0 .1 M
W 00 .T W
W W .100
TO BIH & BIL
M .TW W
W . 00
1IRQ O M .T W O M.T INSTRUCTION
.C O W Y .C W W W 0 Y .C T W PROCESSING
0 0 Y .T W W 1 0 0 M . T 1
LEVEL-SENSITIVE
. 0 TRIGGER M .
W.1 Y.COM W . W LEVELY .CO .TW
W WW 00Y.CO .TW W W(MOR
1 0 0 BIT)
0 M.T W. OM IRQF
.10 W.1 OM Y.C
WW 00Y.CO .TW WW .100Y.C M.TW WW VDD
. 1 0 0 M .TW
. 1 M W O W O
WW 00Y.CO .TW WWPA3 .100Y.C M.TW WWD IRQ.1Q00Y.C M.TW EXTERNAL
INTERRUPT
W . 1 O M W O W W
LATCH .C O
W Y .C W W W PA2 0 Y .C .T W W 0 0 Y .T W REQUEST
W 00 .T . 1 0 M CK . 1 O M
W.1 OM PA1 W
W Y.C
O
WW
W
0Y.C IRQE .TW
WW .100Y.C M.TW WPA0 . 1 00 M .T W CLR
W . 1 0
O M
W O
W
WW .100Y.C M.TW
O
WW .10PIRQ 0Y.C M.TW WW .100Y.C M.TW
W (MOR) O W O
W
WW .100Y.C M.TW
O
W W .C O
W WW 00Y.CO .TWRESET W WW 00Y.CO .TW
Y W
W
W .10 0
OM.T W .1
.C OM W W.1 Y.COM W
C W IRQ VECTOR WFETCH
WW .100Y. M.T
W W .100
Y
M.T IRQR
W
W .100 OM
.T
W O W C O W . C W
WW .100Y.C M.TW WW .100Y. M .TW W 00Y
.1Logic M.T
O W Figure O 8-4. External Interrupt W .C O
W
W O W O
W O bitWin the 0 0Y.C M WW external Y.C .TW
WW .100Y.C M.TSetting W the IW
. 1 condition code.TWregister disables W . 100 interrupts. O M
W O W
WW interrupt .CO .TW WW 00Y
.C W
WW .100Y.C M.The TW port A external . 1 00Y bit (PIRQ) M in the mask option
W .1 register O M.T pins
enables
W O W O W .C
WW .100Y.C MPA0–PA3 .TW WW as.10external
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W O W
WW sensitivity .CO .TW WW option 00Y
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WW .100Y.C M The.TW external interrupt . 1 00Y bit M (LEVEL) in the mask W . 1 registerO Mcontrols
O W O Y. C
W
WW .100Y.C interrupt .TW triggering
W
Wsensitivity Y.C
00of W
external.Tinterrupt pins. WW The IRQ/V
.100 PP pin Mcan W
.Tbe
M . 1 M W O
W Onegative-edge triggered
WWcan .be .CO .TW and low-level
Wonly orYnegative-edge
WW triggered. Y.C Port A W
WW .100Y.C external M .T Winterrupt pins 1 0 0positive-edge M triggered only or W .
both1 00positive-edge
O M.T
O W O Y. C
W
WW .100Y.Cand M .TW triggered.
high-level WW The.1level-sensitive
00Y
.C .TW triggering option WW allows . 100 multiple M.TW
W wire-ORed O M W .C O
W CO
WW .100Y.external interrupt WW to be
sources 0Y.C Mto Tan W external W W
interrupt 00YAn external
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M .T W
W . 1 0
O
. W . 1 O M.T
W interrupt
O request, shown in Figure 8-5,
.C is latched as long as any
WW .100Y
source is
.C holding
WW .100Yan .C
external .TW interrupt pin Wlow. W
1 00Y M .TW M .TW
M W . O W O
W
WW .100Y.C M.TW
O
W W . C O
W WW 0t0ILILY.CO .TW W WW 00Y.CO .TW
W 00 Y .T W .1 M
W.1 EXT. . C OM W W.1 Y.COM W WW 00Y.CO .TW
W W 00 W
W 00Y INT. PIN .T tILIH W
W.1 Y.COM W
.T .1 M
W
W .100 O M.T
W
C
. PIN1 .TW W . C W
WW .1EXT. W ILIH .100Y W .100 .T
INT. t
00Y.. M W O M.T W .C OM
W O C W W
WW .100.Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
WEXT. INT. PINn O W O W .C O
W O W O
W
WW .100IRQY.C M.TW
O
W W(INTERNAL) .CO
W 00 Y .T W 1 M .1 M
W.1 Y.COM Figure 8-5. External W W.Interrupt Y .C OTiming
W WW 00Y.CO
W W W 00 .T W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100
W O WW
W O W O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W
76 WW .100YResets .C W
.TInterrupts
and WW MOTOROLA
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y . C W
W O M.T
M W O Interrupts
0 Y .CO .TW W W 0 0 Y.C .T W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 M.T 8-2. ExternalW W.1 Y M
W W.1 Y.COTable W Interrupt 0 .CO (V
Timing W= 5.0 Vdc)(1)
.T W W 0 0 .T W .1 0 M .T DD
OM .1 M WW 00Y.COSymbol
Y .C W W WW 00Y.CO Characteristic .T W W 1 .TW Min Max Unit
. 1 00 M .T W . 1 O M W . O M
W
0 Y.C
O
.T W WWInterrupt 0 Y.C Width .Low
0Pulse TW(Edge-Triggered) WW .100Y.C tILIH M.T
W 125 — ns
. 1 0 M W . 1 O M W C O
WW 00Y.CO .TW WW .100Y tILIL M.TWNote(2) .
WW Interrupt 0
. 1 0Y.CPeriodM.TW
Pulse — tcyc
W . 1 O M W C O W W . C O
W .C W1.WVDD =.15.0 .
Y ±10%, V.TSSW= 0 Vdc, TA W 00Y unless .T W
. 100Y M .TW W
00Vdc
O M = –40°C to.1+85°C,
W C O Motherwise noted.
W .C O 2. The
W minimum .tCILIL should not
W be less than the
W number of
Y .interrupt service
W routine cycles plus
WW .100Y W W 19 tcyc..100Y M.T
W 00 .T
W O M.T W . C O W W.1 Y.COM W
WW .100Y.C M.TW WW .100Y .TW
MExternal
W .100 M.T
W Table O
8-3. Interrupt W
Timing (V .C O (1)
W W Y .C O
W W W 0 Y .C .T W W W 0 0 YDD 3.3.TVdc)
= W
W 00 .T 0
W.1 Characteristic OM .1 M
W W.1 Y.COM W W Y .C W W WW Symbol 0 Y .CO Min .TW Max Unit
W 00 .T W . 1 0 0 M .T . 1 0 M
. 1 M W O
W O Interrupt W W .CO WW .t1ILIH 00Y
.C 250.TW —
WW .100Y.C M.TW WPulse Width .TW
Low (Edge-Triggered) ns
. 1 00Y M W O M
O W O Y. C
W
WW .100Y.C M.TW InterruptW
W Period00Y.C
Pulse
.TW WW tILIL .100 Note M
(2) W—
.T tcyc
. 1 M W O
W O 3.3W
W .C=O0 Vdc,.TTW W unless00otherwise Y.C noted. .TW
WW .100Y.C M.TW 1. VDD = W Vdc ±10%,
. 1 0 0VYSS M A = –40°C to W +85°C
W . 1 O M
O 2. The minimum Wt should notO be less than the number of interrupt C
service
. routine cycles plus
W
WW .100Y.C M.TW 19 tcyc. W
W ILIL
0 0 Y.C .T W WW .100Y M .TW
W. 1 OM W O
W
WW .100Y.C M.TW
O
8.3.3
W .C O
WTimerYInterrupts W WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 .T W .1 M
W.1 Y.COM TheWtimer can generate W W.1 theYfollowing.C OM interrupt requests:
W WW 00Y.CO .TW
W W 0 .T W
W
W .100 O M.T• Real time WW.10 .C OM W W.1 Y.COM W
.C W
WW .100Y M .TW W
W . 100
Y
O M .T W
W .100 O M.T
W O • Timer overflow WW .100Y. C
W O
W O W
WWcondition .CO register W interrupts. 00Y
.C W
WW .100Y.C Setting M .T Wthe I bit in the
.1 0 0Ycode M .TW disablesW timer
W . 1 O M.T
W O C
W
WW .100Y .CO .TW WW .100Y.C M.TW WW .100Y. M .TW
8.3.3.1 Real-Time Interrupt M W O W O
W
WW .100Y.C M.TW
O
W W A.C O
real-time interrupt occurs WW if the real-time
Y .CO interrupt W flag, RTIF, W
W
Wbecomes 0 Y COwhileTW
.set
W Y
.100 the real-time
W
M.T interrupt enable
W
W
0
.10RTIE, isOalso
bit,
T
M. set. RTIF and RTIE 0
1 in the O
W.are M.
timer
W O C W .C
WW .100status Y.C and.T W register.
control WW .100Y .
M .TW W . 1 00Y M .TW
OM W O W O
W
W O W O
8.3.3.2 Timer Overflow W Interrupt
WW .100Y.C M.TW
O
O W O
W A timer . C O WWoccurs Y .C W W W 0 Y.C W
W W
. 1 00 Y overflow
M .T Winterrupt W
request
W .1 0 0 if the
O
timer
M . T overflow flag, TOF,
W . 0
becomes
1 O M.T
Wset while O timer overflow interrupt .Cbit, TOIE, W and0TOIE Y. C
WW are 0in0Y
.Cthe TW and control
.status WW enable 1 00Y M .TW
is also set.WTOF
. 1 0 M .TW
.1 the timerM .
register.
W O W O
W
WW .100Y.C M.TW
O
W W .C O
8.3.4 Interrupt Processing
W 00 Y .T W .1 M
W
W The CPU takes the .following W to begin
actions 00 servicing .an T interrupt: W
W .100 O MT W.1 Y.COM W W W.1 Y.COM
.C W W 00 .T
WW• Stores Y
100 theOCPU
.Figure M
W
.Tregisters onW the stack .10in0 the order M.T shown in
W.1 Y.COM
W W .C O W
WW .100Y.C M.TW
8-6 WW .100Y M.T
W W .100
W O W C O W W .C OM
• W Sets theYI.C bit in the W condition code W register to
Y . prevent further
W interrupts
W 0 0Y
W
W .100 O M.T
W
W .100 O M.T W W.1
W .C
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O Rev. 4.0 W O
W O W
and
W
.TInterrupts WW 77
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
0 0 .1 M
W 00 .T W
W.1• Loads C OM the program counter W W.1 the Ycontents
with .CO .of
M the appropriate interrupt
.T W W W 0 Y .
0vector locations: .T W W .1 0 0 M TW
. 1 M W O
OM W CO WW .interrupt 0Y.C vector) .TW
0 0 Y.C .T W WW .10–0Y.$07FC M .T
and W$07FD (software 1 0 M
. 1 M W O
W Y.C
O W
WW .1–00Y$07FA .CO and TW WW interrupt .C
00Y vector) W
. 1 0 0 M .T W
W O M . $07FB (external
W . 1 O M.T
WW 00Y.CO .TW Y.C and.T$07F9 W .C
WW .–100$07F8 M
W (timerWinterrupt . 0Y
10vector) M .TW
. 1 M O W O
WW 00Y.CO .TW W
The WW 0Y.C M.TW(RTI) instruction
return-from-interrupt
0 WW causes 1
.C
00Y the CPU Wrecover the CPU
.Tto
1 . 1 W . O M
W. OM W .COstack.TasWshown in W W 8-6. .C W
WW .100Y.C M.TW WW from
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. 1 00Y
the
M
Figure
. 1 00Y M.T
W O W O
W
WW .100Y.C M.TW
O
W W . C O
W WW 00Y.CO .TW W WW 00Y.CO .$00C0 TW
(BOTTOM OF STACK)
W 00 Y .T W . 1 M .1 M
W.1 OM W O W O $00C1
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M$00C2 .TW
W O
W O W
WW UNSTACKING .CO .TW W 00Y
.C W
WW .100Y.C M.TW . 1 00Y M •W
W . 1 O M•.T
W O W .C O • WW Y. C • .TW
WW .100Y.C M.TW WW ORDER . 1 00Y M .TW .100 M
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
•
WW .100Y.C • M.TW
W W .C O
Y W
W 00
W.1 Y.COM W
.T 5 1 .1
W .C OM CONDITION CODE REGISTER W W.1 Y.COM W
W W
W W
. 1 00 M .T 4 W 2
W . 100
Y
O M .T ACCUMULATOR W
W .100 O M.T
W O .C W REGISTER WW .100Y .C W
WW .100Y.C M.TW 3
WW 3
. 1 00Y M .TINDEX M.T
W O W O
W
WW .100Y.C M.TW 1
O 2
WW .100Y.C M.TW
4 PROGRAM COUNTER (HIGH BYTE)
WW .100Y.C M.TW
W W .C O
W
5
WW 00Y.CO .TW PROGRAM COUNTER (LOW BYTE)
W WW 00Y.CO .TW
W 00 Y .T W .1 M .1 M
W W.1 Y.COM W WW 00Y.CO .T• W W WW 00Y.CO .TW
W 00 .T W .1 • M
W.1 Y.COM W W W.1 Y.COM • W WW •00Y.CO .TW
W W
W
W .100 O M.TORDER
STACKING W
W .100 OM •
.T
W W.1• Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W $00FD .C W
WW .100Y.C M.TW WW .100Y. M .TW W $00FE.100Y M.T
O W O W .C O
W
WW .100Y.C M.TW WW .100Y.C M.TW WW$00FF (TOP
.
Y
100OF STACK)OM.T
W
W O W .C O W W .C
WW .100Y.C M.TW WW 8-6..1Interrupt
Figure 00Y .TW OrderW W.100Y OM.TW
Stacking
M
W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O 8-4. Reset/Interrupt
Table
WW Vector 0 0 Y.C Addresses
.T W WW .100Y.C M.TW
W .C O W.1
LocalWW Global0Y.C
OM Priority
W WWVector 0 Y.C
O
W
Function WW Y W 0 .T W 1 0 M.T
. 1 00 Source
M .T Mask W .
Mask1 O M
(1 = Highest) W .
Address C O
W
WW .10Power-On 0Y.C M.TW
O
W O W O
W
WW .RESET .CPinO
W None WWNone.100Y.C M1.TW WW .100Y.C M.TW
00Y .T $07FE–
1 WW 00Y.CO .TW
Reset $07FF
W W Watchdog
COP .C O(1)M WW 00Y.CO .TW W
W Illegal 0 Y .T W W .1 M
0Address
W W 00 Same Priority .T W
Software Interrupt W
User
W
0
.10Code O M.T None None W.1
. C OM $07FC–W W.1 Y.COM
$07FD
(SWI) .C W as
Y Instruction W W 00 .T
WW .100Y .TW W .100 M.T W.1 Y.COM
External Interrupt W
IRQ/V Pin COM IRQE I Bit W . C 2 O – W
WW .100Y.
PP
.TW WW .100Y M.T
W $07FA W $07FB
.100
W
RTIF Bit O MRTIE Bit W C O W W .C OM
.C W Y . W $07F8–W 0Y
Timer Interrupts
WWTOF Bit .100
Y
M .TW
TOIE Bit
I Bit
W .100
3
M.T
$07F9
W.1
0
W C O W W .C O W
WW .1in0the 0Y.mask W Y W W
1. The COP watchdog is programmable
W O M.T register.
option W
W .100 O M.T
WW .100Y. C
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W
and
W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M W O Interrupts
0 Y .CO .TW W W 0 0 Y.C .T W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
M .TW W
W . 100 O M .TFROM RESET W
W .100 O M.T
.CO .TW WW .100Y. C
. 1 M W O W O
W
0 Y.C
O
. 1 0 M W O
W YES O
WW 00Y.CO .TW WW .100Y.C M I BIT.T W
SET? WW .100Y.C M.TW
.1 M W O W O
W W.1 Y.COM W WW 00Y.CO NO W W WW 00Y.CO .TW
W 00 .T W .T .1 M
W W 00 .T W
W
W .100 O M.T W.1 Y.EXTERNAL C OM YES W W.1 Y.COM W
.C W W
WW .100Y W .1 0 .T
CLEAR IRQ0LATCH.
M .TW W
W . 100 INTERRUPT? O M .T W C OM
W O W .C W Y . .TW
WW .100Y.C M.TW W . 1 00Y NO M.TW W
W . 100 O M
W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
WW .100TIMER Y.C .T W WW .100Y.C M.TW
W OM YES W O
W
WW .100Y.C M.TW
O
WW INTERRUPT? 0 0 Y.C .T W WW .100Y.C M.TW
.1 M WW 00Y.CO .TW
W W Y.C O
W W WW 00Y.CO .TW W
W
W .100 O M.T W .1 NO OM
.C
STACK PC,
W
SET I BIT. W.1 Y.COM W
X, A, CCR.
.C W W
W W
. 1 00Y M .TW W
W . 100
Y
O M .T LOAD PC WITH W
INTERRUPT
W .100
VECTOR.
O M.T
W O WW .100Y .C
W
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W WWNEXT00Y.CO .TW
FETCH W WW 00Y.CO .TW
W 00 Y .T W .1 M .1 M
INSTRUCTION.
W W WW 00Y.CO .TW W
W 00 .T W.1 Y.COM W .1 M
W
W .100 O M.T
W
SWIWW
.100 OM
.T
W W.1 Y.COM W
C .C W
WW .100Y.
YES
M.T
W W
INSTRUCTION?
W .100
Y
O M.T
W
W .100 OM
.T
W O C W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
O W O W .C O
W
NO
WW .100Y M .TW
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W
RTI
WW YES
Y
O
.CUNSTACK W W WW 00Y.CO .TW
W 00 Y .T INSTRUCTION? W 0 0 .T
CCR, A, X, PC.
.1 M
W W 00 .T W .1
W W.1 Y.COM W NO W W WW 00Y.CO .TW
W
W .100 O M.T
W
W .100EXECUTEOINSTRUCTION.
M.T W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW FigureW8-7. Interrupt
W Y. .TW W .100
Y
M.T
W . 100 FlowchartO M W C O
W O WW .100Y .
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
W.100 O M.T W.1 Y.COM W W W.1 Y.COM
.C W
WW .100Y M .TW W
W .100 O M.T W
W .100
W O WW
W O W O
W O Rev. 4.0 W O
WW .100Y.C —M
W O W
MOTOROLA WW .100YResets .C W
.TInterrupts
and WW 79
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
OM.T
WW .100Y .C W
W O M.T
Y.CO .TW W WW 00Y.CO .TW
0 0 .1 M
W 00 .T W
W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW WW .100Y. C
. 1 M W O W O
W
0 Y.C
O
. 1 0 M W O W O
.1 M W O W O
W 00 .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100 OM
.T
W O C W .C
WW .100Y.C M.TW W W
1 00Y
.
M .TW W . 100
Y
M .TW
W . O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
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W 00
W.1 Y.COM W
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W O W .C O W
W O W O W W .C O
Y
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W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
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WW .100Y M.T
W O W .C O W
W W .100
W O W C O W W .COM
.C W Y . W W 0Y
WW .100Y M.T
W W .100 M.T W.1
0
W O W W .C O W
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W
and
W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
M .TW W
W . 100 O M .T W
W .100 O M.T
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. 1 M W O W O
W
0 Y.C
O
.T W WW .100Y.C M.TW Section WW 9..10Multifunction0Y.C M.TW Timer Module
. 1 0 M W O W O
.1 M W O
W.1 9.1 Introduction
M .1 M WW 00Y.CO .TW
W Y .C O
W W WW 00Y.CO .TW W
W 00
W.1 Y.COM W
.T W.1 Y.Ctimer
The multifunction OM provides a timingWreference W.1 Ywith M
.COprogrammable real-time
W W 00 .T W W
1 00 M
W
.T 9-2 shows the timer W . 0 0
1organization. M .TW
. 1 M interrupt W .
capability. Figure
O W O
W
WW .100Y.C M.TW
O
W O
WW 9.2 0 Y
Features W
0
W Features W of the 0
multifunction .Ttimer include: W
W
W .10 0
O M.T W .1 0
.C OM W W.1 Y.COM W
C W W
WW .100Y. M.T
W • Timer W overflow .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW • Four WW Y. W W .100
Y
M.T
selectable
W . 100 interrupt O M .T
rates W C O
W O .C WW timer Y . .TW
WW .100Y.C M.TW • Computer WW operating . 1 00Y properly M .TW(COP) watchdog . 100 M
W O W O
W
WW .100Y.C M.TW
O
9.3
W W
Operation .C O
W 00 Y .T W .1 M
W W 00preceded W
T a prescaler that divides
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W
W .100 O MA.T15-stage ripple counter, W.1the timing .C OM W W.1 the Y .C
internal
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W of
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WW .100Y M .TW W
W . 10can0
O M .T W .10 O M.T
W O the first eight timer stages be
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W the
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WW .100Y.C register .TWat address WW 1 00timer M .TW function W .100 stageOallows M .TWa
M $0009.W . A overflow
O at the eighth
W
W
WW .100Y.C timer
O
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interrupt every WW 1024 internal0 0Y.Cclock TW
cycles.
. WW .100Y.C M.TW
.1 M
W W .C OM
W Y
00 TheM next.T four stages lead W W 1 real-time
to .the .1 RT1 and M
W.1 Y.bits C O W .C OMinterrupt (RTI) circuit. W WThe Y.CO RT0 W
W .TW Y W W
at.Taddress $0008 allow.1a0timer interrupt 0 M.T
W .1 00 in the
M
timer statusW and control
W . 100 register O M W C O
W O W four0stages .
WW .100Ythe
every
.C 16,384, 32,768, W
.TW COP system.
65,536,
W or0131,072
. 1 0Y.C M clock
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Y
1 0 3.OM.T
drive W
M
selectable For
W information O on the COP, refer toWSection
W
WW .100Computer Y.C
O
. T W
Operating WW .Module
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1 M
W W .C OM
W 00 Y .T W .1 M
W
W Name.100 .T Bit 7 6W 00 .T W 1W.1 Bit 0 OM
Addr. Register
W OM W5.1 Y4.COM 3 W 2
W .C W
W W 0 0 .C
Y Read: .TTOF W RTIF W W
. 1 0 0 M .
0 T 0
W . 1 0 Y
0 M.T
Timer Status and Control . 1
Register M W O W RT0.C O
W
WW (TSCR) .CO WW .100Y.C TOFR
TOIE RTIE
.TW RTIFR W W.100Y OM.TW
W
RT1
$0008
.1 00Y Write: M.TW W O M
SeeW page 83. .CO
WW .100YReset: 0.TW 0 WW0 .1000Y.C 0M.TW 0 W1W .1010Y.C M.TW
W W .C OM
W WW TMR4 Y .CTMR3O
W W WW 00Y.CO .TW
Y W 0 M. T
W .100 M.T .10 W.1 Y.COM W
Timer Counter Register Read: TMR7 TMR6 TMR5 TMR2 TMR1 TMR0
W
(TCR) O W .C O W
$0009 W W
See page 84..10Write: 0Y.C M.TW WW .100Y M .TW W .100 M.T
O W O W .C O
W
WW .1Reset: .C W Y.C .TW WW 0 .100Y .T
00Y 0 M.TW 0 W
0
W 0 .100 0
O M 0 0 W .C OM
W O .C W Y
WW .100Y.C M=.TUnimplemented W WW .100Y M.T
W W .100
W O W C O W W .C OM
.C W Y . W W 0 Y
WW .100Y TW
M.I/O
W .100 M.T W.1
0
W Figure O
9-1. Register Summary
W W .C O W
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O Rev. 4.0 W O
W O W W
MOTOROLA WW .100Multifunction Y.C TW Module W
.Timer 81
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
Multifunction Timer Module .TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM WRESET
W W.1 Y.COM W W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW WW .100Y. C
00Y WW .100Y.C OVERFLOW M .TW M .TW
W . 1 O M W C O W W .C O ÷ 4 INTERNAL CLOCK
.C W Y . W TIMER COUNTER
W REGISTER
0 Y T W (XTAL ÷ 2)
. 1 00Y M .TW W
W . 100 O M .T BITS [0:7] OF W .10
15-STAGE O M.
WW 00Y.CO .TW WW .C
WW .100Y.C M.TRESET W RIPPLE COUNTER 0Y
. 10 M .TW
. 1 M W O W O
W W. 1
.C OM
W 00 Y .T W .1 M
W.1 Y.COM W W.1 Y.COM W WW 00Y.CO .TW
INTERNAL DATA BUS
W W W 00 .T W
W
W .100 O M.T W.1 Y.COM W W W.1 Y.COM WREQUEST INTERRUPT
W Y.C W W W 0 .T W 0 0 .T
W 00 .T 0
W.1 Y.COM W .1 M
W 00 .T W 0 0 .T .1 M
W W
W .100 M.T
W .100 .T W.1 Y.COM W
RTIFR
OM
TOFR
TOIE
RTIE
W
RTIF
W C O W .C TOF
W W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. TIMERMSTATUS/CONTROL .TW W
REGISTER
.100
Y
M.T
O W O W .C O
W
RT0
RT1
W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W . 100 RTI RATE O M .T
SELECT W .100
RESET
W O M.T
W O WW .100Y. C
CLEAR COP TIMER
W O W O W W .C O
WW .100Y.C M.TW WW ÷ .2100Y.÷C2 M÷.T2 W ÷ 2 W÷ 2 ÷. 1 00Y ÷ 2 M.TW
WW 00Y.CO .TW
2
W W Y.C O
W W WW 00Y.CO .TW W
W 00 .T W.1 BITS [8:14] M .1 M
W W.1 Y.COM W W Y .C
OF
O15-STAGE
W
RIPPLE COUNTER
W WW 00Y.CO .TW
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W ÷ .C
WW .100Y. M .TW W . 1 00Y8
M .TW S WQ
W .100
COP RESET
OM
.T
W O W C O W .C
WW .100Y.C M.TW WW .100Y .
M .TW W . 1 00Y M .TW
W O W O
WW .100Y.C M.TW
W ORESET R
W O
WW .100Y.C M.TW W
Figure 9-2. Multifunction .1 Timer M Block DiagramWW O
W W
. 1 00 Y
M .T W W
W .1 O M W . 1 0
O M.T
W .CO .TW WW .100Y. C
9.4 InterruptsWW 00Y WW .100Y.C M.TW M .TW
.1 M W O
WW The.1following
00Y timer sources canWgenerate . 1 interrupts: M
W W .C OM
W 0
• .10Timer
Y .T flag (TOF) — The W 1 bit isOset M when the first eight .1 M
W .C
overflow
OM W W.TOF Y .C W W W stages
0Y .CO .TW
W W over fromW$FF to .$00. W 0
W .100
Y counter.Troll
of the
M W 100 The O M.Toverflow interrupt
timer enable
W.1 Y.COM
W bit, TOIE, .C O enables TOF interrupt W requests. .C W W
WW .100Y W W .100
Y
M.T
W 00 .T
W O M.T W .C O W W.1 Y.COM
• Real-time Y.C interrupt Wflag (RTIF)W— WThe RTIF Ybit is set.Twhen W the selected W RTI 00
WW .100 becomes M.Tactive. The real-time 100
.interrupt M bit, RTIE, enables W .1 OM
Woutput C O W W .C O
enable W Y.C
WW RTIF . W Y W W 0 0
W
0Y
.10interrupt O M.T
requests. W
W .100 O M.T W W.1
W .C
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W W
82 WW .100Multifunction Y.C TW Module W
.Timer MOTOROLA
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW Multifunction Timer Module
M W O I/O Registers
0 Y .CO .TW W W 0 0 Y.C .T W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
9.5 I/O RegistersWW.1 .C OM
W W
M .TW W
W . 100
Y
O M .T W
W .100 O M.T
.CO .TW .C registers WWmonitor Y. C
00Y WWThe .following
1 00Y M .TW control and . 100the timer M .TW
operation:
. 1 O M W O W .C O
W
0 Y.C .T W WW • .1Timer 0 0Y.Cstatus .Tand W control register WW (TSCR) . 1 00Y M.T
W
. 1 0 M W O M W .C O
WW 00Y.CO .TW WW• .Timer 1
.C
00Y counter .T W
register (TCR) WW .100Y M .TW
. 1 M W O M W O
W W. 1 9.5.1OM
.C
Timer Status and Control
W WW 0Register Y .CO .TW W WW 00Y.CO .TW
W 00 Y .T W 0 .1 M
W.1 Y.COM W W W.1 Y
The read/write .C
timer OM statusW and controlWregister WW performs 0 Y .CO the.TfollowingW functions:
W W 00 .T W 1 00 .T . 10 M
. 1 M W . O M W O
W
WW .100Y.C M.TW
O • W
W Flags.1timer 00Y
.C
interrupts
.TW WW .100Y.C M.TW
W O M W O
W
WW .100Y.C M.TW
O • Enables
WW .10timer 0Y.Cinterrupts .T W WW .100Y.C M.TW
M WW 00Y.CO .TW
W W Y .C O
W • W WW timer
Resets 0 Y .CO .flags
interrupt
T W W
W
W .10 0
O M.T • Selects W .1 0
real-time .C O M
interrupt rates W W.1 Y.COM W
C W W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W W .C O W Y.C W
WW .100Y.C M.TW Address:W $0008 .100Y M .TW W
W .100 O M.T
O W O .C
W
WW .100Y.C M.TW WBit W7 006Y
.C 5.TW 4 WW3 . 1002
Y
M 1.T
W Bit 0
. 1 O M W O
W O WW RTIF .C W0W .1000Y.C M.TW
WW .100Y.C M.TW Read: W TOF
. 1 00Y M .TW RTIE ORT1
W W .C O
W Write: WW 00Y.CO .TW
TOIE
TOFR
W WW RTIFR 0 0 Y.C .T W
RT0
W 00 Y .T W .1 .1 M
W.1 Y.COM WReset: 0 WW 0 .C O0 M 0 0 WW 0 Y .CO1 .TW1
W Y W W 0 0
W
W .100 O M.T
W
=W .100
Unimplemented OM
.T
W W.1 Y.COM W
.C W Y .C W W 0
WW .100Y M .TW Figure
W
9-3. W . 100 Status
Timer O M .T
and Control Register W .10(TSCR) O M.T
W O WW .100Y. C
W O W O
W
WW .100Y.C TOF
O
—
.T WTimer Overflow WW Flag 0 0Y.C M.TW WW .100Y.C M.TW
.1
W W .C OM This read-only flag W W
becomes set
Y
O the first eight stages
.Cwhen W W WW of the 0 Y .CO roll
counter .TW
W 00 Y W
.Tfrom $FF to $00. TOF W . 1 0 T
0generatesMa. timer overflow interrupt . 0
1 requestOifM
. 1 M
over O W TOIE
W O WW 00Y.C W .C
00Yto TOFMhas .TW
WW .100Y.C is also M .T W
set. Clear W
TOF by writing
. 1 a logic M .TW
1 to the TOFR Wbit. .
Writing
W 1 O
O W O .C
W
WW .100Y.Cno effect. .TWReset clears WWTOF..100Y.C M.TW WW .100Y M .TW
M W O W O
W
WW .100RTIF
O
Y.C — Real-Time .T W Interrupt WW Flag.100Y.C M.TW WW .100Y.C M.TW
W W This
.C
M
Oread-only flag becomes WWset when Y .Cthe O selected RTI outputWbecomes
W W
W
0 .CO .TW
Yactive.
W 00 Y W W 0 0 .T 0
.1 RTIF O
W.1 RTIF M.T
Ogenerates a real-time interrupt
W W.1 Yrequest .C OM if RTIE is also set. WW Clear
Y
M
.C by .TW
W Y . C W W 0 W
.T has no effect. ResetW 0 0
W 00writing
W.1 RTIF. OM
.T 1 to the RTIFR
a logic bit. 0Writing
W.1 Y.COM W
to RTIF
W W.1 clears Y.CO .TW
M
W .C W W W 0 0
W
W .100
Y
O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C
—. Timer Overflow W . C W
WW TOIE 00Y
.1This
W
M.T bit enables timer
Interrupt
W Enable
W
Y
Bit
.100 interrupts. O M.T Reset clearsW
W
W .100 OM
.T
W O
read/write overflow Y. C TOIE. Y .C W
WW .1010Y .C .TW interrupts WW enabled . 100 M .TW W .100 M.T
= Timer M overflow W O W .C O
W
WW .1000=YTimer .CO overflow .TW interrupts WWdisabled 00Y
M W . 1 O M W O
WW
W
RTIE — Y.C
Real-Time
0
O
. W
Interrupt
T Enable WWBit .100Y.C M.TW WW .100Y.C M.TW
0
W This
1
W. read/write .C OMbit enables real-time
W WW interrupts. Y
O
.CReset W
clears RTIE. W WW 00Y.CO .T
W 0 Y .T W 10 0 .T .1 M
W 1.1 =0Real-time .C OMinterrupts enabledWW. .C OM
W WW 00Y.CO
W W 00 Y W
W 0 =.1Real-time 00Y M .T
interrupts disabled W
W.1 Y.COM W
.T W.1 Y.COM
W .C O W W
WW .100Y M .TW W
W .100 O M .T W
W .100
W O WW
W O W O
W O Rev. 4.0 W O
WW .100Y.C —M
W O W W
.Timer 83
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W
W .100 — Timer
TOFR
.T
OM Overflow Flag Reset W
1
W.Bit .CO .TW
M
W W Y .C W W 0 0 Y
M.T
W 100 a O
.Writing logicM.T1 to this write-only bit.1clears M
.C O W W Y .C W W W W
0 Y .the
COTOFTbit.
. W
TOFR always reads as
00 Y .TW W logic0 0 0. Reset T
clears
. TOFR. .1 0 M
W
W .100 O M.T
W RTIFR
W .10—0 Real-Time .TInterrupt Flag Reset
OM1 to this write-onlyW .1Bit
Wclears OM
.CRTIF
W Y.C W W W Writing 0 a
Y .C
logic T W W bit 0 0 Y
the TWRTIFR always reads
.bit.
100 M .T . 1 0 0. Reset M . W . 1 O M
. asW logic O clears RTIFR.
W. 1 OM RT1Wand W RT0Y— O WW Bits O
.C .CReal-Time W
Interrupt Select
W 0Y.C W
W W
. 100 Y
M .TW W 10
These .read/write
W
0
O bits
M .T select one of four W .1 0
real-time M.T rates, as shown in
interrupt
O
W
WW .100Y.C M.TW
O
W W 9-1.00Because
Table Y.C .TWselected RTI
the WW output . 0Y.C theMCOP
10drives .TWwatchdog,
. 1 M W O
W O changing
WW .1the
W .CO .interrupt
real-time rate W alsoWchanges .C
00Ythe counting Wrate of the COP
WW .100Y.C M.TW watchdog. 0 0Y
Reset sets M TW
RT1 and RT0. W .1 O M.T
W O C
W
WW .100Y.C M.TW
O
W O
W ONOTE: ChangingWRT1 W andYRT0 .COwhen a
WCOP timeout WWis imminent .Ccan cause
00Yinterrupt .TW
a real-time
WW .100Y.C M.TW interrupt W request . 1 0to0 be missed M .Tor an additional . 1 M
W W .C O
W W W Y .CO W W WW 00Y.CO .TW to be
real-time request
W 00 Y W
.T generated. To prevent 0
10 this occurrence, .T clear the COP .1 timer before M changing RT1
W W.1 Y.COM Wand RT0. WW. 0Y.COM W W WW 00Y.CO .TW
W .T
W
W .100 O M.T W .10
.C OM W W.1 Y.COM W
C W W Interrupt
WW .100Y. M.T
W W Table
.100
Y9-1. Real-Time
M.T
W Rate.Selection 00
W 1 Y.COM W
.T
W O W .C O W
WW .100Y.C M.TW WW .100Y M .TW W .100Minimum MCOP .T Timeout
W O W O
RTI Period COP Timeout W
Period
W .C O
WRate 0(f0Y.C Y .TW
WW .100Y.C M.TW
Period
MHz).TW(–0/+1 RTIW
RT1:RT0 RTI
W 1 OP = 2 O Period) .100
W . M W (fC O =M 2 MHz)
O WW .100Y.
OP
W
WW .100Y.C M.TW WW14 .100Y.C M.TW M .TW
W O 0 0 fOP ÷ 2 W 8.2 msO 8 x RTI Period W W O
.C65.5 ms .TW
WW .100Y.C M.TW WW .100Y.C M.TW W . 1 00Y M
W W .C O 0 1 fOP ÷ 2W 15 W 16.4Yms .CO .TW 8 x RTI PeriodWW
W
0 .CO ms .TW
Y131.1
W 00 Y .T W W 10 0 .1 0 M
W.1 Y.COM 1 0W fOP ÷ 216WW. 32.80ms .C OM WW 00262.1 Y .COms .TW
W W Y .T8 Wx RTI Period W
W
W .100 O M.T W .10
.C OM W W.1 Y.COM W
C W W
WW .100Y. 1 1 W fOP ÷ 217
M.T
W .10ms
65.5 0Y M8.Tx RTI Period
W
W
0 ms M.T
.10524.3 O
W O W C O W Y.C W
WW .100Y.C M.TW WW .100Y. M .T W W . 1 0 0 M.T
O W O W .C O
W
WWCounter .C .TW WW .100Y.C M.TW WW .100Y .TW
9.5.2 Timer
.1 00YRegister M O W O M
W .CO .TW WW 00Y.C TWThe valueWof the first
W Y.C
00eight .TW
WW .100AY15-stage ripple counter
Wis the . 1
core of the M .
timer. W . 1 O M
W OM WW CO WW 0Y.C inM.TW
WW .10stages 0Y.C is M .TW at anyW
readable time from . 1 0Y.read-only
0the M .TW timer counter register . 1 0shown
W O
W .CO WW 00Y.CO .TW WW .100Y.C M.TW
WW .1Figure 0 0 Y 9-4.
.T W W .1 M
W W .C OM
Y W
W
W
0
.10Address: O $0009
M .T W .1
C W W 2
WW .100Y. Bit 7.TW 6
M
W5 .1004
Y
M3 .T W1
W .10Bit0 0 OM
.T
W O W C O W .C W
WW .1Read: .C .TWTCR6 WW .TCR4 Y. TCR3 .TWTCR2 W 100
Y
M.T
00Y TCR7 M
TCR5
W 100 O M TCR1
W .TCR0
C O
W .CO .TW WW .100Y .
WW .Write: 00Y WW .100Y.C M.TW M .TW
1 M W O W O
WReset: 0O 0 0
WW 0.100Y.C0 M.TW 0 0 WW 0 Y.C .TW
WW .100Y.C M.TW W . 100 O M
W O
W
WW .100Y.C M.TW
O = Unimplemented
WW .100Y.C M.TW WW .100Y.C M.T
W O (TCR) W O
W
WW .100Y.C M.TW
O Figure 9-4. Timer Counter
WW .100Y.C M.TW
Register
WW .100Y.C M
W W .C O
W WW 00Y.CO .TW W WW 00Y.CO
W 00 Y .T W .1
W.1 Y.COM W W W.1 Y.COM W WW
W W 0 0 .T W
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
W
W .100 O M.T
W
W .100 OM
.T
C W .C
M.T .100
Y — Rev. 4.0
W O W W
84 WW .100Multifunction Y.C TW Module W
.Timer MOTOROLA
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW Multifunction Timer Module
M W O Low-Power Modes
0 Y .CO .TW W W 0 0 Y.C . T W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W
W .100
Power-on clears
.T
OM the entire counter W W .1
chain and .C
theOM internal clock begins clocking the
W W
W counter. Y .C
0 After M W
T cycles (or 16 cycles W 0 Y
0if the SOSCD .TW
.T 1 0 4064. .1 M
.C OM W .
Wregister Y .C O
W W
W
Wcircuit 0 Y .CO .TWin the mask option
bit
00 Y .T W W .10 0is set), the
M. T power-on reset .1 0
is released, M clearing the counter again
WW and allowing Y. the MCU .TWto come out W of reset. Y W
. 1 00 M .T W . 100 O M W .100 O M.T
WW 00Y.CO .TW .C function WWcounter .C
WAWtimer.1overflow
00Y M .TW at the eighth .
Y
100stageOallows M .TWa timer interrupt every
. 1 M O W
WW 00Y.CO .TW W WWinternal
1024
0
.C cycles.
0Yclock .TW WW .100Y.C M.TW
. 1 M
W W. 1
.C OM
W 00 Y .T W .1 M
W.1 9.6 Low-Power
OM Modes W.1 . C OM WW 00Y.CO .TW
W . C W W Y W W
W .100
Y
M.T
W
W.and100 M.T
Oinstructions W.in1
C OM
W .C O The STOP
W WAIT
Y .C W put the W W
MCU low 0 Y .
power-consumption W standby
WW .100Y M .TW W
states. W . 100 O M .T W .10 O M.T
W O WW .100Y. C
W O W O
WW 9.6.1
W
0 .CO Mode
YStop .T W WW .100Y.C M.TW WW .100Y.C M.TW
0 O
W.1 OM W Y.hasCO the T WWon the
W
0Y.C M.TW
WW .100Y.C M.TW The STOP WWinstruction 1 0 0 M . W
following effects .1 0 timer:
W. CO W O
W
WW .100Y.C M.TW • Clears
O
WWthe .timer 0 0 Y.counter .T W WW .100Y.C M.TW
W . C O W 1 Y.COM W
Winterrupt WW 00Y.CO .TW
W Y W • W
Clears 0 flags (TOF T and RTIF) W
and interrupt enable bits (TOFE and
W
W .100 O M.T W .10 O M. W W.1 Y.COM W
RTIE)WinW .C
WW .100Y.C M.TW further
TSCR, removing any pending timer W interrupt requests and disabling
. 100
Y
M .TW W .100 O M.T
O timer W interrupts O .C
W
W
W O W O
WW Wait
9.6.2
W
0Y.C M.TW
O
0Mode
W W . 1
.C O
Y W
W 00
W.1 Y.COM The.Ttimer remains active W.1afterYa.CWAIT OM instruction. Any W W.1 timer
enabled .CO
M
interrupt
W W 00 request W
.T can bring the MCU W W
1 0
0out of waitMmode. .T W W .1 0 0 Y
M .TW
. 1 M W . O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W .C O W
W O W O W W .C O
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100
W O W C O W W .COM
.C W Y . W W 0Y
WW .100Y M.T
W W .100 M.T W.1
0
W O W W .C O W
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O Rev. 4.0 W O
W O W W
.Timer 85
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
OM.T
WW .100Y .C W
W O M.T
M WW 00Y.CO .TW
0 Y.CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW WW .100Y. C
. 1 M W O W O
W
0 Y.C
O
. 1 0 M W O W O
.1 M W O W O
W 00 .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100 OM
.T
W O C W .C
WW .100Y.C M.TW W W
1 00Y
.
M .TW W . 100
Y
M .TW
W . O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W .C O W
W O W O W W .C O
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100
W O W C O W W .COM
.C W Y . W W 0Y
WW .100Y M.T
W W .100 M.T W.1
0
W O W W .C O W
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W W
86 Y.C
WW .100Multifunction TW Module W
.Timer MOTOROLA
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW WW .100Y. C
. 1 O M W O W .C O
W
0 Y.C .T W WW .100Y.C M.TW WW .110.
Section 00Y Electrical M.T
W Specifications
. 1 0 M W O W .C O
. 1 M W O W O
W. 1 10.1 OM Maximum Ratings WW 00Y.CO .TW
W 00
W.1 Y.COM W
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Maximum W.1ratings C OM
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Wwhich
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W W 00 .T W W
1 0 Y .
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W
WW .100Y.C MNOTE:
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WW at00the O
W O This device Wis not Yguaranteed
WW operating .CO .TW to operate properly Y.Cmaximum TW
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W 10.5 5.0-V. 1 DC M
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W C O WW 0and .C OM WW Y.C
O
W
W W 0 Y . .T W Characteristics
W 0 Y 10.6 3.3-V
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Electrical 0
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. 1 0 M.T
. 1 0 M W . 1 O M W C O
W O
WW .100Y.CTable WW .100(1) Y. .TW
WW .100Y.C M.TW M TW Maximum
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W O M
W O
W
WW .100Y.C M.TW
O
O
W W Y .C O
W W WW Rating
0 Y .CO .TW Symbol WWW 00Value Y.C .TW
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W 0 0 .T . 1 0 M . 1 O M
W.1 OM Supply Voltage
WW 00Y.CO .TW DD WW
V W –0.3 Y to +7.0
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V
WW .100Y.C M.TW W
Current Drain per Pin .1 M . 1 0
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W W .C O
W(Excluding VW ,W
W
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W 0 0 Y .T DD
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W.1 OM WW 00Y.CO .TWVIn WVW
W .C+O0.3 .TW V
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WW .100Y.C M.Input TW Voltage W SS – 0.31to
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Wto 2 x VY.C+O0.3
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WW .100Y .TW W .10 M.T
W 100 .T
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M W . O M W C O
W O Storage Temperature Range
WW .100Y.C M.T WW Y. .TW°C
WW .100Y.C M.TW
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W –65 to +150
W .100 O M
W O 1. Voltages are referenced W . .CO WW .100Y.C M.TW
WW .100Y.C M.TW WW to V.SS 1 00Y M .TW
W W .C O
Y W
W
10.2 Operating 00
W.1 Temperature OM
.T Range W.1 Y.COM W W W.1 Y.COM W
. C W
W W
.1 00Y M .TW W
W . 100 O M .T W
W .100 O M.T
W O W(TW .C
WW .100Y.C M.TW Package Type WW .100Y.CSymbol M .TW Value L to TH. 1) 00
Y Unit .TW
M
W W .C O W W (4) Y.C O
W W W W
0 Y .CO .TW
Y W P , CDW
(1) (2) W , CS.100
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W .100 M.T
MC68HC705KJ1C A
W C O W W .C OM W W Y.C O
W
W Y . W W 0 0 Y .T W W .1 0 0 M.T
W .1 002. P = plastic
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W . 1 O M W C O
W
WW .103.0Y .CO dual
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W integrated
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Wcircuit (SOIC) 00Y
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W . 1 O M W O
W 4. S = ceramic
WW .100Y.C M.TW
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W O W O
W
WW .100Y.C M.TW
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W O W O
10.3 Thermal Characteristics W
WW .100Y.C M.TW
O
W W .C O
W Y
00 Characteristic .T W 0 0 1 M
W.1 Resistance OM
Symbol
W.1 Y.COM W
Value
W W.Unit Y .CO .TW
W .C W W 0
W Thermal
.100
Y
M .TW W 00
W.1 Y.COM W
.T 0
W.1 Y.COM
W
MC68HC705KJ1P .C O (1)
W W
WWMC68HC705KJ1DW Y W W θJA.100 M.T 60
W °C/W 00 .T
W .100 O M(2).T W .C O W W.1 Y.COM
WW Y.C (3) .TW WW .100Y M.T
W W .100
W .100
MC68HC705KJ1S
O M W W .C O W W Y.COM
W .C Y W W 0
W .10dual
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O M.T W.1
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3.W
W
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W W .100
Y
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W
W O W C O
W O Rev. 4.0 W O
W O W
MOTOROLA WW .100YElectrical .C .TW
Specifications WW 87
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
Electrical SpecificationsM.TW WW .100Y.C M.TW
0 0 .1 M
W 00 .T W
10.4 Power Considerations W.1 Y.COM W W W.1 Y.COM W
W
M .TW W
W . 100 O M .T W
W .100 O M.T
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Y. can .be
. 1 00Y M
WWThe .average1 00Y chip M TW
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W 10J,0in °C O M TWobtained from:
O W O TA + (PD0Y .C
W
00 Y.C .T W WW .100Y.C M.TW TJ W = W
. 1 0 × θ JA )M.TW (1)
. 1 M W O
WW 00Y.CO .TW WW 00Y.CO .TW
Wwhere: WW .100Y.C M.TW
.1 M W. 1 OM W O
WW 00Y.CO .TW WWTA = .ambient 0 0 Y.C temperature .T W in °C WW .100Y.C M.TW
1 M O in °C/W
W.1 Y.COM W WJAW= package
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ambient W
W W
. 100 M .T W
P =
W P. 1 0
0 +P M
O
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W .1 0
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W O D
W INT .C
I/O
WWdissipation Y.C .TW
WW .100Y.C M.TW W PINT = I.CC 1 00×YVCC = M chip .TW internal power W . 100 O M
W O W
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WW .100Y.C M.TW P
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M
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W .pins
1 O M.T
O W O Y. C
W
WW .100Y.C M.TW For most WWapplications, .C
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W . 1 O M W O
W O
WW .100Y.C M.TW Ignoring WW Y.C
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P , .
the1 M P D andW TW J is approximately:O
W W Y .C O
W W
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W 0 Y .CO .TW W 0 0Y.C M.TW
W 0 0 .T 1 0 .1
W.1 OM W. OM PD = -----------------------------------
K
WW 00Y.CO .TW (2)
WW .100Y.C M.TW WW .100Y.C M.T W T + 273
J
W °C .1 M
W O W O
W
WW .100Y.C M.TW
O
W COfor KTgives: W O
W
WW .100Y.C M.TW
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WW (1).10and 0Y.(2) . W WW .100Y.C M.TW
M O
W .C O WW = P00DYx.C (TO A + 273°C) W + ΘJA x (P W DW) W 0 Y.C W (3)
W W
. 1 00 Y
M .T W W
W . 1 O M .T
W .1 0
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W
WW .100Y.C Mwhere
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W . 1 00 M .T . 1 0 M W .1 OM
W O
W
WW .100Y.C M.TW
Oiteratively for any value of T .
WW .1A00Y.C M.TW WW .100Y.C M.TW
W W .C O
W 00 Y .T W .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
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W 00
W.1 Y.COM W
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W O W . C O W
W O W O W W .C O
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
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W O W O
W
WW .100Y.C M.TW
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W O W O
W
WW .100Y.C M.TW
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W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
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WW .100Y M.T
W O W .C O W
W W .100
W O W C O W W .COM
.C W Y . W W 0Y
WW .100Y M.T
W W .100 M.T W.1
0
W O W W .C O W
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W
88 WW .100YElectrical .C .TW
Specifications WW MOTOROLA
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW Electrical Specifications
M W O 5.0-V DC Electrical Characteristics
0 Y .CO .TW W W 0 0 Y.C . T W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
10.5 5.0-V DC Electrical W W.1 Characteristics .C OM
W W
M .TW W
W . 100
Y
O M .T W
W .100 O M.T
.CO .TW WW .100Y. C
00Y WW .100Y.C(1) M.TW M .TW (2)
. 1 M W
Symbol MinO Max Unit
WW 00Y.CO .TW
Characteristic Typ
W
0 Y.CO .TW W WW .100Y.C M.TW
.10 OutputM high voltage .1 M W O
WW 00Y.CO (ILoad =T–2.5 W mA) PA4–PA7 W WW 00Y.CO .TW W WV OH .1 0 0
VY .C–0.8 .TW — — V
. 1 M . W . 1 O M W
DD
O M
W (IO = –5.5 mA) PB2–PB3, PA0–PA3 .C W V Y .C
–0.8 — W —
W 00Y
.C Load .TW WW .100Y M .TW W .100
DD
M.T
WW .100Y.C M.TW
(8)
WW .100Y.(ICLoad =M10.0
Output low voltage
.TW WVOL .100—
Y
M— .TW 0.8 V
W O mA) PA0–PA7, PB2–PB3 W C O W W .C O
Y.Chigh voltage WW .100Y . W Y W
WW .100Input M.T
W
W O M.T
W
W .100 O M.T
W O W × .C
0Y.C M.TW
V 0.7 V — V
WW .100PA0–PA7, Y.C PB2–PB3, .T W IRQ/VPPW W
, RESET, OSC1
1 0
IH
W .1 00DD Y
M .TW DD V
M . W O
W .CO WW 00Y.CO .TW WW V .100Y.C —M.TW
WW .Input 0 0 Ylow voltage W
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W 1 PA0–PA7, C
M
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W OSC1
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W WSS Y.CO W
W . .T=W Y W W 0 0 .T
W
W Supply
Y
.100 current O M
(fOP 2.1 MHz; fOSC = 4.2W
W MHz).100 OM
.T
W W.1 Y.COM W
C
Y. (3) W Y .C W W — .100 4.0 M.T 6.0
WW Run .100mode (4)OM.T
W W .100 M.T mA
WW .C W W Y .C O
W
I DD
W W —
W
0 Y .CO .T2.8
1.0 W mA
W . 1 00Y (5) M.TW
Wait mode W
W . 100 O M .T
— W .10 0.1 OM 5.0
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Stop mode O
W WW .100Y
SupplyW current .(f
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WWRun mode 0 Y
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W . C W W.1 Y.COM IW — WW 5.2 .CO 7.0
Y W mA
W mode0(4)
WWait 0 Y T W W 0 0 .T DD W
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. 1.1 M
W Stop
W
W mode 00Y.C .TW WW .100Y .C
M .TW
— W . 100 M .T µA
. 1 O M W O W W .C O
W WWHi-Z leakage
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WW 00Y.CO .TW
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WW current
Wpulldown 0 Y .CO .TW W WW .100Y.C M.TW
Input 0
W.1 Y(with M .1 M W CO
.COindividual WW 00Y.CO IIL .TW 35 WW80 100Y.200 .TW
µA
WW PB2–PB3
PA0–PA7,
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Input pullup W.1 Y.COM W
Wcurrent WW 00Y.COIIL .TW –15 WW
W
–35 .100Y
.C TW
.µA
W 0 0 .T W . 1 M –85 M
RESET . 1 M W O W O
WW
W
0 Y.C
O
Input current (6)
1 0 0.2WW ±1Y.CO µA W
WW
.
.C OM WW 00Y.CIInO .TW— W 0 .T
RESET, W IRQ/V PP , OSC1 Y W W 0
W .100 O M.T W .1
.C O M W W.1 Y.COM W
CapacitanceWW Y.C W WW .100Y .TW W .100 M.T
Ports (As Inputs orW .100
Outputs) O M.T W COutCOM — — W W 12 .C O pF W
RESET, IRQ,
W OSC2
WOSC1, 00Y
.C .TW WW .100CYIn. M .T—W —
W .8100
Y
M.T
.1 M W O W C O
WW oscillator .CO .internal TW resistor W
W 0Y.C M.TW WW .100Y. .TW
Crystal/ceramicW resonator
. 1 00Y mode M . 1 0
W ROSC O 1.0 W O M
WW .100Y.C M.TW
O 2.0 3.0 MΩ
OSC1 to OSC2(7) WW Y.C W WW .100Y.C M.TW
W .1 0 0 M .T W O
1. VDD = 5.0 Vdc ± 10%, WWVSS =000YVdc, .COTA = –40°C W to +85°C, W WWotherwise
unless 0 CO
Y.noted. T W WW .100Y.C M.TW
W
2. Typical values at midpoint.1of voltage O .T . 1 0 M . O
WW using .C
M 25°C only
range,
WWall inputs Y COV fromTrail;
.0.2 W W WW 0 Y.C W
3. Run mode IDD is W measured
. 1 0 Y external
0OSC2. M. square
T W wave clock Wsource;
W . 1 0 0
O M . no dc loads; less than
W . 50
1 0 pF
O M.T
on all outputs; CL = 20 pF
WWsystem
on
.CO Wait.Tmode W .C
4. Wait mode IDD: only Wtimer 00Y active. W is affected W by0OSC2
Wlinearly . 1 0Y.Ccapacitance. M .TW Wait modeWis measured . 100
Y
M .TW
asW .1 M
O V; VIH = VDD – 0.2 V. Wait W IDDYis.Cmeasured W O W
W wave00Y.C O
with all ports configuredW
W 0.2 V from
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0 0
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Y no dc loads; .T Wless than 50WpFWonmode 1 0 0 CL = M .T
using externalW square
. 1 M .TW
clock source; all inputs . 1 rail; M all .outputs; 20 pF on OSC2. W O
5. Stop mode IDD is measured WW with OSC1 Y .=CVOSS. Stop Wmode IDD is measured
W WW with00allYports .CO configured .T W as inputs;W VILW= 0.2 V; 00Y.C .T
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W .1 0 0
O M .T
W . 1
.C O M W W.1 Y.COM
6. Only input high current W W to +1 µA
rated Y.C
on RESET. TW WW .100Y M.T
W W .100
7. The ROSC value selected for RC W .100 versions
oscillator O M. of this device is unspecified. W W . C O W W Y.COM
WI/O pins0combined Y . C Wnot exceed 100 W mA. .100 Y W W 0 0
8. Maximum current drain for Wall
W .1 0 O M.T
should
W O M.T W W.1
W . C
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O Rev. 4.0 W O
W O W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
0 0 .1 M
W 00 .T W
10.6 3.3-V DC Electrical W.1 Characteristics .C OM W W.1 Y.COM W
W W
M .TW W
W . 100
Y
O M .T W
W .100 O M.T
.CO .TW WW .100Y. C
00Y WW .100Y.C(1) M.TW M .TW (2)
. 1 M W
Symbol O
Min Max Unit
WW 00Y.CO .TW
Characteristic Typ
W
0 Y .CO .TW W WW .100Y.C M.TW
.10 Output M high voltage .1 M W O
WW 00Y.CO (ILoad =T–0.8 W mA) PA4–PA7 W WW 00Y.CO .TW W W V OH .1 0 0
V Y .C–0.3 .TW — — V
. 1 M . W . 1 O M W
DD
O M
W (IO = –1.5 mA) PA0–PA3, PB2–PB3 .C W V Y .C
–0.3 — W —
W .C Load .TW
00YOutputM WW .100Y M .TW W .100
DD
M.T
W . 1 O W O W W .C O
W PA4–PA7WW .100Y.C M.TW
low voltage
WW .100Y.(ICLoad =M5.0 .TmA) WVOL W.10 —
0Y M— .TW
W O= 3.5 mA) PA0–PA3, PB2–PB3 W C O W .C O 0.5 V
W .C W W Y . W W 0 0 Y .T W
W .100
YLoad
(I
M.T
W 00 .T —
W.1 Y.COM W
— 0.5
W .C O W W.1 Y.COM W W
WW .100PA0–PA7, Input Y high voltage
.TW IRQ/V W 00 .T W 0.7.1× 0V0 M.T
M
PB2–PB3, , RESET, W . 1
OSC1 O M VIH
W DDY.CO— VDD V
W W .C O PP W Y .C W W W 0 .T W
Y W W 0 .T 0
W 100 low voltage
W.Input OM
.T 0
W.1 Y.COM W VIL WW VSS 0Y.C —
W.1 OM 0.2 × V
W DD
. C W V
W W
. 1 00Y PB2–PB3,
PA0–PA7,
M .TWIRQ/VPP, RESET, W OSC1
W . 100 O M .T W .10 O M.T
W O W MHz) 00Y.C WW .100Y. C
WW Supply Y.C (fOP .=T1.0
00current W MHz; fOSCW = 2.0
1 M .TW M .TW
. 1 (3)O M W . O W .C O
WW Run
W mode
0 Y.C .T W WW .100Y.C M.TW IDD WW— .100Y1.2 M.T0.8
W
2.5 mA
. 1 0 (4) M W O — W 0.3 . C O mA
WWait
WW Stop.1mode
mode
.CO .TW WW .100Y.C M.TW WW Y
000.1 TW
.5.0
00Y(5) M W O
—
W . 1
.C O M µA
W O
.C 2.1.TMHz; W .C W Y W
W current
WSupply 1 00Y (fOP = M W fOSC = 4.2WMHz) . 100
Y
M .TW W
W .100 O M.T
. O W O . C
WRun WWmode0(3)0Y.C .TW WW .100Y.C M.TIW WW .11.4
— 00Y 3.0.T
M
W mA
. 1 M W O DD W 0.3 0Y.C 1.0
O
Wait W mode(4) .CO — W
WW .1(5) 0 0Y .TW WW .100Y.C M.TW W . 10 M .TW mA µA
M — W 0.1 O5.0
Stop mode
W W Y .C O
I/OW ports hi-z.1 00 current .T .1 M .1 OM
OMindividual pulldown activated) — WWW
leakage
PA0–PA7, W WPB2–PB3 Y . C
(without W W WW 00Y.CO IIL.TW 0.1
1 0 0 Y.C±1 .TW µA
W . 1 00 M .T W . 1 O M W .
.C O M
WW current O W
Input pulldown
W 0 0 Y.C .T W WW .100Y.C IM .TW 12 W 30 .100Y100 OM.TµA W
PA0–PA7, PB2–PB3 . 1 (with M
individual pulldown activated) W O IL
W C
WWcurrent
W .CO .TW WW .100Y.C M.TW WW .100Y. .TW
Input pullup . 1 00Y M W O W –45.C O M
µA W
RESETWWW
O I W
WW .100Y.C IL M.TW
–10
0 Y.C .T W W–25 . 1 00Y M .T
.1 0 M W O W .C O
W O W
Input current(6)
WW , OSC1 Y.C .TW WW .100Y.CIIn M.TW— W 0Y
10±1 .TW
.100 M W O 0.1 W . O µA
M
WW .100Y.C M.TW
RESET, IRQ/VPPW O
W W 0 0 Y.C .T W WW .100Y.C M.TW
Capacitance
W W. 1
.C OM
W WW 00CY.CO .TW W WW 00Y.CO .TW
Ports (as inputs W or 00
outputs) Y .T W .1 pF M
W.1 COut OM — — 12
RESET, IRQ/VPPW W.1 OSC2
, OSC1, . C OM
W W Y . C — W — W WW 8 00Y.CO .TW
W 00Y .T W 00 In .T W.1 Y.COM W
Crystal/ceramic resonator W.1oscillator .C OMinternal resistor
mode W W.1 Y.COM W W
W W 00Y .TW W .R 00
1OSC M1.0.T 2.0 W 3.0 .100 MΩ M.T
OSC1 to OSC2(7) . 1 M W O W C O
W
WW V .1=000YVdc, .CO .TW WW .100Y.C M.TW WW .100Y. M .TW
1. VDD = 3.3 Vdc ± 10%, W T M
= –40°C to +85°C, unless W
otherwise O
noted. W O
2. Typical values atW
SS
W of 0voltage
midpoint 0
OA
Y.C range,.25°C T W only WW .100Y.C M.TW WW .100Y.C M.TW
3. Run mode IDD is measured 1
W.using external OM square wave clock source; Wall inputs 0.2 .CVOfrom .rail; no dc loads; less W 50 pFY.CO
Wthan
on all outputs; CL W W
= 20 pF on OSC2. 00 Y . C
.T W W W
1 0 0 Y
M T W W . 100 M .TW
.1 M . O W O
4. Wait mode IDD: only timer Wsystem active.
YIL.C
OWait mode is affected linearly WWby OSC2 0Yis.C
capacitance.
TW Wait mode is W W
measured
00Y
.C .TW
with all ports configured WWas inputs; . 1 0 0V = 0.2 V;
M V.T W= V – 0.2 WWait
V. mode . 1 0I measuredM . using external square W .
wave 1 O M
W O
WOSC2. WW .100Y.C M.T
IH DD DD
clock source; all inputs 0.2
W WW V from rail;
0 Y CO
.no dc loads;W
T less than 50 pF W W
on all outputs;
0 0 Y.CCL = 20 pF .T on
0 . . 1 M
5. Stop mode IDD is measured with.1 OSC1 = VSS.M
WW 00Y.CO .TW
Stop mode IDD is measured Wwith all portsOconfigured as inputs; VIL =W0.2 WV; .CO
VIH = VDD – 0.2 V. W WW .100Y.C M.TW W 1 00Y
6. Only input high current rated toW +1.1µA on RESET. O M W C O W W .
.COM
forW .C W device is unspecified.W Y . W W 0 0Y
7. The ROSC value selectedW
.100
RC oscillator
W
Y versions of
O M.T
this W
W .100 O M.T W W.1
W .C
WW .100Y.C M.TW W .100
Y
M.T
W W
W O W C O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M W O Driver Characteristics
0 Y .CO .TW W W 0 0 Y.C .T W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
10.7 Driver Characteristics W W.1 Y.COM W W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO 800 WW Y. C
00Y .TW WW .100Y.C M.TW 800 . 100 85°C OM.T
W
W . 1 M
O 700 W
85°C 25°C O W W .C 25°C
0 0 Y.C .T W WW .100Y.C M.TW W700 . 1 00Y M .TW
. 1 M W O W .C O
WW 00Y.CO .TW 600
WW .100Y .C .TW WW .100Y
600
.TW
VDD – VOH (mV)

VDD – VOH (mV)
–40°C
. 1 M
500
W O M 500 W O M
WW 00Y.CO400 .TW WW .100Y.C M.TW WW .100Y.C –40°CM.TW
400
W. 1 M W O
.C O WW 00Y.CO .TW 300WW 0 Y.C W
W M.T
300 W
W 00 Y .T W . 1 M .1 0
. 1 M W O W O
O WW .100Y.C M.TW VDD = 3.3 V
W 200 200
WW .100Y.C100 M.TW WW .100VYDD.C= 5.0 V M.TW
WW 00Y.CO .TW
100
W W Y .C 0
O
W W WW 00Y.CO .TW W
W 00 .T –6 .1 –8 OM–10
0 .1 –4.CO
M –6
W W.1 Y.C0 OM –2W –4
IOH W
(mA)
W
0 Y .C W
0
W WW –2
0 0 Y .TW
–8 –10
W 0 0 .T W .1 0 M .T . 1 I OH (mA)
M
W W.1 Notes: .C OM
W 0 Y .T W 1
W .10 AtM
1. O VDD = 5.0 V, devices are W .1 and tested
specified C OM for (VDD – VOH) ≤ 800 W W.@
mV IOHY =.C OM
–2.5 mA. W
.C W Y . W W 0
W W
.1 0 0 Y 2. At V
MDD .T= W
3.3 V, devices W are specified
W . 1 0 0 and tested
O
.
forT
M DD OH(V – V ) ≤ 300 mV
W @.1 0
I OH = –0.8 M.T
OmA.
W O C W .C W
WW .100Y.C M.Figure TW 10-1. W
W
. 0Y.
10Typical M .TW W .100
Y
M.T
O PA4–PA7 W O High-Side Driver W
Characteristics .C O
W
O W O W .C O
W
WW 800.100Y.C M.TW WW .125°C 00Y
.C TW
.800 WW .100Y85°C M .TW
W M
O 700 W O
W 700
WW 600 .100Y.C M.TW
O
WW .100Y.C M600
85°C .TW WW .100Y.C 25°C M.T
W
W O W O
W O
WW –40°C.100Y.C M WW .100Y.C M.TW
VDD – VOH (mV)
VDD – VOH (mV)
WW500 .100Y.C M.TW 500.TW

O
400W . C O WW 00Y.CO400 .TW W WW 00–40°C Y.C W
W W 00 Y .T W W . 1 M .1 O M.T
300 W.1 M W O W C
W .CO .TW WW .100Y.C 200 M.TW
300
WW .100Y. .TW
W200 . 1 00Y M VW O W O M
.C= 3.3 V .TW
W O WW .100Y
WW .100Y.C100 M.TW
VDD = 5.0 VDD
W100W 0 0 Y.C .T W M
0 WW
.1
.C OM
W WW 00Y.C0O .TW W WW 00Y.CO .TW
W0 00
–2 Y –4 .T –6 –8W –10.1 0 M –2 –4 –6 .1 –8 OM –10
W.1 Y.COM IOH (mA) W W Y .C O
W W
IOH (mA)
W
W
0 Y .C W
W W
1 0 0 M .T W W . 1 0 0 M .T
W . 1 0
O M.T
Notes: W. O W .C O W .C
W W
1. At VDD .=10 0YV,.Cdevices
5.0 TWspecified andWtested for.1(V
.are
W 00DDY– VOH)M .TWmV @ IOH =W
≤ 800 –5.5 mA. . 100
Y
M .TW
M O W O
2. AtW W CO areTspecified
V, .devices WW 0Y COH) ≤ 300TmV
– .V W @ IOH = –1.5 WW 00Y
.C .TW
W VDD =.3.3 1 00Y . W and W tested for (VDD
. 1 0 M . mA.
W . 1 O M
W OM W O
WW .100Y.C M.TW
WW 10-2.
Figure 0 0 Y.C
PA0–PA3 .TandW PB2–PB3 WW Typical . 1 0 0Y.C M.Driver
High-Side TW Characteristics
W.1 OM W O W O
W W .C O
Y W
W
W .100 O M.T W .1
C W W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
O W O W .C O
W
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W .100 O M .T W
W .100
W O WW
W O W O
W O Rev. 4.0 W O
W O W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
0 0 .1 M
W 00 .T W
800 W.1 Y.COM W W W.1 800 Y.COM W
W W 00 .T
M .TW 700 W
W . 100 O M .T W .1700
C O M85°C 25°C
C O W .C W Y . W
00Y
. .TW W 00Y 25°C M.TW
.185°C
W .100 OM
.T
W.1 Y.COM 600 W C O W W 600
.C W
00 W
.T500 WW .100Y. .TW W 500.10
0Y M.T
VOL (mV)
. 1 M M W O
VOL (mV)
W O .C
WW 00Y.CO .T 400W WW .100–40°C Y.C .TW WW 400 .100Y M .T W
–40°C
. 1 M W O M W O
WW 00Y.CO 300 .T W WW .100Y.C M.TW WW300 .100Y.C M.TW
W. 1 OM200 W O
.C WW 00Y.CO .TW W W 0 Y.C W
W M.T
W 200 0
W 00 Y .T W . 1 VDD = 5.0 VOM .1 VDD = 3.3 V
W . 1 M
O 100 W C W W .C O
W .C W W Y . W W 100
0 Y .T W
W .100
Y
M .T W 00
W.1 Y.COM W
.T
0 WW
.10 OM
W .C O 0
W W0 0 Y .C TW 40
WW .100Y M
0 .TW 10 20 W 30
IOL (mA) W.1
0
040 50
M .T W .1100 20 M.30
O
50
W O W .C O W Y .C I (mA)
W
WW .100Y.CNotes:M.TW
OL
Y W W .100 .T
W O
W
WWare specified Y. C 0Y mA. M.TW
WW .100Y.C 1. At M
V.TDDW= 5.0 V, devices . 100 andOtested M .TforW VOL ≤ 800 W mV @ IOL.1
W
= 010.0
O
W OAt V = 3.3 V, devices W W .C tested.T VOL ≤ 500 mV WIOL = 5.0 Y.C
WW .100Y.C MDD
2.
.TW W
are specifiedYand
1 0 0 M
forW W@ .1 0 0mA. M .TW
. O W O
W O WW 00Typical Y.C Low-Side W 00Y
.C W
WW .100Y.C M.T Figure
W 10-3.W PA4–PA7
. 1 M .TW Driver WCharacteristics
W . 1 O M.T
O W O . C
W
WW .100800 Y.C .TW WW .100Y.C M.TW WW .100Y M .TW
M W O W O
W O
WW .100Y.C M.TW700
800 W Y.C .TW
WW .10700 0Y.C M.TW 85°C W85°C
W . 100 O M
W O .C
W
WW .1600 .CO .TW WW .100Y.C M.TW WW .25°C 00Y M.T
W
00Y
25°C
M 600 W 1 O
W O
WW 500
W .CO .TW W–40°CW 00Y
.C W WW .100Y.C M.TW
00Y .T500
VOL (mV)
VOL (mV)
1 .1 M O
.
W400 Y.CO M WW 00Y.CO .T W W WW –40°C
0 Y.C W
W W
. 1 00 M .T W W
W . 1 O M 400
W .1 0
O M.T
W O WW .100Y. C
WW 300 .100Y.C M.TW WW .100Y.C M300 .TW M .TW
W O
W O WW 00Y.CO 200.TW WW .10V0DDY=.C3.3 V M.TW
WW .100Y.C M.TW VDD = 5.0WV
200
.1 M
W
100W
.C O
W WW 00Y.CO 100 .TW W WW 00Y.CO .TW
Y W
W 0 .100
OM
.T W.1 Y.COM 0
W W.1 Y.COM W
0W .C W W W 20 00
W W
.1 00Y
10
IOLM .TW
(mA)
20 W 30
W . 100 O M
0 .T 10
IOL (mA) W.1
30
O M.T
W O WW .100Y .C
W O W O
Notes: WW
0 .CO .TW
Ydevices WWfor V.10≤0Y .C . TW WW .100Y.C M.TW
1. W 0 M
1 WW 00Y.CO .TW
At VDD = 5.0 . V, are
M specified and tested W OL 800 mV O @ IOL = 10.0 mA.
2. AtW WW
VDD Y
= 3.3 V,0devices.CO are specified
.T W and W
tested Wfor V OL ≤0 0 Y
500 .CmV @ IOL.T =W 3.5 mA. W .1 M
0
Figure W
W 10-4. .T PB2–PB3WTypical 0 .T Characteristics W
0PA0–PA3
0 and 0Low-Side
W.1 Y.COM W
Driver .1 M
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
O W O W .C O
W
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100
W O WW
W O W O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W
W O M
W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M W O Typical Supply Currents
0 Y .CO .TW W W 0 0 Y.C .T W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
10.8 Typical Supply W W.1Currents .C OM
W W
M .TW W
W . 100
Y
O M .T W
W .100 O M.T
.CO 7.0 WW .100Y. C
00Y .TmA W WW .100Y.C M.TW M .TW
W . 1 O M W O SEE NOTE 1 W
W .C O
0 0 Y.C .T W WW .100Y.C M.TW W . 1 00Y M.T
W
. 1 M W O W .C O
WW 00Y.CO 6.0 mA .TW WW .100Y.C M.TW WW .100Y M .TW
. 1 M W O W .C O
5.5 V W
W . 1 00Y M .TW
W. 1 OM
5.0 mA
W O W O
SUPPLY CURRENT (IDD)
W O SEE NOTE W2 O WW 00Y.CO .TW

WW .100Y.C 4.0 mA W WW .100Y.C M.TW 4.5 V W
W O M .T
W .C O W W.1 Y.COM W
. C W W
WW .100Y3.0 mA M.TW W
W . 100
Y
O M .T W
W .100 OM
.T
W O C W .C
WW .100Y.C M.TW W W
1 00Y
.
M .TW W . 100
Y
M .TW
W . O W O
W
WW .102.0
O
0YmA.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW
W3.6 V O W O
W
WW .100Y.C M.TW
O
WW 3.0.1V 00Y.C M.TW WW .100Y.C M.TW
W O Notes: WW O
W 1.0 mA O
WW .100Y.C M.TW WW .100Y.C M.TW W At VDD .=105.0
1. 0YV,.Cdevices TWspecified and
M.are
W O W O W
W for IDD .C O
≤ 7.0 mA @ fOP
WW .1000Y.C M.TW WW .100Y.C M.TW Wtested Y
100V, devices
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2.0 MHzWW O 2. At VDDW O are specified and
W 0 O 1.0 MHz .C W for IDD0≤04.25 Y.CmA @ f.OP TW
WW .100Y.C M.INTERNAL
3.0Y
TW OPERATING W . 1 0 0 MHz M
4.0 MHz
.TW W
tested
. 1 M = 2.1 MHz.
O W
FREQUENCY (f ) O W .C O
W
OP
WW .100Y M.T
W
W O W O
W
WW .100Y.C M.TW
O Figure 10-5. Typical Operating I (25°C)
WW .100Y.C M.TW DD WW .100Y.C M.TW
W W .C O
W 00 Y .T W .1 M .1 M
W W.1 Y.COM W WW SEE Y .CO W W WW 00Y.CO .TW
W 00 .T W .10 0 NOTE 1 .T .1 M
W.1 Y.COM W SEE NOTE W W
2 .C OM WW 00Y.CO .TW
W Y W W
W µA
700
W .100 O M.T
W
W .100 5.5 VOM.T W W.1 Y.COM W
C W .C W
WW .100Y.
600 µA M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
O W 4.5 V O W .C O
500 µA W
SUPPLY CURRENT (IDD)
W O
400 µA WW
W
0 Y.C
O
0
W W. 1
.C OM
300 µA W 00 Y .T 3.6 V W .1 M
W.1 Y.COM 3.0WV W W.1 Y.COM W WW 00Y.CO .TW
W W 00 .T W .1
200 µA
W
W .100 O M.T
W
W .100Notes: OM.T W W.1 Y.COM W
100 µA C W .C
Y1. At VDD.T=W
WW .100Y. M.T
W W .100
5.0 V, devices
M for I ≤ 3.25 mA @W W .100 and OM.T
Ware specified
W O W .C O
tested f = 4.0 MHz.Y.C W
0 W W 0 0 Y.C .T W WW .100Y 2. At VDD M . WDD
W OP
=T3.3 V, devices are specified . 1 00and M.T
0 1.0 MHz . 1 2.0 MHz M 3.0 MHz 4.0 W
MHz O W .CO
WW
W .CO .TW WW .100Y.tested C for T
. IDDW≤ 1.75 mA @ WfOPW= 2.1 MHz.
100
Y .TW
.1 00Y M W O M W . O M
WW .100Y.C M.TW
INTERNAL OPERATING OFREQUENCY (f )
W
WW .100Y.C M.TW
OP
WW .100Y.C M.TW
W W Figure .C O Typical Wait Mode
10-6.
W WWIDD0(25°C) Y .CO .TW W WW 00Y.CO .T
W 00 Y .T W 0 .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W .100 O M .T W
W .100
W O WW
W O W O
W O Rev. 4.0 W O
W O W
W O M
W Y . C W
W 00 .T
W W.1 Y.COM
W .100
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
0 0 .1 M
W 00 .T W
10.9 EPROM Programming W.1 Y.CCharacteristicsOM W W.1 Y.COM W
W W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW .C WW Y. C W
00Y WW .100Y Characteristic
M .TW (1) Symbol .100 MinOM.T Typ Max Unit
W . 1 O M W C O W W .C
.C W W Y . W W 0 0 Y .T W
W .100
Y
O M.T
W Programming
W .100 voltage OM
.T
VW W.1 16.0 .C OM 16.5 17.0 V
W Y.C W W W IRQ/V PP 0Y .C T W W PP
0 0 Y .TW
0 0 .T . 1 0 M . . 1 M
W.1 OM WW 00Y .CO .TW WW 00Y.CO .TW
WW .100Y.C M.TW WProgramming .1
current W I W.1 —¦Y.COM3.0 W 10.0
W C O IRQ/V
W WPP .C OM PP
W
mA
W Y . W W 0 0 Y .T W W .1 0 0 .T
W 00 .T W.1 timeY.COM W M
W W.1 Y.COM W Programming
W W WW 00Y.CO .TW
W .100 M.T
W 00 .T W.14 Y.CO—M W —
W.1 Y.COM W
Per array byte tEPGM ms
W W .CO MOR W t W W 4 00 — .T —
Y W W 0 . T
W 00 .T 0 W.1 Y.COM W
MPGM
W.1 Y.COM W W W.1 Y.COM W W 0
W W ± 0 ° W ° .10otherwise .T
W
W .100 O M.T
1. V DD = 5.0 Vdc
W .10 10%, V SS
O
=
M.T A
0 Vdc, T = – 40 C to +85
W
C, unless
W . C OM
noted.
WW .100Y. C Y W
W .100 O M.T
W O C
W
10.10 Control
WW .100Y.C M.TW
O Timing WW .100Y.C M.TW WW .100Y. M .TW
W Table 10-2. O Control Timing (V W .C O (1)
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WWDD =.15.0 00Y
Vdc)
M.T
W
W O W O W W .C O
WW Characteristic .C YMin .TW Unit
WW .100Y.C M.TW WSymbol Max
. 1 00Y M .TW W . 100 O M
W O
W O
WW .100Y.C M.TWCrystal oscillator
Oscillator frequency
WW option 00Y
. 1 M fOSC W — CO 8.0 MHz
W W Y .C O
W External clock W WW 00Y.CO .TW
source W W 0 0
dcY. 8.0. T W
W 00 .T W.1 (f Y.C OM .1 M
W W.1 Y.COM Internal W operating W
frequency ÷ 2) W W WW 00Y.CO .TW
W 0OSC .T .1
W
W .100 O M.TCrystal oscillator WW.10 C OM fOP WW — .C O4.0M
MHz
WW .100Y .C
. T W clock W 1 0 0 Y .
M .T W W . 1
dc 0 0Y
4.0 M .TW
OM
External . W O
W WW 00Y.CO .TW WW 250 0Y.C— M.TW
WW .100Y.C Cycle .T Wtime (1 ÷ fOP)W .1 0
W.1 Y.COM W
t ns
W W .C OM W
cyc
W W W
0 Y .CO .TW
Y RESET W W 0 .T 0
W
W .100 O M.T pulse width low WW.10 .C OM tRL
W W.1 Y—.COM tcyc W
1.5
WW .100Y. IRQM C W
.TW pulse width
interrupt
Wlow .100Y
W O M.T
W
W .100 OMtcyc
.T
W O C t W 1.5 — .C W
WW .100Y.C (edge-triggered) .TW WW .100Y. M .TW
ILIH
W .100
Y
M.T
W O M W O W W . CO
WW .100Y.IRQ C interrupt
.TW pulse width low WW .100Y.C M.TW tILIL W1.5 . 00Y
1Note (2) M
tcyc .TW
M W O W O
WW .100Y.C M.TW
(edge- and level-triggered)
W
WW .100Y .CO .TW WW .100Y.C M.TW
W PA0–PA3
. C OM Interrupt pulse width
WW 00Y.CO .TW
high
tIHIL 1.5
W WW —00Y.CtO W
W Y W M.T
W cyc
W . 1 00 (edge-triggered)
M .T W .1 O M W .1 O
W O W .C WW .(2) Y. C W
WW .10PA0–PA3 0Y.C interrupt M .TWpulse width W W.100Y OM.TtIHIH W
1.5 W
Note
100 tcyc OM.T
W (edge- and
WW .100Y.C M.TW
O level-triggered)
W O t , tOL W O
W OSC1 pulseOwidth
WW .100Y.C OH W 100 WW— .100ns Y.C .TW
WW .100Y.C M.TW M .T
W OM
W–40°C toY+85 O
W1. VDD =Y5.0
WW 2. .The .COVdc ± .10%, V = 0 Vdc, W
TWtILILSSor tILIH should W TA =not 0 .Cthan
0more
°C, unlessW otherwise noted.
.Tnumber of cycles WW .100Y.C M.TW
1 00maximumMwidth . 1
be M the it takes
W to Y.CO
W executeY.the C Ointerrupt service routine plus WW .CO W Wbe .TW
W W
. 1 00
re-entered. M .T W W 19 tcyc 0
. 1 0 orYthe interrupt
M .T service routineW will
W . 100 O M
W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100
W O WW
W O W O
W O W O
.TW WW .100Y.C — Rev. 4.0
W O W
94 WW .100Y .C
ElectricalM .TW
W W .C O
W 00 Y .T W
W W.1 Y.COM
W .100
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T
M W O Control Timing
0 Y .CO .TW W W 0 0 Y.C . T W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1Timing OM = 3.3 Vdc)(1)
W W.1 Y.COM Table W 10-3. Control W 0 Y .C(V DD .TW
.TW W .10
M
W
W . 100 O M .T W C O M
.CO W Y .C W
Characteristic W W 0Y . Symbol.TW Min Max Unit
00 Y .T W W .10 0 M. T .1 0
W.1 Y.COM W W C O W W . C OM
WWOscillator Y. .TW Y W
.100 fOSC
frequency W
. 1 00 M .T .
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W 100oscillator O M
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WW 00Y.CO .TW .Csource.TW W Y .C W
WWExternal 0 0 Y
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.1 M W.1 Y.COM W WW 00Y.CO .TW
WW 00Y.CO .TW W W
Internal 00
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W .1 O M W.1oscillator .C OM W W.1 fYOP.COM — W 2.1 MHz
.C W
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0Y W W 00 T
WW .100Y .T W WExternal.1clock 0 M .T
W . 1 O M .dc 2.1
W OM WW 00Y.CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW W
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W W .C O
W WW 00Y.CO .TW W WW 0cyc0Y.CO 476.TW — ns
W 00 Y .T W .1 M
W.1 Y.COM W RESET pulse
W W.1width Y low OM
. C W WW tRL00Y.CO1.5 .TW — tcyc
W W 0 .T W 1
W 00
W.1 Y.COM W IRQ
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M
W W W 0 Y .C T W W 0 0Y 1.5
.TW— tcyc
W 0 0 .T (edge-triggered)
. 1 0 M . . 1 O M
W.1 OM W .CO W
WW t .100Y.C1.5 M.TW (2)
WW .100Y.C M.TW IRQ interrupt WWpulse.1width 00Y low M.TW tcyc
W W . CO (edge- andW W
level-triggered)
Y . C O
W W W WILIL
0 Y .CO Note .T W
Y W W .100width high .T 0
W
W .100 O M.T PA0–PA3 interrupt W pulse .C OM W W.1 Y.COM W
C W .TW
WW .100Y. 00Y W IHIL .100
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W . 1 O M W O M
W
WW .100Y.C M.TW
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M tIHIH W 1.5 CONote(2) t
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W W WW 00Y.CO .TW
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W W.1 Y.COM OSC1 W pulse width WW Y . C W tOHW , tOLWW 20000Y.CO— .TW ns
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W W 0 Y .C plus 19.Ttcyc W or the W
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.T 0
W
W W
. 1 00 M .TW W
W .100 O M .T W
W .100 O M.T
W O WW .100Y. C
W O W O
W
WW .100Y.C M.TW
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WW .100Y tILIL.C
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W W Y. CIRQOPIN
W tILIH
W WW 00Y.CO .TW W
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W
W .100 O M.T
W
W .100 OM
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W W.1 Y.COM W
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W ILIH .100Y .C W W 00 .T
WW .100Y . 1 M.TW IRQ t
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W O W W .C O W
WW .100Y..C M.TW Y W W .100 .T
.
W O
W
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WW .100IRQ M .TW M .TW W
W .100 O M.T
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W
WW .100Y.C M.TW
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W IRQY.CO
WW (INTERNAL) 0 .T W WW .100Y.C M.TW WW .100Y.C M.TW
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10-7. W
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W W
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W . 100
Y
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W .100 O M.T
W O WW .100Y .C
W O W C O W W .C OM
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WW .100Y.C M.TW M.T
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W .100 OM
WW .100Y . W Y W W 0 0
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W .100 O M.T W W.1
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WW .100Y.C M.TW W .100
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W W
W O W C O
W O Rev. 4.0 W O
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W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
0Y.C W
W . 1 0
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WW .100Y .C W
W O M.T
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W 00 .T W
W
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W . 100 O M .T W
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O
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WW 00Y.CO .TW WWtILIH .100Y.C M.TW WW .100Y.C M.TW
W W.1 Y.COM IRQW (NOTE 2) WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 .T W .1 M
W.1 Y.COM W W W.1 Y.COSCILLATOR OM
W STABILIZATION DELAY W(5)W 00Y.CO .TW
W W 00 .T W
W
W .100 O MIRQ.T(NOTE 3) W.1 Y.COM W W W.1 Y.COM W
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WW .100Y M .TW W
W . 100 O M .T W
W .100 OM
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WW .100Y.C M.TW W W
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W
WW .100Y.C MCLOCK
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W O W O
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WW .100Y.C M.TW
O
W O W .CO 07FE WW
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WW .100YADDRESS .CINTERNALBUS.TW WW .100(NOTE 07FE
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W . 07FE
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W
O W O W O
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W
WW .100Y.C M.TW WW .100Y.C M.TW WW .1RESET 0YOR
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W
WW .1Notes: .CO .TW WW .100Y.C M.TW WW .100Y.C M.TW
00Y W O
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WW .100Y.C M.TW
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W W 3. Edge- .Cand
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W
W .100 O M.T
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W .100 OM
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W W.1 Y.COM W
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WW .100Y. M.T
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WW VDD.100Y.C (NOTE 1).T
W WW .100Y. M .TW W .100
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W
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WW .100Y M .TW
W . 1 O M W O
W WPIN
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W
0 Y.C
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W W. 1
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W 00 Y .T W .1 M
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W
W .100 O M.T
W
W .100 OM
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W W.1 Y.COM W
C W .C TW
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M.07FE 07FE
W 07FE .100Y07FE M.07FE 07FE
W
W
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WW .100Y.C M.TW WW .100Y. M .TW W .100
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WW 00Y.CO .TW WW .100Y.C M.TW NEW W NEW .100Y
W
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W .1 O M W O W W .CO
WW .100Y.C M.TW WW .100Y.C M.TW PCH WPCL .100Y .TW
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W
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W W.1 Y.COM W W 0 W WW
W 00 10-9. Power-On
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W
W
W .100 O M.T
W
W .100 OM
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C W .C
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Y — Rev. 4.0
W O W
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W Y .C W
W 00 .T
W W.1 Y.COM
W .100
O
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M W O Control Timing
0 Y .CO .TW W W 0 0 Y.C .T W
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W W.1 Y.COM W W
M .TW INTERNAL CLOCK
W
W . 100 O M .T W
W .100 O M.T
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. 1 M W O
W Y.C
O
WINTERNAL WW .100Y07FE
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M ADDRESS BUS M 07FE 07FE W
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W O
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WW 00Y.CO .TINTERNAL
M W O W
WWNEW .100Y .CO .TW
W WW .100Y.C M.TW NEW OM OP
W .1 O M DATA BUS W W .C O W W Y.C DUMMY W CODE
W Y.C W W 0 Y .T W W PCH
0 PCL
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W 00 .T 0
W.1 Y.COM W .1 M
W .100 M.T
W t 00 .T W.1 Y.COM W
W.1 Y.COM W
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W . C O W W
WW .100Y M .TW W
W . 100 O M .T W
W .100 OM
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W O C W .C
WW .100Y .C
NOTES:
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1 00Y
.
M .TW W . 100
Y
M .TW
M
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WW .100Y
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W
WW .100Y.C M.TW
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W . 1 O M W O
W
WW .100Y.C M.TW
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W W .C O
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W W 00 .T W
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WW .100Y.C M.TW
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W W .100
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WW 11.
Section Y.C
0Ordering TW Information WW and Y.C
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. 1 0 0 M .T W
W . 1 0
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W. 1 11.1 OM Introduction WW 00Y.CO .TW
W Y .C W W WW 00Y.CO .TW W 1
W 00 .T W.1 Y.COMthe RC W.low-speed .COoption
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W 0 .T in WAppendix .1 0 A. MC68HRC705KJ1 .T and Appendix . 1 B. MC68HLC705KJ1
M are
W .10 O M W W .C OM W W Y .C O
W
WW .100Y .C W available in these Y packages: W W 0 0 .T
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W
W . C
WW .100Y.C M.TW • W648 — Plastic
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W OM
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W O W C O W .C W
WW .100Y.C M.TW • W 751GW — Small Y. outline.Tintegrated W circuit
W (SOIC) .100
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W . 100 O M W C O
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WW .100Y.C M.TW
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WWcontains .CO .TW WW .C
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WW .100Y.C M.TWThis section . 1 00Y ordering M information and mechanical
W . 1 O M.T for the
W C O W W . C O W Y . C W
WW .100Y. available
W package types. Y W W 00 .T
W O M.T
W
WW .100Y .C
WW .100Y.C M.TW M.T
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W
W O W O
W
WW .100Y.C MTable
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W .C O WW 00Y.CO .TW W W(1) 0 Y.C W
W W
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W Table
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O M.T
W O WW .100Y. C
WW .100Y.C M .TW WW .100Y.C M.TW M .TW
W O
W O Package Case
WW Count
W Pin
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WW .Order .C
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WW .100Y.C MType .TW Outline
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W W .C O PDIP WW16 00Y.CO–40 to W W W W
0Y .CO(2) .TW
Y W 648 W .T +85°C 0
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W.1 Y.COSOIC M.T W.1 Y.COM W W W.1 Y.COM (3) TW
W W W 00
W .1 0 0 M .T W 751G W 16
W . 1 0 0 –40
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W . 1 O M.
W C O W .C W Y .C W
WW .100Y. Cerdip .TW
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M .TW 620A W 16W.100Y –40OtoM+85°C W .100
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W
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WW .104.0Y W W 0 0 .T
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WW 00Y.CO .TW
W Y W W 0 .T W
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W .100 O M.T W .1 0
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WW .100Y. M.T
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WW .100Y.C M.TW
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W W 00 .T W
W
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WW .100Y M .TW W
W .100 O M .T W
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W O Rev. 4.0 W O
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WOrdering 00Y
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MOTOROLA
W .1Information
O
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M Mechanical Specifications 99
W Y .C W
W 00 .T
W W.1 Y.COM
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WW .100Y .C W
W O M.T
TW WWSpecifications Y.C .TW
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W O
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W
WCaseY#648 .CO .TW W WW 00Y.CO .TW
W 0
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.C W W
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Y
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W .100 NOTES: 1. O
M.T
W.1 Y.COM W W
–A–
W C O W . C DIMENSIONING AND TOLERANCING PER ANSI
W
00 .T16 WW .100Y. M .TW W Y Y14.5M, 1982.
.100 2.3. CONTROLLING M.T DIMENSION: INCH.
W . 1 O M 9W
C O W W . C O
. TW
DIMENSION L TO CENTER OF LEADS WHEN
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0 FORMEDM .
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W.1 Y.COM 1 W W W. .C OM WW 005.Y.ROUNDED
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DIMENSION B DOES NOT INCLUDE MOLD FLASH.
W
W W 0 . T W 8
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INCHES MILLIMETERS
W Y .C W W
F WW 00Y.CO .TW W W 0 0 YDIM.C MIN MAX .T WMIN MAX
W 00 .T W.1 Y.COM W
C L .1 A 0.740M0.770
O 0.270 18.80 19.55
W W.1 Y.COM W W 0 W WW 00YBC .C0.250 .T W 6.35 6.85

W 0 .T W S
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M W W D
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W 1.77
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W Y.C W W 0 Y .T W W 0 0 0.70
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W W.1 Y.COM W W W WW 0HJ 0Y0.008 CO

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MC68HRC705KJ1 WW 103
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WW 00Y.CO .TW WW .100Y.C 1-800-521-6274 .TW or 480-768-2130 WW .100Y M .TW
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O

DATA DIRECTION REGISTER B

W.1 Y.COM W WW 00Y.CO .TW

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