Tema01Operacional PDF

20/11/2015
Operational Amplifiers and Applications 1 de 24
Grado en Ingeniería Electrónica
Industrial y Automática
Electrónica Analógica
(507103006)
Unidad 1
Operational Amplifiers and Applications
juan.suardiaz@upct.es
20/11/2015 1
Juan Suardíaz Muro Electrónica Analógica
Departamento de Tecnología Electrónica
Chapter Goals
Understand the “magic” of negative feedback and the
characteristics of ideal op amps.
Understand the conditions for non‐ideal op amp behavior so they
can be avoided in circuit design.
Demonstrate circuit analysis techniques for ideal op amps.
Characterize inverting, non‐inverting, summing and
instrumentation amplifiers, voltage follower and first order filters.
Learn the factors involved in circuit design using op amps.
Find the gain characteristics of cascaded amplifiers.
Special Applications: The inverted ladder DAC and successive
approximation ADC
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• Operational Amplifiers are represented both
schematically and realistically below:
– Active component!
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IC Product
OFFSET OUTPUT A 1 8 V+
NULL
1 8 N.C.
-IN 2 7 V+ -IN A 2  7 OUTPUT B


+ -IN B
+IN 3 6 OUTPUT
+IN A 3  6
+
OFFSET V 4 + 5 +IN B
V 4 5 NULL
DIP-741 Dual op-amp 1458 device
Background
• Originally invented in early 1940s using vacuum tube
technology
– Initial purpose was to execute math operations in analog
electronic calculating machines
• Shrunk in size with invention of transistor
• Most now made on integrated circuit (IC)
– Only most demanding applications use discrete components
• Huge variety of applications, low cost, and ease of
mass production make them extremely popular
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Single-ended Amplifier
• Differential Amplifier
– Amplifies difference
between inputs
• Output gain high
– A ~= 106
• Tiny difference in the input
voltages result in a very
large output voltage
– Output limited by supply
voltages
• Comparator
– If V+>V‐, Vout = HVS
– If V+<V‐, Vout = LVS
– If V+=V‐, Vout = 0V
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Single‐Ended Input
+
V o • + terminal : Source
~ Vi • – terminal : Ground
 • 0o phase change
+
V
o
• + terminal : Ground
• – terminal : Source

• 180o phase change
~ Vi
Double‐Ended Input
• Differential input
V +
d V o
• V d  V  V
~
 • 0o phase shift change
between Vo and Vd
+ Qu: What Vo should be if,

V o
~ V1 V 2

~ V2 V 1
Ans: (A or B) ?
(A) (B)
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Distortion
+V =+5V cc
+5V
+
V o
V d 0

5V
V =5V cc
The output voltage never excess the DC

voltage supply of the Op-Amp
Differential Amplifier Model: Basic
Represented by:
A = open‐circuit voltage gain
vid = (v+‐v‐) = differential input signal
voltage
Rid = amplifier input resistance
Ro = amplifier output resistance
The signal developed at the amplifier
output is in phase with the voltage
applied at the + input (non‐inverting)
terminal and 180° out of phase with that
applied at the ‐ input (inverting) terminal.
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3‐stage Op‐Amp
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Why are they useful?
• Sensor signals are often too weak or too noisy
– Op Amps ideally increase the signal amplitude
without affecting its other properties
• Negative feedback leads to stable equilibrium
• Voltage follower (direct feedback)
– If Vout = V‐ , then Vout ~ V+
Closed Loop Transfer Function
H(s) = A / (1 + AF)
When AF >> 1…
H(s) = 1 / F
Where: A = Op Amp Open Loop Gain
F = Feedback Loop Gain
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Ideal Operational Amplifier
• The “ideal” op amp is a special case of the ideal differential amplifier
with infinite gain, infinite Rid and zero Ro .
v
v  o lim v  0
id A and A   id
• If A is infinite, vid is zero for any finite output voltage.
• Infinite input resistance Rid forces input currents i+ and i‐ to be zero.
• The ideal op amp operates with the following assumptions:
• It has infinite common‐mode rejection, power supply rejection,
open‐loop bandwidth, output voltage range, output current
capability and slew rate
• It also has zero output resistance, input‐bias currents, input‐offset
current, and input‐offset voltage.
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Comparator
V1
Vout
V2
Pulse Width Modulator
• Output changes when
– Vin ~= Vpot
• Potentiometer used to vary
duty cycle
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The Inverting Amplifier: Configuration
• The positive input is grounded.
• A “feedback network” composed of resistors R1 and R2 is connected
between the inverting input, signal source and amplifier output node,
respectively.
Inverting Amplifier:Voltage Gain
• The negative voltage gain implies
that there is a 1800 phase shift
between both dc and sinusoidal
input and output signals.
• The gain magnitude can be
greater than 1 if R2 > R1
• The gain magnitude can be less
than 1 if R1 > R2
vs  isR  i R  vo  0 • The inverting input of the op amp
1 2 2 is at ground potential (although it
But is= i2 and v‐ = 0 (since vid= v+ ‐ v‐= 0) is not connected directly to
ground) and is said to be at
v v R
is  s and Av  o   2 virtual ground.
R vs R
1 1
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Inverting Amplifier: Input and Output
Resistances
Rout is found by applying a test current
(or voltage) source to the amplifier
output and determining the voltage (or
current) after turning off all
independent sources. Hence, vs = 0
vx  i R  i R
2 2 1 1
But i1=i2
v x  i ( R  R )
1 2 1
v
R  s  R since v  0 Since v‐ = 0, i1=0. Therefore vx = 0
in i 1
s irrespective of the value of ix .
Rout  0
Inverting Amplifier: Example
• Problem: Design an inverting amplifier
• Given Data: Av= 20 dB, Rin = 20k,
• Assumptions: Ideal op amp
• Analysis: Input resistance is controlled by R1 and voltage gain is set by
R2 / R1.
AvdB 20log Av ,  Av 1040dB/20dB 100
and Av = ‐100
10 
A minus sign is added since the amplifier is inverting.
R  R  20k
1 in
R
Av  2  R 100R  2M
R 2 1
1
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The Non‐inverting Amplifier:
Configuration
• The input signal is applied to the non-inverting input terminal.

• A portion of the output signal is fed back to the negative input
terminal.
• Analysis is done by relating the voltage at v1 to input voltage vs and
output voltage vo .
Non‐inverting Amplifier: Voltage Gain, Input
Resistance and Output Resistance
R vs  v  v
Since i‐=0 v  vo 1 and id 1
1 R R
1 2
But vid =0 vs  v
1
R R
vo  vs 1 2
R
1
v o R1  R2 R
 Av    1 2
vs R R
1 1
vs
R  
in i
Since i+=0 
Rout is found by applying a test current source to the amplifier output
after setting vs = 0. It is identical to the output resistance of the inverting
amplifier i.e. Rout = 0.
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Non‐inverting Amplifier: Example
• Problem: Determine the output voltage and current for the given non‐
inverting amplifier.
• Given Data: R1= 3k, R2 = 43k, vs= +0.1 V
• Assumptions: Ideal op amp
• Analysis: R 43k
Av 1 2 1 15.3
R 3k
1
vo  Av vs (15.3)(0.1V)1.53V
Since i‐=0, vo 1.53V
io    33.3A
R  R 43k  3k
2 1
Finite Open‐loop Gain and Gain Error
vo  Av  A(vs  v )  A(vs  vo)
id 1
vo A
Av  
v s 1  A
A is called loop gain.
For A >>1,
1 R
Av  1 2
 R
R 1
v  1 v  v This is the “ideal” voltage gain of
1 R R o o
1 2 the amplifier. If A is not >>1,
R there will be “Gain Error”.
 1 is called the
R R feedback factor.
1 2
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Gain Error
• Gain Error is given by
GE = (ideal gain) ‐ (actual gain)
For the non‐inverting amplifier,
1 A 1
GE   
 1 A  (1 A )
• Gain error is also expressed as a fractional or
1 A
percentage error.  1 A 1 1
FGE   
1 1 A A

1
PGE  100%
A
Gain Error: Example
• Problem: Find ideal and actual gain and gain error in percent
• Given data: Closed‐loop gain of 100,000, open‐loop gain of 1,000,000.
• Approach: The amplifier is designed to give ideal gain and deviations
from the ideal case have to be determined. Hence,
.  1
10 5
Note: R1 and R2 aren’t designed to compensate for the finite open‐
loop gain of the amplifier.
• Analysis: A 10 6
Av    9.09x104
1 A 10 6
1
10 5
10 9.09x10 4
5
PGE 100% 9.09%
10 5
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Output Voltage and Current Limits
Practical op amps have limited
output voltage and current
ranges.
Voltage: Usually limited to a few
volts less than power supply span.
Current: Limited by additional
circuits (to limit power dissipation v vo v
io  i  i  o   o
or protect against accidental short L F R R R R
circuits). L 2 1 EQ
R  R (R  R )
The current limit is frequently EQ L 1 2
specified in terms of the
minimum load resistance that the For the inverting amplifier,
amplifier can drive with a given R R R
output voltage swing. Eg: i  5V 10mA EQ L 2
o 500
Example PSpice Simulations of
Non‐inverting Amplifier Circuits
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The Unity‐gain Amplifier or “Buffer”
• This is a special case of the non‐inverting amplifier, which is also called
a voltage follower, with infinite R1 and zero R2. Hence Av = 1.
• It provides an excellent impedance‐level transformation while
maintaining the signal voltage level.
• The “ideal” buffer does not require any input current and can drive any
desired load resistance without loss of signal voltage.
• Such a buffer is used in many sensor and data acquisition system
applications.
The Summing Amplifier
Since i‐=0, i3= i1 + i2,
R R
vo   3 v  3 v
R 1 R 2
1 2
• Scale factors for the 2 inputs
can be independently adjusted
by the proper choice of R2 and
R1.
• Any number of inputs can be
connected to a summing
Since the negative amplifier junction through extra
input is at virtual ground, resistors.
v v • This circuit can be used as a
i  1 i  2 i   vo
1 R 2 R simple digital‐to‐analog
1 2 3 R
3 converter. This will be
illustrated in more detail, later.
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The Difference Amplifier
R
Since v‐= v+ vo   2 (v  v )
R 1 2
1
For R2= R1 vo  (v v )
1 2
• This circuit is also called a
differential amplifier, since it
amplifies the difference between
the input signals.
v o  v-  i R  v-  i R • Rin2 is series combination of R1
2 2 1 2 and R2 because i+ is zero.
 
R R R  R
 v-  2 ( v  v- )   1
 2 v-  2 v • For v2=0, Rin1= R1, as the circuit
R 1 

R  R 1 reduces to an inverting amplifier.
1  1  1 • For general case, i1 is a function of
R both v1 and v2.
Also, v  2 v
R R 2
1 2
Difference Amplifier: Example
• Problem: Determine vo
• Given Data: R1= 10k, R2 =100k, v1=5 V, v2=3 V
• Assumptions: Ideal op amp. Hence, v‐= v+ and i‐= i+= 0.
• Analysis: Using dc values,
R 100k
A  2   10
dm R 10k
1
 
Vo  A V V 10(5 3)
dm 1 2 
Vo  20.0 V
Here Adm is called the “differential mode voltage gain” of the difference amplifier.
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Measuring current
• Current (I) better than voltage (V) for measurement
– Voltage suffers losses due to resistances in path
– Low impedance is better for resisting noise
• So how do we generate a constant current source?
– Transconductance Amplifier
Transconductance Amp
• Precision 250Ω resistor
• 1V / 250 Ω = 4mA
• 5V / 250 Ω = 20mA
• RLoad doesn’t matter, just
as long as op‐amp has
www.allaboutcircuits.com
high enough voltage rails
Uses:
- In: Sensors (temp, pressure, etc),
- Out : Radios (Variable Freq Osc)
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Slew Rate
 Linear RC Step Response: the slope of the step response is

proportional to the final value of the output, that is, if we
apply a larger input step, the output rises more rapidly.
 If Vin doubles, the output signal doubles at every point,
therefore a twofold increase in the slope.
 But the problem in real OpAmp is that this slope can not
exceed a certain limit.
Slewing in Op Amp
Output resistant
of OpAmp
In the above case, if input is too large, output of the OpAmp

can not change than the limit, causing a ramp waveform.
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Nonlinear Limitations
Another nonlinear limitation is limited rate of change of the output
signal known as the slew-rate limit SR
dvo Using slew rate we can find
 SR
dt maximum frequency known
as full-power bandwidth.
Assuming
vo t   Vom sin  t 
  Vom cos t  
dvo
dt
 2 f Vom  SR
So the full-power bandwidth
SR
f FP 
2 Vom
Dc offset values
There are three dc offset values related to op-amp design:
1) Bias currents IB+, IB- – related to differential inputs
2) Offset current – ideally zero value
3) Offset voltage – results in nonzero output for zero input
They can be represented as additional dc sources in the
op-amp model
I  I B
I B  B
2
I off  I B   I B 
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Finite Common‐Mode Rejection Ratio (CMRR)
A(or Adm) = differential‐mode gain
Acm = common‐mode gain
vid = differential‐mode input voltage
vic = common‐mode input voltage
v v
v  v  id v  v  id
1 ic 2 2 ic 2
A real amplifier responds to signal An ideal amplifier has Acm = 0, but for a
common to both inputs, called the real amplifier,
common‐mode input voltage (vic).  
 A v   v 
In general, vo  A v  cm ic  A v  ic 
dm id A dm  id CMRR 
v  v  
 dm 
vo  A (v v ) Acm 1 2 
dm 1 2  2  A
 CMRR  dm
vo  A (v ) Acm(v ) Acm
dm id ic
and CMRR(dB) 20log (CMRR)
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Finite Common‐Mode Rejection Ratio:
Example
• Problem: Find output voltage error introduced by finite CMRR.
• Given Data: Adm= 2500, CMRR = 80 dB, v1 = 5.001 V, v2 = 4.999 V
• Assumptions: Op amp is ideal, except for CMRR. Here, a CMRR in dB of 80 dB
corresponds to a CMRR of 104.
• Analysis:
v  5.001V 4.999V
id
v  5.001V 4.999V  5.000V
ic 2
 v   
vo  A v  ic  25000.002 5.000 V 6.25V
dm id CMRR   104 
In the "ideal" case, vo  A v  5.00 V
dm id
6.255.00
% output error  100% 25%
5.00
The output error introduced by finite CMRR is 25% of the expected ideal output.
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uA741 CMRR Test: Differential Gain
Differential Gain Adm = 5 V/5 mV = 1000
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uA741 CMRR Test: Common Mode
Gain
Common Mode Gain Acm = 160 mV/5 V = .032
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CMRR Calculation for uA741
Adm 1000
CMRR   3.125x104
Acm .032
CMRR(dB) 20log10 CMRR  89.9 dB
Instrumentation Amplifier
R
vo   4 (va  v )
R b
3
va  iR  i(2R )  iR  v
2 1 2 b
v v
NOTE
i 1 2
2R
1
R  R 
vo   4 1 2 (v  v )
R  R  1 2
3 1
Combines 2 non‐inverting amplifiers Ideal input resistance is infinite
with the difference amplifier to because input current to both op
provide higher gain and higher input amps is zero. The CMRR is
resistance. determined only by Op Amp 3.
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Instrumentation Amplifier: Example
• Problem: Determine Vo
• Given Data: R1 = 15 k, R2 = 150 k, R3 = 15 kR4 = 30 k V1 = 2.5 V,
V2 = 2.25 V
• Assumptions: Ideal op amp. Hence, v-= v+ and i-= i+= 0.
• Analysis: Using dc values,
 
R  R  30k 150k 
A   4 1 2  1

 22

dm R  R  15k  15k 
3  1 
Vo  A (V V )22(2.5 2.25)5.50V
dm 1 2
The Active Low‐pass Filter
Use a phasor approach to gain analysis of
this inverting amplifier. Let s = j.
v˜ ( j ) Z2( j )
Av  o  Z j  R
v˜( j ) Z ( j ) 1 1
1
1
R R
2 jC 2
Z ( j ) 
2 1  1
R  j CR
2
2 jC
R 1 R e j
Av   2  2
R (1 jCR ) R (1 j )
1 2 1 c
c  2f c  1  fc  1
RC 2R C
2 2
fc is called the high frequency “cutoff” of
the low‐pass filter.
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Active Low‐pass Filter (continued)
• At frequencies below fc (fH in the
figure), the amplifier is an
inverting amplifier with gain set
by the ratio of resistors R2 and R1.
• At frequencies above fc, the
amplifier response “rolls off” at ‐
20dB/decade.
• Notice that cutoff frequency and
gain can be independently set.
 
   
R  j  R 

j 
 R j[ tan1( / c )]
e
  e
Av  2    2   2 e
R (1 j )
 
 2  jtan
 1( / )   2
1 
c

2    
e
c    
 R 1 
   R 1   magnitude phase
1  
  1  
 
 c   c 
Active Low‐pass Filter: Example
• Problem: Design an active low‐pass filter
• Given Data: Av= 40 dB, Rin= 5 k, fH = 2 kHz
• Assumptions: Ideal op amp, specified gain represents the desired low‐
frequency gain.
• Analysis:
Av  1040dB / 20dB  100
Input resistance is controlled by R 1 and voltage gain is set by R2 / R1.
The cutoff frequency is then set by C.
R
R  R  5k andAv  2  R 100R  500k
1 in R 2 1
1
C 1  1 159pF
2f R 2 (2kHz)(500k)
H 2
The closest standard capacitor value of 160 pF lowers cutoff frequency to
1.99 kHz.
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Low‐pass Filter Example PSpice Simulation

Output Voltage Amplitude in dB
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Output Voltage Amplitude in Volts (V) and Phase in Degrees (d)
Cascaded Amplifiers
• Connecting several amplifiers in cascade (output of one stage connected to
the input of the next) can meet design specifications not met by a single
amplifier.
• Each amplifer stage is built using an op amp with parameters A, Rid, Ro,
called open loop parameters, that describe the op amp with no external
elements.
• Av, Rin, Rout are closed loop parameters that can be used to describe each
closed‐loop op amp stage with its feedback network, as well as the overall
composite (cascaded) amplifier.
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Two‐port Model for a 3‐stage Cascade
Amplifier
• Each amplifier in the 3‐stage cascaded amplifier is replaced by its 2‐port
model. 
R
 
R

   
vo  A vs inB 
A 
 vB
inC 
A
 vC
vA R R  R R 
 outA inB   outB inC 
vo
Since Rout= 0 Av  A A A
vs vA vB vC
Rin= RinA and Rout= RoutC = 0
32

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20/11/2015

Operational Amplifiers and Applications 1 de 24

Operational Amplifiers and Applications

Operational Amplifiers and Applications 2 de 24

Juan Suardíaz Muro Electrónica Analógica

Operational Amplifiers and Applications 3 de 24

Juan Suardíaz Muro Electrónica Analógica

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Juan Suardíaz Muro Electrónica Analógica

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-IN 2 7 V+ -IN A 2  7 OUTPUT B

DIP-741 Dual op-amp 1458 device

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+ Qu: What Vo should be if,

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The output voltage never excess the DC

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• The input signal is applied to the non-inverting input terminal.

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