Intel Galileo X1000 Gen 2

CR-1 : @GALILEO_LIB.
GALILEO(SCH_1):PAGE1
8 7 6 5 4 3 2 1
D
D
GALILEO GEN2
INTEL QUARK X1000
C C
FAB H
PB: H48142-207
B
PBA:H48125-800 B
A A
INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124
TITLE
GALILEO Gen2 DOCUMENT NUMBER REV
H38681 2.0
Thu Sep 11 08:52:51 2014 DESIGN TITLE PAGE
SHEET 1 OF 28
8 7 6 5 4 3 2 1
CR-2 : @GALILEO_LIB.GALILEO(SCH_1):PAGE2
8 7 6 5 4 3 2 1
TABLE OF CONTENTS
SHEET NUMBER SHEET NAME SHEET NUMBER SHEET NAME
1 DESIGN TITLE PAGE

D
2 TABLE OF CONTENTS D
3 DISCLAIMER
4 SYSTEM BLOCK DIAGRAM
5 QUARK DDR3 & PCIE
6 QUARK GPIO
7 QUARK MISC
8 QUARK POWER
9 QUARK DECOUPLING
10 SDRAM 1
11 SDRAM 2
12 SDRAM TERMINATION
13 MINI PCIE CONNECTOR
14 MICRO SD CONNECTOR
15 USB CONNECTORS
16 UART 1 & JTAG
C
17 LAN C
18 SPI: ADC&FLASH
19 QUARK STRAPS
20 EXTERNAL IO MUXING 1
21 EXTERNAL IO MUXING 2
22 LVL B BUFFER
23 LVL C BUFFER
24 AMUX & EXTERNAL IO
25 VOLTAGE REGULATORS
28 POWER BUTTONS & MISC
B B
A A
INTEL CORPORATION
2111 NE 25TH AVENUE
Thu Mar 03 10:58:31 2011 HILLSBORO OR 97124 DOCUMENT NUMBER: H38681
TITLE: GALILEO Gen2
TABLE OF CONTENTS REV: 2.0 SHEET 2 OF 28
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
C C
B B
A A
INTEL CORPORATION
2111 NE 25TH AVENUE
HILLSBORO OR 97124 DOCUMENT NUMBER: H38681
TITLE: GALILEO Gen2
DISCLAIMER REV: 2.0 SHEET 3 OF 28
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
C C
B B
A A
INTEL CORPORATION
2111 NE 25TH AVENUE
TITLE: GALILEO Gen2
SYSTEM BLOCK DIAGRAM REV: 2.0 SHEET 4 OF 28
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
QUARK_X1000_R1P2
U2A5 BGA393
DDR3 M_DQ<15..0> BI 10C3<> 11C3<>

12D7<> 11C6< 10B6< BI
M_BS<2..0>
2 AR13 DDR3_BS<2> DDR3_DQ<15> AR11 15
1 AT26 DDR3_BS<1> DDR3_DQ<14> AT10 14
D 0 AP26 AN5 13
DDR3_BS<0> DDR3_DQ<13> D
DDR3_DQ<12> AT5 12
12A8<> 11B6< 10B6< OUT M_CAS_N AN29 DDR3_CASB DDR3_DQ<11> AP10 11
12B8<> 11B6< 10B6< OUT M_RAS_N AR27 DDR3_RASB DDR3_DQ<10> AR9 10
12A8<> 11B6< 10A6< OUT M_WE_N AP28 DDR3_WEB DDR3_DQ<9> AP4 9
12D7<> 11C3< 10C3<> M_MA<15..0> DDR3_DQ<8> AT3 8
BI
15 AT14 DDR3_MA<15> DDR3_DQ<7> AK12 7
14 AP14 DDR3_MA<14> DDR3_DQ<6> AH12 6
13 AR29 DDR3_MA<13> DDR3_DQ<5> AJ6 5
12 AR15 DDR3_MA<12> DDR3_DQ<4> AG6 4
11 AN15 DDR3_MA<11> DDR3_DQ<3> AH15 3
10 AN24 DDR3_MA<10> DDR3_DQ<2> AL15 2
9 AP16 DDR3_MA<9> DDR3_DQ<1> AK11 1
8 AR17 DDR3_MA<8> DDR3_DQ<0> AL11 0
7 AN17 DDR3_MA<7> M_DQS<1..0> 10C3<> 11C3<>
BI
6 AR20 DDR3_MA<6> DDR3_DQS<1> AN6 1
5 AN20 DDR3_MA<5> DDR3_DQS<0> AK7 0 VREF
4 AT21 DDR3_MA<4> M_DQS_N<1..0> BI 10C3<> 11C3<>
3 AP21 DDR3_MA<3> DDR3_DQSB<1> AR6 1
2 AR22 DDR3_MA<2> DDR3_DQSB<0> AH7 0 R3L6
1 AN22 DDR3_MA<1>
0 AR24 DDR3_MA<0> DDR3_DM<1> AP7 DDR3_DM1 11C3<
OUT 274 1%
DDR3_DM<0> AL12 DDR3_DM0 OUT 10C3< 0402LF CH
C AG30 DDR3_CK<1> R3L7 C
12D3< 11B6< 10D3< 10B6< BI
M_CK<0> AJ30 DDR3_CK<0>
DDR3_DRAMRSTB AL25 M_DRAMRST_N 10A6< 11B6<
BI 34 1%
AH29 DDR3_CKB<1> 0402LF CH
12C3< 11B6< 10C3< 10B6< M_CK_N<0> AL30 DDR3_CKB<0> DDR3_VREF AM29 R3L5
BI
DDR3_ODTPU AL19 DDR3_ODTPU
AP12 DDR3_CKE<1> DDR3_DQPU AH23 DDR3_DQPU
AN11 AK23 32.4 1%
12A8<> 11B6< 10B6< BI
M_CKE<0> DDR3_CKE<0> DDR3_CMDPU DDR3_CMDPU 0402LF CH
AT32 DDR3_ODT<1> RESERVED AK19 RSVD_0 R3L8
12A8<> 11B6< 10B6< M_ODT<0> AT31 DDR3_ODT<0> RESERVED AH19 RSVD_1 0 EMPTY
BI
AP31 DDR3_CSB<1> RESERVED AK17 RSVD_2 R3L9
12A8<> 11B6< 10B6< M_CS_N<0> AN31 DDR3_CSB<0> RESERVED AL17 RSVD_3 0 EMPTY
BI
V1P5_S0
V1P5_S0 6A6> 5A7> DDR_PWROK AK25 DDR3_IDRAM_PWROK RESERVED AT34
IN R2B1
6A6> 5A7> DDR_ISYSPWRGOOD AH25 DDR3_ISYSPWRGOOD RESERVED AR35 RSVD_4
IN
10K 5%
R2A8 PCIE 0402LF CH
1 2 PCIE_RBIAS R2A10
AJ3 PCIE_RBIAS PCIE_IRCOMP AJ1 PCIE_IRCOMP
7.5K 1% EMPTY 7.5K 1%
0402LF CH INTERNAL REFCLK USED ON PCIE AE2 PCIE_REFCLKP RESERVED AE10 RSVD_5 0 R3L10 0402LF CH
B AE4 AA10 B
PCIE_REFCLKN RESERVED RSVD_6 0 R3L14
0402LF EMPTY
ONLY 1 PCIE IS USED AK2 PCIE_PERP_1 PCIE_PETP_1 AH4
AK4 PCIE_PERN_1 PCIE_PETN_1 AH2
C3A4
13B3< PCIE0_RX0_P AM2 PCIE_PERP_0 PCIE_PETP_0 AD3 PCIE0_TX0_P_C PCIE0_TX0_P 13B3>
IN OUT
13B3< PCIE0_RX0_N AN1 PCIE_PERN_0 PCIE_PETN_0 AD1 PCIE0_TX0_N_C
IN 0.1UF 10%
1 OF 5 16V
X7R
0402LF
IC C3A3
PCIE0_TX0_N OUT 13B3>
0.1UF 10%
16V
X7R
0402LF
V1P5_S3
A A
1 R4L2 1 R4L1
1K 1K
1% 1%
2 CH 2 CH
0402LF 0402LF
1/16W 1/16W
DDR_PWROK OUT 5B7< 6A6>
DDR_ISYSPWRGOOD OUT 5B7< 6A6>
INTEL CORPORATION
2111 NE 25TH AVENUE H38681
HILLSBORO OR 97124 DOCUMENT NUMBER:
TITLE: GALILEO Gen2
QUARK DDR3 & PCIE REV: 2.0 SHEET 5 OF 28
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V3P3_S0
1 R3A13 1 R3A15
D 2.2K 2.2K
QUARK_X1000_R1P2 5% 5% D
2 CH 2 CH
0402LF 0402LF
U2A5 BGA393 1/16W 1/16W V3P3_S5
19D7> 18A4< OUT
SPI0_MOSI 33.2 R2B8 CH SPI0_MOSI_R AG35 SPI0_MOSI
18A1> IN
SPI0_MISO AG33 SPI0_MISO
I2C
ON-BOARD ADC AE34
AE32
SPI0_SS_B I2C_DATA B6
C7
I2C_SDA BI 13B2<> 20A2<> 20B4<>
19D5> 18B4< OUT
SPI0_SCK 33.2 R2B11 CH SPI0_SCK_R SPI0_SCK I2C_CLK I2C_SCL BI 13B2< 20A2< 20B4<>
21C6< 19D4> OUT

SPI1_MOSI 33.2 R2B9 CH SPI1_MOSI_R AH32 SPI1_MOSI
23B7< 23B1< 6C7<> IN SPI1_MISO AK34 SPI1_MISO
AJ33 SPI1_SS_B TCK M3 JTAG_TCK R2L21
SPI
IN 16A4>
21D3< 19D3> SPI1_SCK 33.2 R3M6 CH SPI1_SCK_R AH34 SPI1_SCK TDI N4 JTAG_TDI 16A5> 49.9
OUT IN 1%
TDO R1 JTAG_TDO OUT 16A5<
TMS N2 JTAG_TMS 16B4> TP1 TP2 EMPTY
IN 0402LF
19B1> 18D6< OUT
LSPI_MOSI_R AK32 LSPI_MOSI TRST_B L4 JTAG_TRST_N IN 16A5>
18C1> IN LSPI_MISO AN35 LSPI_MISO CAD NOTE:
18C6< OUT
LSPI_CS_N_R AM33 LSPI_SS_B
19A6> 18C6< LSPI_SCK_R AM35 LSPI_SCK PLACE NEAR QUARK
OUT
PRDY_B E7 PRDY_B
PREQ_B B2 PREQ_B
DFX
22A2> 21D3< BI
MUX8_I0 1K R2M5 CH MUX8_I0_R J15 GPIO_SUS<5>
C 23C7< 23C2<> BI
LVL_C_A2 1K R39 CH LVL_C_A2_R G15 GPIO_SUS<4> RESERVED AT2 TP0 C
22B2> 21B6< BI
MUX5_I0 1K R12 CH MUX5_I0_R E15 GPIO_SUS<3> RESERVED AR1 TP1
22C2> 21A8< BI
MUX3_I0 1K R3M2 CH MUX3_I0_R J12 GPIO_SUS<2>
13B6< 13A7< BI
WIFI_DISABLE_N E12 GPIO_SUS<1>
13B6< 13A6< BI
PCIE_RESET_N G11 GPIO_SUS<0>
22C2> 21B8< BI
MUX2_I0 1K R2B21 CH MUX2_I0_R W33 GPIO<9>
22D2> 21C8< MUX1_I0 1K R2B20 CH MUX1_I0_R V34 GPIO<8> TP2A2 R3L2
BI TP2A1
GPIO
23B7< 23B1< 6C7< BI SPI1_MISO 1K R3M14 CH SPI1_MISO_R V32 GPIO<7> 2
U33 T_POINT1 T_POINT1
22D2> 21D8< BI
MUX0_I0 1K R3M10 CH MUX0_I0_R GPIO<6> 1M 5%
23D2<> 23C7< 21B3< BI
LVL_C_A1 1K R3M8 CH LVL_C_A1_R T34 GPIO<5> 1 1 0402LF CH
22A2> 21A6< BI
MUX7_I0 1K R3M5 CH MUX7_I0_R T32 GPIO<4>
23D2<> 23C7< 7B7< IN
UART0_RXD 1K R3M13 CH GPIO3_R R35 GPIO<3> TP TP
22B2> 21B6< BI
MUX6_I0 1K R2B7 CH MUX6_I0_R R33 GPIO<2>
20B5> IN
EXP2_INT 33.2 R2B29 CH EXP2_INT_R N34 GPIO<1> Y3L1
18A5< OUT
SPI0_CS_N 33.2 R2B14 CH SPI0_CS_N_R N32 GPIO<0> XTAL_IN AA2 CLN_XTAL_IN
XTAL_OUT AB1 CLN_XTAL_OUT 25.000MHZ
G3 RTCX2 RESERVED B1 RSVD_7 R3A24
C2A6 0
2 RTCX1 J2 RTCX1 RESERVED A2 RSVD_8 EMPTY
18PF 5% J11
0402LF COG 1
VCCRTCEXT IVCCRTCEXT XTAL
RTC
Y2A1 1 R2A9 REF0_OUTCLK 100MHZ G91801-001
B 10M J7 M8 C3L5 C3L6 B
32.768KHZ 5% RTCRST_B REF0_OUTCLK_P REFCLK0_P OUT 13C3< 18PF 18PF
2 CH RTC32K_CLK_SEL E11 RTC_EXT_CLK_EN_B REF0_OUTCLK_N M6 REFCLK0_N OUT 13C3< 5% 5%
CRU/PLL
XTAL 0402LF S0_PGOOD A4 S0_PG 50V 2 2 50V
C3A10 2 28A5> 6A6< IN R3L11 COG COG
2 RTCX2 1/16W 25D3> 6A6< IN
S5_PGOOD G7 S5_PG REF1_OUTCLK_P J6 REF1_P 0402LF 0402LF
REF1_OUTCLK_N H6 REF1_N 110 CH
18PF 5%
0402LF COG CAD NOTE:
CKSYS25OUT W7 CKSYS25OUT
TRACE TO CRYSTAL HAS 28D7> RESET_N D6 RESET_BTN 25MHZ - NOT USED
TO BE LENGTH MATCHED IN
19A3> IN
EC_PWRBTN_N L2 PWR_BTN FLEX0_CLK V4 FLEX0_CLK
13B8> IN
WAKE_N A5 WAKE_B FLEX1_CLK V2 FLEX1_CLK
B4 GPE_B FLEX2_CLK U3 FLEX2_CLK
V3P3_RTC GPE_N NOT USED (INTERNAL PU) R2A5
S3_1V5_EN K1 S3_1V5_EN RMII_REF_CLK_OUT T4 RMII_REF_CLK_R RMII_REF_CLK_OUT
PWRMGMT
28A8< 26B5< OUT OUT 17B8<
26D5< OUT S3_3V3_EN K3 S3_3V3_EN 00
28A6> 6A6< IN S3_PGOOD J4 S3_PG 0402LF CH
R2L9 OSC_COMP W3 OSC_COMP R2A12 R2A13 R2A14 R3L13
2 RTCRST_N 28C5< 28B8< 26A8< 6A6< S0_1V0_EN F4 S0_1V0_EN R3L3 49.9 49.9 49.9 49.9
OUT 1% 1% 1% 1%
10K 5% 28B7< 27C6< 26B3< OUT
S0_1V5_EN F2 S0_1V5_EN HPLL_REFCLK_P V7 EXT_REFCLK_HPLL CH CH CH CH
0402LF CH 26D3< OUT
S0_3V3_EN E4 S0_3V3_EN HPLL_REFCLK_N V5 10K 5% 0402LF
28B6> 6A6< IN PG_V1P0_S0 D2 S0_1P0_PG 0402LF CH 1/16W
C3L13 C2L1 AF11 RSVD_9 R3L12
0.1UF C3L8 1UF RESERVED 0 NOT USED
10% 1UF 10% J30 VNNSENSE RESERVED AD11 RSVD_10 EMPTY V1P5_S5
16V 6.3V H30
2 X7R 10%
6.3V V3P3_RTC 2 X5R VSSSENSE
0402LF 2 X5R 0402LF PAD_BYPASS_CLK AC4
A R3 A
0402LF 5B7< 5A7> OUT
DDR_PWROK ODRAM_PWROK
5B7< 5A7> OUT
DDR_ISYSPWRGOOD T2 OSYSPWRGOOD 2 OF 5 1 R2A11
R2L10 7.5K
2 1%
IC 2 CH
TP4 0402LF
RTC_EXT_CLK_EN_B 1K 1%
0402LF EMPTY
R2L11 T_POINT1
10K 25D3> 6B6< S5_PGOOD 1
0: EXTERNAL CLOCK FROM RTCX1/RTXC2 5% TP5
1: INTERNAL CLOCK CH
0402LF
T_POINT1
1
TP7 INTEL CORPORATION
28A6> 6A6< S3_PGOOD T_POINT1 2111 NE 25TH AVENUE
28A5> 6B6< S0_PGOOD 1 HILLSBORO OR 97124
TP6
T_POINT1
1
TP8
T_POINT1
TITLE
GALILEO Gen2 DOCUMENT NUMBER REV
28C5< 28B8< 26A8< 6A6> S0_1V0_EN H38681 2.0
28B6> 6A6< PG_V1P0_S0 1 QUARK GPIO
SHEET 6 OF 28
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
7D4<> USBH0_DP_R R79 USBH0_DP BI 15C6<>

USBH0_DN_R 0 CH USBH0_DN
7D4<> R77 BI 15C6<>
0 CH
C52 C53
CAD NOTE: 18PF 18PF
5% 5%
PLACE USB CAPS AS CLOSE 25V 25V
AS POSSIBLE TO SOC. EMPTY EMPTY
0201LF 0201LF
QUARK_X1000_R1P2
D
U2A5 BGA393 D
7C4<> USBH2_DP_R R78 USBH2_DP BI 15B6<>

USBH2_DN_R 0 CH USBH2_DN
7C4<> R76 BI 15A6<>
USBH1_DP P29 USBH1_DP BI 13B3<> 0 CH
USBH1_DN P30 USBH1_DN BI 13B3<>
AA4 C51 C54
RESERVED 18PF 18PF
W5 RESERVED USBH0_DP V30 USBH0_DP_R 7D3< 5% 5%
TS_IREF_N W9 TS_IREF_N USBH0_DN V29 USBH0_DN_R 7D3<
25V 25V
C0G C0G
TS
AC7 TS_TDA 0201LF 0201LF
R3L4 NOT USED, LEAVE FLOATING AC5 TS_TDC USBD_DP M29 USBH2_DP_R 7D3<
8.06K USBD_DN M31 USBH2_DN_R 7D3<
1% V3P3_S0
2 CH
0402LF USB_CLK96P M35 INTERNAL CLOCKS USED FOR USB
1/16W USB_CLK96N M33
PD_CLK14 D9 CLK14 LEAVE FLOATING PER USB TEAM INPUT
USB
LEGACY
B9 THRM_B RESERVED L34 RSVD_11 R2B28
0 EMPTY R3B4
NOT USED (INTERNAL PU) C10 SMI_B RESERVED L32 RSVD_12 10K
R3A20 5%
10K USB0_OC_B G35 USB_OC0_N 15C5> CH
1% IN 0402LF
USB1_OC_B J32 USB_OC1_N 1/16W
CH
0402LF F34
C USBH0_PWR_EN USB_PWR_EN0 OUT 15C8< C
USBH1_PWR_EN G33
IUSBCOMP_N18 K33 USBCOMP

OUSBCOMP_P18 J34
1 R2B2
RMII_REF_CLK C16 RMII_REFCLK 17B5>
22.6
IN 1%
C28 SD_DATA<7> 2 CH
B27 SD_DATA<6> MAC0_TXEN C21 RMII_S0_TX_EN_R 33.2 R2M12 CH RMII_S0_TX_EN 0402LF
33.2 OUT 17C4<
D27 SD_DATA<5> MAC0_TXDATA<1> D22 RMII_S0_TXD1_R R2M14 CH RMII_S0_TXD1 OUT 17C4< 19B7> 1/16W
14C6<> CLN_SD_DAT<3..0> A26 SD_DATA<4> MAC0_TXDATA<0> A21 RMII_S0_TXD0_R 33.2 R2M8 CH RMII_S0_TXD0
BI OUT 17C4< 19B6>
3 C26 SD_DATA<3> MAC0_RXDV C18 RMII_S0_RX_DV IN 17C1>
B24 B20
ETHERNET
2 SD_DATA<2> MAC0_RXDATA<1> RMII_S0_RXD1 IN 17C1>
1 D24 SD_DATA<1> MAC0_RXDATA<0> D20 RMII_S0_RXD0 IN 17C1>
SDIO
0 C23 SD_DATA<0>
MAC0_MDC D17 RMII_S0_MDC_R 33.2 R2M7 CH RMII_S0_MDC 17C4< 17C7>
33.2 OUT
MAC0_MDIO B17 RMII_S0_MDIO_R R2M11 CH RMII_S0_MDIO BI 17C2<> 17C6<>
14C6<> CLN_SD_CMD B22 SD_CMD
BI 33.2 R2L4 CH CLN_SD_CLK_R
19A7> 14C6< OUT
CLN_SD_CLK J19 SD_CLK MAC1_TXEN C12
G19 SD_WP MAC1_TXDATA<1> B15 RMII_S1_TXD1 OUT 19B4>
14C6> CLN_SD_CD_N E19 SD_CD_B MAC1_TXDATA<0> D15 RMII_S1_TXD0 19D1>
ONLY USED FOR STRAPS
IN OUT
14A5< SD_LED E17 SD_LED MAC1_RXDV C14
B OUT B
G17 SD_PWR MAC1_RXDATA<1> B13
MAC1_RXDATA<0> D13
MAC1_MDC B11
AD29 SIU0_CTS_B MAC1_MDIO D11
AC27 SIU0_DCD_B
AA32 SIU0_DSR_B
W29 SIU0_DTR_B
AD28 SIU0_RI_B
UART
W30 SIU0_RTS_B
23D2<> 23C7< 6B7< IN
UART0_RXD AA34 SIU0_RXD
21A6< OUT
UART0_TXD W35 SIU0_TXD
16C5> UART1_CTS_N AB33 SIU1_CTS_B
IN
16C5< OUT
UART1_RTS_N AD33 SIU1_RTS_B
21B1> IN
UART1_RXD AC34 SIU1_RXD
21C3< 16C5< OUT
UART1_TXD AC32 SIU1_TXD
TXD OUTPUT FROM QUARK
3 OF 5
A A
IC
INTEL CORPORATION
2111 NE 25TH AVENUE
TITLE: GALILEO Gen2
QUARK MISC REV: 2.0 SHEET 7 OF 28
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V1P0_S0
V3P3_S0
V1P0_S3_IVR FB3L1 TP18
D 1 2 T_POINT1
V1P0_S5 QUARK_X1000_R1P2 D
1 V3P3_S3
0.5A 10 BGA393
C3L21 C3L14 U2A5 V3P3_S5
1UF 1UF
10% 10% V3P3_RTC
6.3V 6.3V AB14 VCCADDR_1P0 VCC3P3_S3 K14
TP15 X5R X5R
TP13 0402LF 0402LF AD14 VCCADLLDDR_1P0 VCC3P3_S5 P5 TP21
T_POINT1 AB13
T_POINT1
V1P0_S0_FLT VCCACLKDDR_1P0 T_POINT1
1 P14 VCC1P0_S3 VCC3P3_S0 AA26
1 T13 VCC1P0_S5 VCC3P3_S0 AB24 TP19 1
V16 VCC1P0_S0 VCC3P3_S0 AD24 TP22
V14 T_POINT1
VCC1P0_S0 T_POINT1
AD13 VCCPLLDDR_1P0 1
Y14 VCCAPCIE_1P0 VCCRTC3P3 E1 1
T11 VCCAICLKCB_1P0
V1P5_S0 V1P5_S3 P11 VCCDICLKDIG_1P0 VCCAICLKSE_3P3 P7
V1P5_S5 TP17 V11 VCCAICLKDBUFF_1P0 VCC3P3_A F30
V1P8_S3_IVR VCC3P3_USB_S3 K16
TP12 T_POINT1 T18
T_POINT1
VCCAVISA_1P0
TP10 1 VNN AB18 V1P0_S0
1 VNN AB20
T_POINT1 V1P05_S0_IVR AT12 VCCDDR_1P5 VNN Y18 V1P05_S0_IVR
C 1 V1P0_S5 AT16 VCCDDR_1P5 VNN V18 TP20 C
AT18 VCCDDR_1P5 VNN Y20 V1P0_S3_IVR V1P8_S0_IVR
AT23 Y16 T_POINT1
TP16 VCCDDR_1P5 VNN
VNN V20 1 V1P8_S3_IVR
T_POINT1 R26
TP14 VCCFSOC_1P05
V1P8_S5_IVR 1 T24 VCCFHVSOC_1P05 OVOUT_1P05_S0 P24 V1P8_S5_IVR
T_POINT1 V13 M14 TP3 T_POINT1
V1P8_S0_IVR VCCAICLKSSC1_1P0 OVOUT_1P0_S3
1 R10 VCCAICLKSFR_1P5 OVOUT_1P0_S5 T14 V1P0_S5_IVR 1
AD31 VCCSFRPLLDDR_1P5
AD5 VCC1P5_S0 OVOUT_1P8_S0 P18
1 2 V1P5_S3_LC AT28 VCCCLKDDR_1P5 OVOUT_1P8_S3 M18
TP11 OVOUT_1P8_S5 K11
FB3M1 0.5A 10 K20
T_POINT1
VCCAUSB_1P8_S3
K22 VCCAA_1P8 OVOUT_1P8_SLDO K24
1 P22 VCCAUSB_1P8
TP9 P20 VCC1P8_S0
T20 VCC1P8_S0
T_POINT1 K18 P16
VCC1P8_S3 VSSA_USB
1 K13 VCC1P8_S5 4 OF 5
IC
B C3M3 B
1UF
10%
6.3V
X5R
0402LF
CAD NOTE
PLACE AS CLOSE AS POSSIBLE TO SIGNAL VIAS
STITCHING CAPS FOR SPLIT PLANES
STITCHING CAPS FOR SIGNAL REFERENCE TRANSITION
V1P5_S5 V3P3_S5
V3P3_S5 V3P3_S3 V3P3_S0 V1P0_S0
C2A10
0.1UF 10%
16V
X7R
V3P3_S3 V3P3_S0 0402LF V3P3_S5 VBUS1 V5_ALW_ON V3P3_S0 V1P5_S3 V1P5_S5
A C2A7 C3A20 C3A21 C3B16 C4B6 C2B13 C3B17 C2B12 A
0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
10% 10% 10% 10% 10% 10% 10% 10%
50V 50V 50V 50V 50V 50V 50V 50V
X7R X7R X7R X7R X7R X7R X7R X7R
0402LF 0402LF 0402LF 0402LF 0402LF 0402LF 0402LF 0402LF
C1L3 C4B7 C1M13 C1M14 C3A22 C3M12 C2M10 C3B18 C4A3 C3M13 C1B1 C2A8 C2A9 C3A23 C3A24
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R
0402LF 0402LF 0402LF 0402LF 0402LF 0402LF 0402LF 0402LF 0402LF 0402LF 0402LF 0402LF 0402LF 0402LF 0402LF
INTEL CORPORATION
2111 NE 25TH AVENUE
TITLE: GALILEO Gen2
QUARK POWER REV: 2.0 SHEET 8 OF 28
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V3P3_S0 QUARK_X1000_R1P2
RECOMMENDATION FROM PD STUDY V3P3_S3
BGA393
U2A5
A7 VSS VSS AP23

D 1 1 1 1 A10 AP33
C3M1 C3M2 C3L30 C3M8 C3M7 C3M6 C3M5 C3L19 VSS VSS D
1000PF 1000PF 1000PF 1000PF 1000PF 1000PF 1000PF 0.01UF A12 VSS VSS AT7
10% 10% 10% 10% 10% 10% 10% 10% A14 VSS VSS AN27
50V 50V 50V 50V 50V 50V 50V
2 50V
X7R 2 X7R 2 X7R X7R X7R X7R X7R 2 X7R A16 VSS VSS AP18
0402LF 0402LF 0402LF 0402LF 0402LF 0402LF 0402LF 0402LF A18 VSS VSS F6
A36096-046 A23 VSS VSS H17
A31 VSS VSS B33
AB3 VSS VSS D5
V3P3_S5 AB11 VSS VSS U1
AB16 VSS VSS V27
AD35 VSS VSS G1
AB35 VSS VSS G12
AC2 VSS VSS J25
AC9 VSS VSS K35
1 1 AC29 VSS VSS M1
C3L9 C3L10 AC30 M11
1UF 1UF VSS VSS
10% 10% AD18 VSS VSS M5
6.3V 2 6.3V AD6 VSS VSS M16
2 X5R X5R
0402LF 0402LF AD8 VSS VSS M13
AD16 VSS VSS M22
AN13 VSS VSS M28
AE26 VSS VSS P9
AF13 VSS VSS AD20
C AF22 VSS VSS P13 C
V1P8_S3_IVR AF24 VSS VSS P27
RECOMMENDATION FROM PD STUDY V1P5_S5 AG1 VSS VSS Y22
V1P5_S3
AG3 VSS VSS T16
AH11 VSS VSS T22
AH17 VSS VSS U35
AK15 VSS VSS V9
1 AJ35 VSS VSS V22
C3L11 AK29 VSS VSS W1
1 1 1 1 C3L25 C3L27 1UF AF20 W27
C3L23 C3M4 C3L16 C3L12 1000PF 1000PF 10% VSS VSS
2.2UF 2.2UF 2.2UF 2.2UF 10% 10% 6.3V AL6 VSS VSS Y11
10% 10% 10% 10% 16V 16V 2 X5R AL23 VSS VSS Y13
6.3V 6.3V 6.3V 6.3V X7R X7R 0201LF
2 X5R 2 X5R 2 X5R 2 X5R 0201LF 0201LF AM1 VSS VSS AP2
0603LF 0603LF 0603LF 0603LF D70538-001 AM4 VSS VSS C1
AM7 VSS VSS A28
AM32 VSS VSS A34
AN9 VSS VSS B29
E32 VSS VSS C35
D33 VSS VSS E35
D31 VSS VSS B31
RECOMMENDATION FROM PD STUDY D29 VSS VSS B35
V1P0_S0 F32 VSS VSS A32
B M26 AD22 B
NC NC
E25 NC NC AF14
J23 NC NC AB22
M24 NC NC V24
Y24 NC NC E23
1 1 G25 NC NC G29
C3B10 C2B2 C3L22 C3L17 C3L15 C3L18 C3L20 C3L26 C3L24 C3L29 C3L28 AF16 AF18
22UF 22UF 10UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF NC NC
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% G23 NC NC J29
4V 4V 4V 4V 4V 4V 4V 4V
2 6.3V
X5R 2 6.3V
X5R
4V
X5R X5R X5R X5R X5R X5R X5R X5R X5R M20 NC NC E29
0603LF 0603LF 0402LF 0201LF 0201LF 0201LF 0201LF 0201LF 0201LF 0201LF 0201LF
602433-081 A36096-108 C83410-012 5 OF 5
IC
A A
INTEL CORPORATION
2111 NE 25TH AVENUE
TITLE: GALILEO Gen2
QUARK DECOUPLING REV: 2.0 SHEET 9 OF 28
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V1P5_S3
V1P5_S3
CAD NOTE:
PLACE 0.1UF DECOUPLING AS CLOSE AS POSSIBLE TO DRAM POWER PINS
1
C1A19
D 22UF
20% D
2 6.3V
X5R
0805LF 1 1
C1A15 C4M3 C1A25 C1A24
0.1UF 0.1UF 0.1UF 2.2UF 12D3< 11B6< 10B6< 5C7<> M_CK<0>
10% 10% 10% IN
16V 16V 16V 10%
2 X7R 2 X7R X7R 6.3V
V1P5_S3 0402LF 0402LF 0402LF X5R
0603LF 1
C4M1
1PF
.25PF
2 50V
COG
0402LF
12C3< 11B6< 10B6< 5C7<> IN M_CK_N<0>
VREF C1A23
0.1UF
10%
2 16V MT41K128M8
X7R U1B5
0402LF
B9 VDDQ DM/TDQS B7 DDR3_DM0 IN 5C3>
C1 VDDQ NF/TDQS_N A7
E2 VDDQ
E9 VDDQ DQS C3 M_DQS<0> BI 5C3<>
DQS_N D3 M_DQS_N<0> BI 5C3<>
C A2 C
VREF VDD M_DQ<7:0> BI 5D3<>
A9 VDD DQ<7> E7 7
D7 VDD DQ<6> D2 6
G2 VDD DQ<5> E8 5
G8 VDD DQ<4> E3 4
K1 VDD DQ<3> C8 3
K9 VDD DQ<2> C2 2 M_MA<15:0>
2 M1 C7 1 BI 5D7<> 11C3< 12D7<>
C4M4 C1A22 VDD DQ<1>
0.1UF 0.1UF M9 VDD DQ<0> B3 0
10% 10%
1 16V 16V J8 VREFCA
X7R X7R
0402LF A0 K3 0
0402LF E1 L7 1
VREFDQ A1
M_BS<2..0> A2 L3 2
11C6< 5D7<> IN K2 3
12D7<> A3
2 J3 BA<2> A4 L8 4
1 K8 BA<1> A5 L2 5
0 J2 BA<0> A6 M8 6
A7 M2 7
12A8<> 11B6< 5C7<> IN M_ODT<0> G1 ODT A8 N8 8
A9 M3 9
12A8<> 11B6< 5C7<> IN M_CKE<0> G9 CKE A10/AP H7 10
B R4M1 A11 M7 11 B
ZQ_1 H8 ZQ A12/BC_N K7 12
240 1% A13 N3 13
12D3< 11B6< 10D3< 5C7<> IN
M_CK<0> 0402LF CH F7 CK 14
15
12C3< 11B6< 10C3< 5C7<> IN M_CK_N<0> G7 CK_N
12A8<> 11B6< 5B7<> IN M_CS_N<0> H2 CS_N VSSQ B2
VSSQ B8
12A8<> 11B6< 5D7> M_CAS_N G3 CAS_N VSSQ C9
IN
VSSQ D9
12B8<> 11B6< 5D7> IN
M_RAS_N F3 RAS_N VSSQ D1
12A8<> 11B6< 5D7> IN

M_WE_N H3 WE_N
VSS A1
11B6< 5C3<> IN M_DRAMRST_N N2 RESET_N VSS A8
VSS B1 DESIGN NOTE:
VSS D8
A3 NC_A3 VSS F2 A14, A15 ALLOW FOOTPRINT COMPATIBILITY WITH
F1 NC_F1 VSS F8 2GBIT(256MBIT X 8) AND 4GBIT (512MBIT X8) DEVICES
F9 NC_F9 VSS J1
H1 NC_H1 VSS J9
H9 NC_H9 VSS L1
J7 NC_J7 VSS L9
A N7 NC_N7 VSS N1 A
VSS N9
IC
G83568-001
SDRAM 1
INTEL CORPORATION
TITLE: GALILEO Gen2
SDRAM 1 REV: 2.0 SHEET 10 OF 28
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V1P5_S3
CAD:
PLACE 0.1UF DECOUPLING AS CLOSE AS POSSIBLE TO DRAM PINS
D
V1P5_S3 D
1 1
C1A16 C4M2 C4L3 C1A14
0.1UF 0.1UF 0.1UF 2.2UF
10% 10% 10% 10%
VREF 2 16V 2 16V 16V 6.3V
X7R X7R X7R X5R
0402LF 0402LF 0402LF 0603LF
C1A21
0.1UF
10%
2 16V
X7R
0402LF
MT41K128M8
U1A1
VREF B9 VDDQ DM/TDQS B7 DDR3_DM1 5C3>
IN
C1 VDDQ NF/TDQS_N A7 M_DQS<1> 5C3<>
BI
E2 VDDQ M_DQS_N<1>
BI 5C3<>
E9 VDDQ DQS C3
DQS_N D3 M_DQ<15:8>
BI 5D3<>
A2 VDD
A9 VDD DQ<7> E7 15
D7 VDD DQ<6> D2 14
C 2 C1A20 G2 VDD DQ<5> E8 13 C
C1A13 0.1UF G8 E3 12
0.1UF 10% VDD DQ<4>
10% 16V K1 VDD DQ<3> C8 11
1 16V X7R K9 VDD DQ<2> C2 10
X7R M_MA<15:0> 5D7<> 10C3<> 12D7<>
0402LF 0402LF M1 VDD DQ<1> C7 9 IN
M9 VDD DQ<0> B3 8
J8 VREFCA
A0 K3 0
E1 VREFDQ A1 L7 1
M_BS<2..0> A2 L3 2
12D7<> 10B6< 5D7<> IN K2 3
A3
2 J3 BA<2> A4 L8 4
1 K8 BA<1> A5 L2 5
0 J2 BA<0> A6 M8 6
A7 M2 7
12A8<> 10B6< 5C7<> IN M_ODT<0> G1 ODT A8 N8 8
A9 M3 9
12A8<> 10B6< 5C7<> M_CKE<0> G9 CKE A10/AP H7 10
IN
R4L19 A11 M7 11
ZQ_2 H8 ZQ A12/BC_N K7 12
A13 N3 13
12D3< 10D3< 10B6< 5C7<> M_CK<0> 240 1%
0402LF CH F7 CK 14 DESIGN NOTE:
B IN B
15 A14, A15 ALLOW FOOTPRINT COMPATIBILITY WITH
12C3< 10C3< 10B6< 5C7<> IN M_CK_N<0> G7 CK_N 2GBIT(256MBIT X 8) AND 4GBIT (512MBIT X8) DEVICES
12A8<> 10B6< 5B7<> M_CS_N<0> H2 CS_N VSSQ B2
IN
VSSQ B8
12A8<> 10B6< 5D7> M_CAS_N G3 CAS_N VSSQ C9
IN
VSSQ D9
12B8<> 10B6< 5D7> IN
M_RAS_N F3 RAS_N VSSQ D1
12A8<> 10A6< 5D7> IN

M_WE_N H3 WE_N
VSS A1
10A6< 5C3<> M_DRAMRST_N N2 RESET_N VSS A8
IN
VSS B1
VSS D8
A3 NC_A3 VSS F2
F1 NC_F1 VSS F8
F9 NC_F9 VSS J1
H1 NC_H1 VSS J9
H9 NC_H9 VSS L1
J7 NC_J7 VSS L9
N7 NC_N7 VSS N1
VSS N9
A A
IC
G83568-001
SDRAM 2
INTEL CORPORATION
TITLE: GALILEO Gen2
SDRAM 2 REV: 2.0 SHEET 11 OF 28
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VTT
11C6< 10B6< 5D7<> M_BS<2:0> VTT

BI R1A20 C1A5
2 0.1UF
36.5 R4L23 10%
1 16V
D X7R
36.5 R4L22 0402LF
0 D
36.5 1%
0402LF CH VTT
1
C4L2
0.1UF
10%
11C3< 10C3<> 5D7<> M_MA<15..0> 2 16V
BI R4L11 X7R
15 36.5 R1A19 11B6< 10D3< 10B6< 5C7<> IN
M_CK<0> M_CK_CAP 0402LF
30.1 1%
0402LF CH
14 36.5 R4L7
13 36.5 R1A18 11B6< 10C3< 10B6< 5C7<> M_CK_N<0> R4L10

IN
30.1 1%
0402LF CH
12 36.5 R4L21
11 36.5 R4L20
VTT
C 10 36.5 R4L14 C
9 36.5 R4L8
8 36.5 R4L18
C1A7 C1A8 C1A10 C1A6 C1A9
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
10% 10% 10% 10% 10%
16V 16V 16V 16V 16V 7 36.5 R1A2
X7R X7R X7R X7R X7R
0402LF 0402LF 0402LF 0402LF 0402LF
6 36.5 R1A3
5 36.5 R4L17
CAD:
4 36.5 R1A5
DITRIBUTE DECOUPLING AMONG
TERMINATION RESISTORS
3 36.5 R1A4
B B
2 36.5 R4L6
1 36.5 R4L5
0 36.5 R4L16
1%
G73524-001
11B6< 10B6< 5D7> BI
M_RAS_N 36.5 R4L12
11B6< 10B6< 5D7> BI

M_CAS_N 36.5 R4L13
11B6< 10A6< 5D7> BI

M_WE_N 36.5 R4L15
11B6< 10B6< 5C7<> BI

M_CKE<0> 36.5 R4L3
11B6< 10B6< 5B7<> BI

M_CS_N<0> 36.5 R4L4
11B6< 10B6< 5C7<> BI

M_ODT<0> 36.5 R1A6
A A
INTEL CORPORATION
2111 NE 25TH AVENUE
TITLE: GALILEO Gen2
SDRAM TERMINATION REV: 2.0 SHEET 12 OF 28
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MH1
MTG_HOLE_4V
1
3
4
5
6
D
D
CONN
MH2 MH4
MTG_HOLE_4V MTG_HOLE_4V
1 1 V1P5_S0
3 3
4 4
5 5
6 6
PCIE SLOT 0
CONN CONN
C3A25 C3A26
0.1UF 0.1UF MPCIE_52P_LATCH_KIT
V3P3_S3 10% 10% FULL_MINI_CARD
16V 16V J2L1
X7R X7R
0402LF 0402LF
6 +1.5V REFCLK+ 13 REFCLK0_P IN 6B2>
REFCLK- 11 REFCLK0_N IN 6B2>
C 2 C
+3.3VAUX
UIM_DATA 10
R2A1 UIM_CLK 12
C3A1 C3A2 C3A7 1K 1 14
22UF 0.1UF 0.1UF 1% WAKE_N UIM_RESET USER IDENTITY MODULE (EXTENSION OF SIM)
20% 10% 10% CH UIM_PWR 8
2 6.3V
X5R 2 16V
X7R 2 16V
X7R 0402LF DYNAMIC CLK MANAGMENT OUTPUT 7 CLKREQ_N UIM_VPP 16 NOT SUPPORTED BY QUARK
0805LF 0402LF 0402LF 1/16W
A36096-030 IS NOT SUPPORTED ON GALILEO GND 4
3 COEX1 GND 9
5 COEX2 GND 15
KEY
28 +1.5V PETP0 33 PCIE0_TX0_P OUT 5B2>

6B6< OUT
WAKE_N 48 +1.5V PETN0 31 PCIE0_TX0_N OUT 5A2>
24 +3.3VAUX PERP0 25 PCIE0_RX0_P IN 5B7<

39 +3.3VAUX PERN0 23 PCIE0_RX0_N IN 5B7<
41 +3.3VAUX
52 +3.3VAUX LED_WPAN_N 46
B LED_WLAN_N 44 B
LED_WWAN_N 42
13A7< 6C7<> IN
WIFI_DISABLE_N 20 W_DISABLE_N USB_D+ 38 USBH1_DP BI 7D3<>
USB_D- 36 USBH1_DN BI 7D3<>
13A6< 6C7<> IN
PCIE_RESET_N 22 PERST_N R3A4
SMB_DATA 32 SLT0_SDA 1 2 R3A3 I2C_SDA BI 6D2<> 20A2<> 20B4<>
SMB_CLK 30 SLT0_SCL 0 1 2 I2C_SCL IN 6D2<> 20A2< 20B4<>
0402LF EMPTY 0
17 RESERVED/UIM_C8 GND 18 0402LF EMPTY
19 RESERVED/UIM_C4 GND 21
RESERVED PINS, NO CONNECT 45 RESERVED GND 26
47 RESERVED GND 27
49 RESERVED GND 29
51 RESERVED GND 34
GND 35
GND 37
GND 40
MP1 MP1 GND 43
MP2 MP2 GND 50
A V3P3_S3 KIT_PARTS=(LATCH: QTY=1) A

V3P3_S3
C59768-003
R52
R27 1K
1K 5%
5% CH
CH 0402LF
0402LF 1/16W
1/16W PCIE_RESET_N 6C7<> 13B6<
WIFI_DISABLE_N 6C7<> 13B6<
INTEL CORPORATION
2111 NE 25TH AVENUE
TITLE: GALILEO Gen2
MINI PCIE CONNECTOR REV: 2.0 SHEET 13 OF 28
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V3P3_S0
U1L1
CM1230_02
D
B2 VP D
A2 CH1 CH2 B1
VN A1
IC
U1L2
CM1230_02
TP25
B2 VP
T_POINT1
TP A2 B1
CH1 CH2 MICRO SD CONNECTOR
TP24
VN A1
T_POINT1
TP
V3P3_S0 IC CONN_SDCARD_8P_PP
C
J4A2 C
7B7<> BI
CLN_SD_DAT<2> 33.2 R2L13 CH CLN_SD_DAT2_R 1 DAT2
7B7<> BI
CLN_SD_DAT<3> 33.2 R2L6 CH CLN_SD_DAT3_R 2 CD/DAT3
7B8<> BI
CLN_SD_CMD 33.2 R2L12 CH CLN_SD_CMD_R 3 CMD
4 VDD
19A7> 7B8> IN
CLN_SD_CLK 5 CLK
6 VSS
1 1 7B7<> BI
CLN_SD_DAT<0> 33.2 R2L7 CH CLN_SD_DAT0_R 7 DAT0
C1L1 C1L2 8
1UF 1UF 7B7<> BI
CLN_SD_DAT<1> 33.2 R2L8 CH CLN_SD_DAT1_R DAT1
10% 10%
2 6.3V 2 6.3V 7B8< CLN_SD_CD_N 33.2 R2L5 CH CLN_SD_CD_N_R 9 CARD_DET_SW
X5R X5R OUT
0402LF 0402LF 10 CARD_DET_SW
V3P3_S0 G1 G1
U1L3 G2 G2
G3 G3
CM1230_02 G4 G4
B2 VP
CONN
A2 CH1 CH2 B1 G46739-001
B VN A1 B
V3P3_S0
IC
U1L4
CM1230_02
B2 VP
A2 CH1 CH2 B1
VN A1
IC
7B8> IN
SD_LED
A A
SILKSCREEN:
SD ACTIVITY
DS4A2 R1L10
2 1 LED_SD 2
GREEN 1K 1%
E16297-001 0402LF CH
CAD NOTE:
PLACE SD LED CLOSE TO THE SDIO CONN
INTEL CORPORATION
TITLE: GALILEO Gen2
MICRO SD CONNECTOR REV: 2.0 SHEET 14 OF 28
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CAD NOTE:
PLACE C2B11 AS CLOSE AS
POSSIBLE TO U3B1 PIN5
VBUS1
V5_ALW_ON
V3P3_S0
R3B12 USB HOST
LED_VBUS1
D
1K 1% D
0402LF CH NOTE:
1
1 1 R2B15 DS3B1 C2M7
100UF
C3M11
47UF
C3B14
470PF
TYPE A CONN
C2B11 10K 20% 20% 10%
0.1UF 5% GREEN 6.3V 6.3V 50V J2B3
10% SOT23LF 2 CH LED X5R X5R 2 X7R
2 16V U3B1 0402LF 1210LF 0805LF 0603LF CONN
X7R CONN4_D23040001
0402LF 1/16W
TPS2051BDBVR
MH1
5 IN OUT 1 1
USBH0_DN_CH 2
OC_N 3 USB_OC0_N 7C3<
CAD NOTE: USBH0_DP_CH 3
OUT PLACE CHOKE AND DIODES CLOSE TO USB CONN
7C3> IN
USB_PWR_EN0 4 EN 4
GND 2 L3M2
90OHM MH2
R3B3 1 CHOKE_4P
10K 7D1<> USBH0_DN 1 2
5% BI D23040-001
CH 2 IC
0402LF E58210-001
1/16W
7D1<> BI
USBH0_DP 4 3
C C
IND
E53905-001
V5_ALW_ON U2B2
CM1230_02
B2 VP
A2 CH1 CH2 B1
VN A1
IC
D30400-001
B B
USB CLIENT
VCC_USB1
NOTE:
TYPE B CONN
L3M1 J3B2
90OHM
CHOKE_4P
CAD NOTE: MICRO_USB_5P_SMT
7D1<> BI
USBH2_DP 1 2
PLACE CHOKE AND DIODES CLOSE TO USB CONN
1 VCC
7D1<> BI
USBH2_DN 4 3 USBH2_DN_CH 2 D- MT MT1
USBH2_DP_CH 3 D+ MT MT2
IND MT3
E53905-001 4
MT MT4
ID MT
MT MT5
5 GND MT MT6
V5_ALW_ON U2B3
CM1230_02 HDR
A A
G58911-001
B2 VP
A2 CH1 CH2 B1
VN A1
IC
INTEL CORPORATION
2111 NE 25TH AVENUE
TITLE: GALILEO Gen2
USB CONNECTORS REV: 2.0 SHEET 15 OF 28
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
V3P3_S5 CR1 V3P3_S5
R81
22K
5%
CH
BAT15 0402LF J3
SOT23C 1/16W
DIO 1X6HDR
1
C UART1_RTS_N UART1_RTS_N_R 2 C
7A7> IN R40
240 1% 3
21B3< OUT
UART1_RXD_MUX R42 UART1_RXD_MUX_R 4
21C3< 7A7> IN
UART1_TXD R41 240 1% UART1_TXD_R 5
7A7< OUT
UART1_CTS_N 240 1% R43 UART1_CTS_N_R 6
240 1%
R80 HDR
0
0
EMPTY
0402LF
1/20W
V3P3_S5
B B
R2L1 R1L1 R1L3

1K 1K 1K
1% 1% 1%
EMPTY EMPTY CH
0402LF 0402LF 0402LF
1/16W 1/16W 1/16W
V3P3_S5 R1L5 JTAG_TMS OUT 6C2<
33.2 1%
J2
CONN R1L7 JTAG_TCK 6C2<
conn_2x5_shrd_male OUT
1 1 2 2 JTAG_TMS_R 33.2 1%
3 3 4 4 JTAG_TCK_R
1 5 5 6 6 JTAG_TDO IN 6C2>
C4A1 7 7 8 8 JTAG_TDI OUT 6C2<
0.1UF 9 10 JTAG_TRST_N
10% 9 10 OUT 6C2<
2 16V
X7R H32748-001
0402LF
R1L2
A
1K
1% A
EMPTY
0402LF
1/16W
CAD NOTE:
PLACE CONNECTOR ON SOLDER-SIDE.
INTEL CORPORATION
2111 NE 25TH AVENUE
TITLE: GALILEO Gen2
UART 1 & JTAG REV: 2.0 SHEET 16 OF 28
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V3P3_S0 V3P3_S0_A V3P3_S0_A

V5_ALW_ON
J1A6
CAD NOTE:
1X3HDR PLACE NEAR ETHERNET PORT. V3P3_S0 V3P3_S0_A
1 PIN1 SILK= +5V C1M7 1 C1M8
1 R4B1 1 R4B2 1 R4B3 R1M3 2 0.1UF 1UF
4.7K 1.5K 1.5K 2.2K VSHLD_S5 3 10% 10%
5% 1% 1% 5% 2 X7R 2 X5R
D PIN3 SILK= +3.3V 0402LF 0402LF
2 CH 2 CH 2 CH CH FB1M1 D
0402LF 0402LF 0402LF 0402LF HDR 2
1/16W 1/16W 1/16W 1/16W V3P3_S5 V3P3_S0 FB
AGND_VCC
1 C1M6 C1M10 C1M2 U4B1 R1
1UF 0.1UF 0.1UF IC
RMII_S0_RX_DV_R OUT 17C2< 10% 10% 10% dp83848j 2.2K 5%
2 X5R 2 X7R 2 X7R 1 8
0402LF 0402LF 0402LF IOVDD RESERVED 0402LF CH
18 AVDD33 RESERVED 9
RMII_S0_RST_N OUT 17C4< 26 IOVDD33 RESERVED 10
RMII_S0_MDIO BI 7B2<> 17C2<> IN 17D6>
CRS/CRS_DV/LED_CFG 33 ETH_BLINK
RMII_S0_MDC 7B2> 17C4< 17C7> RMII_S0_RST_N 23 RESET_N RX_DV/MII_MODE 32 RMII_S0_RX_DV_R 33.2 R2M9 CH RMII_S0_RX_DV 7B2<
OUT IN OUT
2 TX_CLK RX_CLK 31
CAD NOTE: 7C2> IN
RMII_S0_TX_EN 3 TX_EN COL/PHYADO 35
V3P3_S0 PLACE CAPACITORS C1M3 & C1M5 CLOSE TO PFBIN(PIN18&37) 19B6> 7B2> RMII_S0_TXD0 4 TXD_0 RXD_0/PHYAD1 36 RMII_S0_RXD0_R 33.2 R2M13 CH RMII_S0_RXD0 7B2<
IN 33.2 OUT
19B7> 7C2> IN
RMII_S0_TXD1 5 TXD_1 RXD_1/PHYAD2 37 RMII_S0_RXD1_R R2M10 CH RMII_S0_RXD1 OUT 7B2<
6 TXD_2 RXD_2/PHYAD3 38
7 TXD_3 RXD_3/PHYAD4 39
34 RX_ER/MDIX_EN
C C1M1 17C7> 7B2> IN
RMII_S0_MDC 25 MDC MDIO 24 RMII_S0_MDIO BI 7B2<> 17C6<> C
R1M10 R1M9 R1M8 0.1UF
49.9 49.9 C1M9 R1M7 49.9 10% 17B7<> 17A3<> RMII_S0_TDN 14 TD- RD- 11 RMII_S0_RDN 17A3<> 17C6<>
0.1UF 49.9 1% 2 X7R BI BI
1% 1% 10% 17B8<> 17A3<> BI
RMII_S0_TDP 15 TD+ RD+ 12 RMII_S0_RDP BI 17A3<> 17B7<>
1% CH 0402LF
CH CH 2 X7R CH 0402LF R4B4
0402LF 0402LF 0402LF 0402LF 2 2 1 PHY_RBIAS 20 RBIAS
2 2 2 16 PFBIN1 PFBOUT 19 RMII_S0_PFB 17C5<
4.87K 1% OUT
0402LF CH 30 PFBIN2
17C2> IN
RMII_S0_PFB LED_SPEED/AN1 21 LED_SPEED 17A1<
RMII_S0_RDN BI 17A3<> 17C2<> 17B6< RMII_I_X1 28 X1 LED_LINK/AN0 22 LED_LINK 17A1<
27 X2
C1M3 C1M5 DGND 29
RMII_S0_RDP 17A3<> 17C2<>
0.1UF 0.1UF 13 AGND IOGND 40 C1M4 1 C4B5
BI 10% 10% 0.1UF 10UF
X7R 2 2 X7R 17 AGND THPAD 41 10% 10%
RMII_S0_TDN BI 17A3<> 17C5<> 0402LF 0402LF 2 X7R 16V
H31881-001 0402LF 2 TANT
CAD NOTE: 0805LF
G63888-001
RMII_S0_TDP 17A3<> 17C5<>
PLACE RESISTOR AND LED SIGNALS HAVE INTERNAL PU
BI CAPAS CLOSE TO RMII PHY AGND_VCC CAD NOTE:
17C4< 1 2 R3A6 RMII_I_X1 PLACE CAPACITORS CLOSE TO PFBOUT(PIN23)
22.6 1% R1M6
6A2> RMII_REF_CLK_OUT 0402LF 1 2
B IN B
00
0603LF CH
R3A7 V3P3_S0
1 2 RMII_REFCLK
OUT 7C3<
22.6 1%
RMII PHY AGND_VCC
CAD NOTE: R2M15
LENGTH MATCH CLOCK SPLIT. TRACE BETWEEN PIN 1 OF RESISTORS SHOULD BE SHORT 4.7K
5%
CH
J4B1
0402LF SINGATRON_2TJ582_010111H
1/16W RMII_S0_CT1 2
CT
YELLOW
V3P3_S0
17B8<> BI
RMII_S0_TDP 1 D1+ J1
C1M12 17C5<>
RMII_VC3 VIN_POE DESIGN NOTE: U16 IS 0.1UF RMII_S0_TDN 3 L2 LED_SPEED 17C2<
17A4< 10% 17B7<> BI D1- J2
2 X7R 17C5<>
DESIGNED FOR SILVERTEL AG9712-FL OR AG9712-2BR 0402LF 17B7<> RMII_S0_RDP 4 D2+ R1M1
BI L1 LED_RJ45_C1
1
J3
D1 17C2<>
U16 RMII_S0_RDN 5 110 1%
esd_diode EMPTY 17C6<> 17C2<> BI D2- J6 L4 LED_LINK 17C2<
SMAJ58CA AG9712S FB1
1 8 RMII_VC4 RMII_VC4_R 10
2
VA1 VDC 17A8<> VC4

17A4< RMII_VC4 2 VA2 FB FB3 J4
L3 LED_RJ45_C2 R1M2
A RMII_VC1 3 RMII_VC3 RMII_VC3_R 9 A
17A4< VB1 C44 17A8<> VC3
GREEN
4 470UF FB J5 110 1%
VB2 R47 0402LF CH
1
D2 5 NC2 620 20%

6 5% 16V MMZ2012R102A 6
esd_diode NC3 ALUM 1K-OHM 0.5A
GND
SMAJ58CA R44 NC1 10 CH 10MMLF FB2 J7
0 9 7 1206LF RMII_VC1 RMII_VC1_R 7
2
5% ADJ GND 1/2W 17A8<> VC1

EMPTY FB FB4 J8 MH1 11
RMII_VC2 0402LF TBD RMII_VC2 RMII_VC2_R 8 12
17A4< 17A8<> VC2 MH2
1/16W VPOE_ADJ FB
R45 R46 CONN
0 5% 0 5%
0402LF EMPTY 0402LF EMPTY
INTEL CORPORATION
2111 NE 25TH AVENUE
TITLE: GALILEO Gen2
LAN REV: 2.0 SHEET 17 OF 28
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V3P3_S0
CR3M1
2
3 VCC_FLASH
C4M5 C4M6
0.1UF 4.7UF
D VCC_DEDIPROG 1 10% 10% 1 1
2 16V
X7R 2 6.3V
X5R D
0402LF 0603LF R3M15 R4M2
BAT54C 4.7K 4.7K
5% 5%
SOT23C
DIO CH CH
0402LF 0402LF
J1B2 2 2 U2B4
2X4HDR7 R2B5 W25Q64FV_8P
19B1> 6C6> IN
LSPI_MOSI_R 1 2
1 2 33.2 1%
3 4 0402LF CH 8 VCC
5 6
8 AT25_WP_N 3 WP_N
R2B6
6C6> LSPI_CS_N_R 1 2 LSPI_CS_N 1 CS_N
IN
HDR 33.2 1% R2B10
A91836-079 0402LF CH LSPI_MOSI 5 DI DO 2 LSPI_MISO_R 1 2 LSPI_MISO 6C6<
OUT
33.2 1%
LSPI_SCK 6 CLK 0402LF CH
LSPI_CS_N HAS INTERNAL 20K PU IN QUARK AT25_HOLD_N 7 HOLD_N GND 4
C
R2B18 C
19A6> 6C6> IN LSPI_SCK_R 1 2
33.2 1% IC
0402LF CH H10285-001
FLASH
BIOS STORAGE
V5_ALW_ON
FB5
V3P3_S0 .28A
120
FB
V5_ALW_ON_FIL CAD NOTE:
1 C5 C2B1
B 1UF 0.1UF PLACE DECOUPLING CAPACITORS AS CLOSE AS POSSIBLE TO ADC B
R2B30 20% 10%
10K 10V 16V
5% X5R X7R
0402LF 0402LF C3M9 C3M10
CH 1UF 0.1UF
0402LF 20% 10%
2 10V 16V
X5R X7R U11
0402LF 0402LF IC
adc108s102
2 VA
13 VD
19D5> 6D7> SPI0_SCK 16 SCLK

IN SPI0_MOSI 14
19D7> 6D7> IN DIN
6B7> SPI0_CS_N 1 CS_N
IN
ANALOG_A0 22 R1A11 ANALOG_A0_R 4 15 SPI0_MISO_R 33.2 R3M11 CH SPI0_MISO
24B2<> 20B5> IN IN0 DOUT OUT 6D7<
24B2<> 20B5> ANALOG_A1 22 R1A16 ANALOG_A1_R 5 IN1
IN ANALOG_A2 22 ANALOG_A2_R 6
24B2<> 20B5> IN R1A13 IN2
24B2<> 20B5> ANALOG_A3 22 R1A10 ANALOG_A3_R 7 IN3
IN AVIN4 22 AVIN4_R 8
24C8> IN R1A1 IN4
24C8> AVIN5 22 R1A7 AVIN5_R 9 IN5
IN 10 3
IN6 AGND
11 IN7 DGND 12
C38 C39 C40 C41 C42 C43
0.001UF 0.001UF 0.001UF 0.001UF 0.001UF 0.001UF H31902-001
A 10% 10% 10% 10% 10% 10% A
10V 10V 10V 10V 10V 10V
X5R X5R X5R X5R X5R X5R
0402LF 0402LF 0402LF 0402LF 0402LF 0402LF
INTEL CORPORATION
TITLE: GALILEO Gen2
SPI: ADC&FLASH REV: 2.0 SHEET 18 OF 28
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V3P3_S0
V3P3_S0 V3P3_S0
R2B16
10K
1% R3M9 R2B12
CH 10K 10K
0402LF 1% 1%
D 1/16W EMPTY CH D
TP23 SPI0_MOSI 6D7> 18A4<
0402LF 0402LF
OUT 1/16W 1/16W
SPI0_SCK 6D7> 18B4< SPI1_MOSI 6D7> 21C6<
SPI1_SCK 6C7> 21D3< RMII_S1_TXD0 7B4>
OUT OUT OUT OUT
R2B19 R2B17 R3A17

10K 10K 10K
SILK=FWR 1%
CH
1%
EMPTY R3M7 1%
CH
0402LF 0402LF 10K 0402LF
DESIGN NOTE: 1/16W 1/16W 1%
EMPTY 1/16W
SHORT TO GND TO ENTER 0402LF
1/16W
RECOVERY MODE. BIT1 BIT0
(HIGH) X8 DDR SDRAM 01 - 1GBIT SDRAM (LOW) MEMORY DOWN CONFIG (LOW) PUNIT BASE ADDRESS
V3P3_S0
C C
R4B8
10K
1%
CH
0402LF
RMII_S0_TXD1 OUT 7C2> 17C4< RMII_S0_TXD0 OUT 7B2> 17C4< RMII_S1_TXD1 OUT 7B4> LSPI_MOSI_R OUT 6C6> 18D6<
R4B6 R4B5 R3A14

100K 100K 10K
1% 1% 1% R2B4
CH EMPTY CH 10K
0402LF 0402LF 0402LF 1%
1/16W 1/16W 1/16W CH
0402LF
B 1/16W B
BIT2 BIT1 BIT0

000 - QUARK SKU SETTINGS (LOW) SINGLE RANK DDR3 SDRAM
EC_PWRBTN_N OUT 6B6<

CLN_SD_CLK 7B8> 14C6<
LSPI_SCK_R 6C6> 18C6<
OUT OUT
A R3A10 A
R1L11 R2B13 10K
10K 10K 1%
1% 1% CH
CH CH 0402LF
0402LF 0402LF 1/16W
1/16W 1/16W
BIT1 BIT0 (LOW) POWER BUTTON NOT USED

00 - REMOVABLE CARD SLOT FOR SDIO
INTEL CORPORATION
2111 NE 25TH AVENUE
TITLE: GALILEO Gen2
QUARK STRAPS REV: 2.0 SHEET 19 OF 28
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VSHLD_S5 VSHLD_S5
R3
4.7K C6
5% 0.1UF
EMPTY 10%
VSHLD_S5 16V U4
0402LF X7R IC
D U1 1/16W 0402LF
IC pca9685
EXP0_INT
25 VDD LED0 3 MUX0_SEL OUT 21D8< D
21 PCAL9535AHF
1 LVL_B_OE0_N LED1 4 MUX0_I1 OUT 21D8<
VDD P0_0 OUT 20C7< 22C7< 22D3<> LVL_I2C_SDA 24 5 MUX1_SEL
2 LVL_B_PU0 24C6<> 20D8<> 20C6<> 20B8<> 20B2<> SDA LED2 OUT 21C8<
P0_1 OUT 22D6< LVL_I2C_SCL 23 6 MUX1_I1
LVL_I2C_SCL 19 3 LVL_B_OE1_N 24C6<> 20D8<> 20C6< 20B8< 20B2<> SCL LED3 OUT 21C8<
20C6< 20B8< 20B2<> BI SCL P0_2 OUT 20C7< 22C3<> 22C7<
24C6<> 20D3< 20 SDA P0_3 4 LVL_B_PU1 22D6<
LVL_I2C_SDA 5 LVL_B_OE2_N OUT 20 OE_N LED4 7 MUX2_SEL OUT 21B8<
20C6<> 20B8<> 20B2<> BI P0_4 OUT 20C7< 22C3<> 22C7< 8 MUX2_I1
24C6<> 20D3<> P0_5 6 LVL_B_PU2 22D6<
VSHLD_S5 LED5 OUT 21B8<
7 LVL_B_OE3_N OUT LED6 9 MUX3_SEL OUT 21A8<
C1 P0_6 OUT 20C7< 22C3<> 22C7< 22 10 MUX3_I1
8 LVL_B_PU3 EXTCLK LED7 OUT 21A8<
0.1UF P0_7 OUT 22D6<
10% 24 A2 P1_0 10 LVL_B_OE4_N 20C7< 22B3<> 22B7<
16V 23 11 LVL_B_PU4 OUT 26 AO LED8 12 MUX4_SEL OUT 21C6<
X7R A1 P1_1 OUT 22A6< R8 27 13 MUX4_I1
0402LF 18 12 LVL_B_OE5_N A1 LED9 OUT 21C6<
A0 P1_2 OUT 20C7< 22B3<> 22B7< 4.7K 28 14 MUX6_SEL 21A6<
13 LVL_B_PU5 5% A2 LED10 OUT
P1_3 OUT 22A6< VSHLD_S5 1 15 MUX6_I1 21B6<
VSHLD_S5 P1_4 14 LVL_B_OE6_N 20C7< 22A3<> 22B7< EMPTY A3 LED11 OUT
15 LVL_B_PU6 OUT U3 0402LF 2 A4
P1_5 OUT 22A6< IC 21 16 MUX9_SEL
16 LVL_B_OE7_N EXP1_INT A5 LED12 OUT 21C3<
P1_6 OUT 20C7< 22A3<> 22B7< PCAL9535AHF 17 MUX10_SEL
9 17 LVL_B_PU7 21 1 LVL_C_OE0_N LED13 OUT 21B3<
VSS P1_7 OUT 22B6< VDD P0_0 OUT 20A7< 23C5< 23D2<> 18 AMUX2_IN1
25 22 2 LVL_C_PU0 LED14 OUT 24C8<
THPAD INT_N P0_1 OUT 23D5< 11 19 AMUX2_IN2
LVL_I2C_SCL 19 3 LVL_C_OE1_N VSS LED15 OUT 24C8<
24C6<> 20D8<> 20D3< 20B8< 20B2<> SCL P0_2 OUT 20A7< 23C2<> 23C5< 29
R67 R72 H47895-001 LVL_I2C_SDA 20 4 LVL_C_PU1 THPAD
20D8<> 20D3<> 20B8<> 20B2<> SDA P0_3 OUT 23D5<
22K 22K EXP0 24C6<> 5 LVL_C_OE2_N
5% 5% P0_4 OUT 20A7< 23C2<> 23C5< H29123-001
R64 CH R71 CH P0_5 6 LVL_C_PU2
BI 23D5<
C 22K 22K P0_6 7 IO7
OUT 20A5< 24C3<> C
5% 5% C4 8 IO7_PU
0.1UF P0_7 20A5<
CH R69 CH 10% 24 A2 P1_0 10 IO8 20A4< 24C3<>
R61 22K 16V OUT
22K 5% LVL_B_OE0_N 20D6> 22C7< 22D3<> X7R 23 A1 P1_1 11 IO8_PU 20A4<
5% CH LVL_B_OE1_N 20D6> 22C3<> 22C7< 0402LF 18 A0 P1_2 12 LVL_C_OE5_N OUT 20A7< 23B2<> 23C5<
CH LVL_B_OE2_N 20D6> 22C3<> 22C7< P1_3 13 LVL_C_PU5 23B5<
R59 OUT
22K LVL_B_OE3_N 20D6> 22C3<> 22C7< P1_4 14 MUX5_SEL OUT 20A7< 21B6<
R51 5% LVL_B_OE4_N 20D6> 22B3<> P1_5 15 MUX7_SEL 20A7< 21A6<
22K CH V3P3_S0 OUT
5% LVL_B_OE5_N 22B7< 20C6> 22B3<> P1_6 16 MUX8_SEL OUT 20A7< 21D3<
CH LVL_B_OE6_N 20C6> 22B7< 9 VSS P1_7 17 SW_RESET_N_SHLD 20A5<
LVL_B_OE7_N 22A3<> 22B7< 20C6> 22A3<> 25 THPAD INT_N 22
22B7< VSHLD_S5
R4 H47895-001
4.7K EXP1
5%
VSHLD_S5 CH
U2
0402LF
IC 1/16W
R5 R6
21 PCAL9535AHF
VDD P0_0 1 ANALOG_A0 18A7< 24B2<>
1.8K 1.8K
OUT 5% 5%
P0_1 2 ANALOG_A0R 22K R34 CH CH
24C6<> 20D8<> 20D3< 20C6< 20B2<> LVL_I2C_SCL 19 SCL P0_2 3 0402LF ANALOG_A1 18A7< 24B2<> 0603LF 0603LF
OUT
20D8<> 20D3<> 20C6<> 20B2<> LVL_I2C_SDA 20 SDA P0_3 4 ANALOG_A1R 22K R35 1/10W 1/10W
24C6<> P0_4 5 0402LF ANALOG_A2 OUT 18A7< 24B2<> 20A2< 13B2< 6D2<> BI
I2C_SCL LVL_I2C_SCL BI 20B8< 20C6< 20D3< 20D8<> 24C6<>
B 6 ANALOG_A2R 22K R36 Q1L2 B
P0_5
P0_6 7 0402LF ANALOG_A3 18A7< 24B2<> FET
C3 OUT
0.1UF P0_7 8 ANALOG_A3R 22K R37
10% 24 A2 P1_0 10 0402LF AMUX2_NO1 OUT 24C8<> I2C_SDA
16V 23 11 AMUX2_NO1_R 22K 20A2<> 13B2<> 6D2<> BI
LVL_I2C_SDA BI 20B8<> 20C6<> 20D3<> 20D8<> 24C6<>
X7R A1 P1_1 R2 Q1L1
0402LF 18 A0 P1_2 12 0402LF AMUX2_NO2 OUT 24C8<> FET
P1_3 13 AMUX2_NO2_R 22K R38 24C6<
VSHLD_S5 P1_4 14 0402LF AMUX1_IN
OUT 20A5< R10 V3P3_S0
P1_5 15 MUX_IO2 0 IO2 OUT 23C3<> 24C3<>
P1_6 16 MUX_IO3 0 R26 CH IO3 22C4<> 24C3<>
OUT
9 VSS P1_7 17 RESET_N_SHLD OUT 20A5< 24A5<> CH
25 THPAD INT_N 22 EXP2_INT 6B7< 24A6<>
OUT
H47895-001
V3P3_S5
R63 R70 R7
22K 22K EXP2 0
5% 5% 5%
R60 CH R68 EMPTY CH
22K 22K 0402LF
5% 5% 1/16W SW_RESET_N_SHLD 20C4<>
CH R66 EMPTY C12
R57 22K 0.1UF R33
22K MUX5_SEL 20C3> 21B6< 10K
5% 5% MUX7_SEL 10% 5% U8
EMPTY 20C3> 21A6< 16V
CH MUX8_SEL 20C3> 21D3<
VSHLD_S5 X7R CH IC
R50 0402LF 0402LF
22K LVL_C_OE0_N 20C4> 23C5< 23D2<> 20C4<> IO8_PU 1/16W 8 cat24c08hu4i
2
5% LVL_C_OE1_N 20C4<> IO7_PU VCC NC
20C4> 23C2<> 23C5< 1
A CH LVL_C_OE2_N NC A
20C4> 23C2<> 23C5< I2C_SCL 6
LVL_C_OE5_N R32 20B4<> 13B2< 6D2<> SCL
20C3> 23B2<> 23C5< R31 I2C_SDA 5
22K 22K 20B4<> 13B2<> 6D2<> SDA
R73 R75 R65 5% 5% 3 A2 VSS 4
22K 22K 22K CH CH 7 WP THPAD 9
5% 5% 5% 0402LF 0402LF
CH R74 CH CH IO7 1/16W 1/16W H31877-001
0402LF 24C3<> 20C3> 20C3> IO8
22K 24C3<>
5% R62 1/16W
CH 22K
5% AMUX1_IN 20B5> 24C6<
CH
0402LF RESET_N_SHLD 20B5> 24A5<> 24A6<>
1/16W
INTEL CORPORATION
2111 NE 25TH AVENUE
TITLE: GALILEO Gen2
EXTERNAL IO MUXING 1 REV: 2.0 SHEET 20 OF 28
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V3P3_S5
V3P3_S5
U9
D
74LVC1G157
U23
74LVC1G157 D
REV=1
MUX0_I1 1 5 REV=1
20D1> IN I1 VCC SPI1_SCK 1 5
19D3> 6C7> IN I1 VCC
22D2> 6C7<> MUX0_I0 3 I0 Y 4 MUX0_Y 21C3<

IN 22A2> 6C7<> IN
MUX8_I0 3 I0 Y 4 MUX8_Y OUT 22B8<
MUX0_SEL 6 2 C14 V3P3_S5

20D1> IN S GND 0.1UF MUX8_SEL 6 2 C25
10% U19 20C3> 20A7< IN S GND 0.1UF
16V 10%
IC X7R 74LVC1G157 16V
IC X7R
MUX0 0402LF
REV=1 MUX8 0402LF
20C1> MUX4_I1 1 I1 VCC 5
IN
21B4> MUX5_Y 3 I0 Y 4 MUX4_Y 22B8<

V3P3_S5 OUT
U10 V3P3_S5
MUX4_SEL 6 2 C20
74LVC1G157 20D1> IN S GND 0.1UF U24
10% 74LVC1G157
REV=1 IC 16V
20D1> MUX1_I1 1 I1 VCC 5 X7R REV=1
IN MUX4 0402LF
16C5< 7A7> UART1_TXD 1 I1 VCC 5
C IN C
22D2> 6C7<> MUX1_I0 3 I0 Y 4 MUX1_Y 22C8<
IN OUT
21D6> MUX0_Y 3 I0 Y 4 MUX9_Y 22C8<
OUT
MUX1_SEL 6 2 C15
20D1> IN S GND 0.1UF V3P3_S5 C26
10% 20C1> MUX9_SEL 6 S GND 2 0.1UF
16V U20 IN
IC X7R 10%
MUX1 0402LF 74LVC1G157
IC 16V
X7R
REV=1 MUX9 0402LF
19D4> 6D7> SPI1_MOSI 1 I1 VCC 5
IN
V3P3_S5 22B2> 6C7<> MUX5_I0 3 I0 Y 4 MUX5_Y 21C5<

IN
U13 V3P3_S0
74LVC1G157 MUX5_SEL 6 2 C22
20C3> 20A7< IN S GND 0.1UF U25
REV=1 10% 74LVC1G157
MUX2_I1 1 5 16V
20D1> IN I1 VCC IC X7R REV=1
MUX5 0402LF
23D2<> 23C7< 6C7<> LVL_C_A1 1 I1 VCC 5
IN
22C2> 6C7<> MUX2_I0 3 I0 Y 4 MUX2_Y 22C8<
IN OUT
16C5> UART1_RXD_MUX 3 I0 Y 4 UART1_RXD 7A7<
B IN OUT B
MUX2_SEL 6 2 C16
20D1> IN S GND 0.1UF V3P3_S5
10% 6 C27
16V 20C1> IN
MUX10_SEL S GND 2 0.1UF
IC X7R U21
MUX2 0402LF 74LVC1G157
10%
16V
IC X7R
REV=1 MUX10 0402LF
20C1> MUX6_I1 1 I1 VCC 5
IN
V3P3_S5
22B2> 6B7<> MUX6_I0 3 I0 Y 4 MUX6_Y 22B8<
U14 IN OUT
74LVC1G157
MUX6_SEL 6 2 C23
REV=1 20C1> IN S GND 0.1UF
20D1> MUX3_I1 1 I1 VCC 5 10%
IN 16V
IC X7R
MUX6 0402LF
22C2> 6C7<> MUX3_I0 3 I0 Y 4 MUX3_Y 22C8<
IN OUT
MUX3_SEL 6 2 C17
20D1> IN S GND 0.1UF
10%
16V V3P3_S5
IC X7R
MUX3 0402LF U22
74LVC1G157
A A
REV=1
7B7> UART0_TXD 1 I1 VCC 5
IN
22A2> 6B7<> MUX7_I0 3 I0 Y 4 MUX7_Y 22B8<

IN OUT
MUX7_SEL 6 2 C24
20C3> 20A7< IN S GND 0.1UF
10%
IC 16V
X7R
MUX7 0402LF
INTEL CORPORATION
2111 NE 25TH AVENUE
TITLE: GALILEO Gen2
EXTERNAL IO MUXING 2 REV: 2.0 SHEET 21 OF 28
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
EU3
IC
74LVC126A
2 3 MUX0_I0 OUT 6C7<> 21D8<

D V3P3_S0
D
LVL_B_OE0_N 20C7< 20D6> 22C7<
1
20D6> LVL_B_PU3 C88413-002
IN VCC=V3P3_S0;GND=GND;TH=GND
20D6> LVL_B_PU2
20D6>
IN
LVL_B_PU1 EU3
IN C31 IC
20D6> IN
LVL_B_PU0 0.1UF
10% 74LVC126A
16V
X7R
VSHLD_S5 0402LF 5 6 MUX1_I0 OUT 6C7<> 21C8<
LVL_B_OE1_N 20C7< 20D6> 22C7<
4
C88413-002
VCC=V3P3_S0;GND=GND;TH=GND
C29 R17 R21 R22 R24 EU3
0.1UF 22K 22K 22K 22K IC
V5_ALW_ON
10%
16V
5%
CH
5%
CH
5%
CH
5%
CH
74LVC126A
X7R U18 0402LF 0402LF 0402LF 0402LF
0402LF IC 1/16W 1/16W 1/16W 1/16W 9 8 MUX2_I0 OUT 6C7<> 21B8<
14 sn74lv125a
VCC BI 24C3<>
BI 20B4> LVL_B_OE2_N
LVL_B_OE0_N 1 24C3<> 20C7< 20D6> 22C7<
10
C 22D3<> 20D6> 20C7< IN 1OE_N C
C28 2 1A 1Y 3 IO3 C88413-002
0.1UF 22C3<> 20D6> 20C7< LVL_B_OE1_N 4 2OE_N EU3 VCC=V3P3_S0;GND=GND;TH=GND
10% IN
16V U17 5 2A 2Y 6 IO5 IC
X7R IC 20D6> 20C7< LVL_B_OE2_N 10 3OE_N 74LVC126A
0402LF IN
20 sn74lv541at 22C3<>
22C3<>
9 3A 3Y 8 IO6
VCC LVL_B_OE3_N 13
20D6> 20C7< IN 4OE_N
MUX9_Y 2 18 BUF_IO3 12 4A 4Y 11 IO9 12 11 MUX3_I0 OUT 6C7<> 21A8<
21C1> IN A1 Y1 7
MUX1_Y 3 17 BUF_IO5 GND
21C6> IN A2 Y2 15
MUX2_Y 4 16 BUF_IO6 THPAD BI 24D3<> LVL_B_OE3_N
21B6> IN A3 Y3 20C7< 20D6> 22C7<
13
5 15 BI 24C3<>
21A6> IN
MUX3_Y A4 Y4 BUF_IO9 H29265-001 C88413-002
21C3> IN
MUX4_Y 6 A5 Y5 14 BUF_IO11 VCC=V3P3_S0;GND=GND;TH=GND
21B3> MUX6_Y 7 A6 Y6 13 BUF_IO10 U15
21A3>
IN
MUX7_Y 8 A7 Y7 12 BUF_IO1 IC EU2
IN IC
21D1> IN
MUX8_Y 9 A8 Y8 11 BUF_IO13 14 sn74lv125a
1 VCC BI 24D3<> 74LVC126A
OE1_N OUT 23B7< 24A1> 24D3<>
19 OE2_N GND 10 LVL_B_OE4_N 1 BI
21 22B3<>
20D6>
20C7< IN 1OE_N
THPAD 2 3 IO11 2 3 MUX5_I0
1A 1Y OUT 6C7<> 21B6<
H31894-001 22B3<>
20C7<
20C6> IN
LVL_B_OE5_N 4 2OE_N
5 2A 2Y 6 IO10
LVL_B_OE6_N 10 LVL_B_OE4_N 20C7< 20D6> 22B7<
1
22A3<> 20C7< 20C6> IN 3OE_N
9 3A 3Y 8 IO1 C88413-002
B
22A3<> 20C7< 20C6> LVL_B_OE7_N 13 4OE_N
VCC=V3P3_S0;GND=GND;TH=GND B
IN
12 4A 4Y 11 IO13 EU2
GND 7 24D3<> IC
THPAD 15 BI 24A5<> 74LVC126A
BI 24C3<>
C30H29265-001 R18 R20 R23 R25
5 6 MUX6_I0
0.1UF 22K 22K 22K 22K OUT 6B7<> 21B6<
10% 5% 5% 5% 5%
16V CH CH CH CH
X7R 0402LF 0402LF 0402LF 0402LF LVL_B_OE5_N 20C6> 20C7< 22B7<
4
0402LF 1/16W 1/16W 1/16W 1/16W C88413-002
20C6> IN
LVL_B_PU7 EU2
20C6> IN
LVL_B_PU6 IC
20C6> IN
LVL_B_PU5 74LVC126A
20C6> IN
LVL_B_PU4
V3P3_S0 9 8 MUX7_I0 6B7<> 21A6<
OUT
LVL_B_OE6_N 20C6> 20C7< 22B7<
10
C88413-002
C32
0.1UF EU2 VCC=V3P3_S0;GND=GND;TH=GND
10%
16V
IC
A X7R 74LVC126A A
0402LF
12 11 MUX8_I0 OUT 6C7<> 21D3<
LVL_B_OE7_N 20C6> 20C7< 22B7<
13
C88413-002
INTEL CORPORATION
2111 NE 25TH AVENUE
TITLE: GALILEO Gen2
LVL B BUFFER REV: 2.0 SHEET 22 OF 28
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
EU4
IC
74LVC126A
2 3 UART0_RXD 6B7< 7B7< 23C7<

D V3P3_S0
D
LVL_C_OE0_N 20A7< 20C4> 23C5<
1
C88413-002
20C3<> LVL_C_PU2 VCC=V3P3_S0;GND=GND;TH=GND
IN EU4
20C4> IN
LVL_C_PU1
LVL_C_PU0 C36 IC
20C4> IN 0.1UF
10% 74LVC126A
16V
X7R
VSHLD_S5 0402LF 5 6 LVL_C_A1 6C7<> 21B3< 23C7<
LVL_C_OE1_N 20A7< 20C4> 23C5<
4
C88413-002
C34 R11 R28 R29 EU4
0.1UF 22K 22K 22K IC
V5_ALW_ON 10% 5% 5% 5% 74LVC126A
16V CH CH CH
X7R U26 0402LF 0402LF 0402LF
0402LF IC 1/16W 1/16W 1/16W
24C3<>
9 8 LVL_C_A2 6C7<> 23C7<
14 sn74lv125a
VCC BI 20B4>
BI 24C3<> LVL_C_OE2_N
LVL_C_OE0_N 1 20A7< 20C4> 23C5<
10
C C33 23D2<> 20C4> 20A7< IN 1OE_N C
2 3 IO0 C88413-002
0.1UF 1A 1Y
10% 23C2<> 20C4> 20A7< IN
LVL_C_OE1_N 4 2OE_N
16V U12 5 6 IO2
X7R IC 2A 2Y
0402LF sn74lv541at 23C2<> 20C4> 20A7< IN
LVL_C_OE2_N 10 3OE_N
20 VCC 9 3A 3Y 8 IO4
23B2<> 20C3> 20A7< IN
LVL_C_OE5_N 13 4OE_N BI 24C3<>
23D2<> 7B7< 6B7< IN
UART0_RXD 2 A1 Y1 18 BUF_IO0 12 4A 4Y 11
23D2<> 21B3< 6C7<> IN
LVL_C_A1 3 A2 Y2 17 BUF_IO2 GND 7
23C2<> 6C7<> IN
LVL_C_A2 4 A3 Y3 16 BUF_IO4 THPAD 15 EU4
5 A4 Y4 15 IC
6 A5 Y5 14 H29265-001 74LVC126A
23B1< 6C7< 6C7<> IN
SPI1_MISO 7 A6 Y6 13 BUF_IO12
22B6> IN
BUF_IO13 8 A7 Y7 12 IO13_LED
9 A8 Y8 11 IO12 12 11 BUF_SPI1_MISO 33.2 R56 SPI1_MISO 6C7<> 6C7< 23B7<
1 OE1_N R30 CH
19 OE2_N GND 10 22K
21 5%
13
THPAD CH C88413-002
0402LF
H31894-001 1/16W 24A5<>
BI 24D3<>
R2A3 LVL_C_OE5_N 20A7< 20C3> 23C5<

B 330 LVL_C_PU5 B
5% 20C3> IN
CH
0402LF
CAD NOTE: IO13_LED_R 1/16W
PLACE AT LED AREA
DS2A1
GREEN
LED
A A
INTEL CORPORATION
2111 NE 25TH AVENUE
TITLE: GALILEO Gen2
LVL C BUFFER REV: 2.0 SHEET 23 OF 28
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
J2B1
THLF
D
1X10RCPT D
V5_ALW_ON V5_ALW_ON
24C4<> 24B2<> ANALOG_A5 10
BI
24C4<> 24B2<> ANALOG_A4 9
BI
AREF 8
7
24A5<> 22B4<> IO13 33.2 R3M16 IO13_R 6 DIGITAL 13
U28 U7 BI
24A5<> 23B3<> IO12 33.2 R3M17 IO12_R 5 DIGITAL 12
C2 IC C9 IC BI
0.1UF 0.1UF 24A1> 22B4<> IO11 33.2 R3M18 IO11_R 4 DIGITAL 11
BI
10% 10% 22B4<> IO10 33.2 R3M19 IO10_R 3 DIGITAL 10
16V TS5A23159 16V TS5A23159 BI
X7R X7R 22C4<> IO9 33.2 R3M20 IO9_R 2 DIGITAL 9
BI
0402LF 8 VP 0402LF 8 VP 20C3> 20A4< BI
IO8 1 DIGITAL 8
20C1> IN
AMUX2_IN1 1 IN1 20B5> 20A5< IN
AMUX1_IN 1 IN1 C2B5
20B5> BI
AMUX2_NO1 2 NO1 COM1 10 AMUX2_COM1 2 NO1 COM1 10 ANALOG_A4 24B2<> 24D3<> 0.1UF CONN
18A7< OUT
AVIN4 9 NC1 20B8<> 20B2<> BI
LVL_I2C_SDA 9 NC1 10%
16V G79666-001
20D3<> 20C6<>
20D8<> X7R
20C1> IN
AMUX2_IN2 5 IN2 5 IN2 0402LF
20B5> BI
AMUX2_NO2 4 NO2 COM2 6 AMUX2_COM2 4 NO2 COM2 6 ANALOG_A5 24B2<> 24D3<>
18A7< OUT
AVIN5 7 NC2 20B8< 20B2<> BI
LVL_I2C_SCL 7 NC2
20D3< 20C6< J1B1
20D8<>
GND 3 GND 3 1X8RCPT
C G63512-001 G63512-001 20C3>20A5< IO7 8 C
BI DIGITAL 7
22C4<> BI
IO6 33.2 R1B2 IO6_R 7
AMUX2 AMUX1 22C4<> IO5 33.2 R4M12 IO5_R 6 DIGITAL 6
BI DIGITAL 5
23C3<> BI
IO4 33.2 R4M11 IO4_R 5
22C4<> 20B4> IO3 33.2 R4M10 IO3_R 4 DIGITAL 4
BI DIGITAL 3
23C3<> 20B4> BI
IO2 33.2 R4M9 IO2_R 3
22B4<> IO1 33.2 R4M8 IO1_R 2 DIGITAL 2
BI DIGITAL 1
23C3<> BI
IO0 33.2 R4M7 IO0_R 1
DIGITAL 0
CONN
CAD NOTE: PLACE RESISTORS CLOSE TO CONNECTOR.
THLF
J1A5
1X6RCPT
20B5> 18A7< ANALOG_A0 1
BI
20B5> 18A7< ANALOG_A1 2
BI
20B5> 18A7< BI
ANALOG_A2 3
20B5> 18A7< BI
ANALOG_A3 4
B 24D3<> 24C4<> BI
ANALOG_A4 5 B
24D3<> 24C4<> BI
ANALOG_A5 6
VSHLD_S5
CONN
G79672-001
R1A21 V5_ALW_ON
100K
1%
CH
0402LF
VSHLD_S5 1/16W
J1
CONN
CONN6_H18587001
V3P3_S5 24D3<> 23B3<> BI
IO12 33.2 R13 IO12_ICSP_R 1 2
24D3<> 22B4<> BI
IO13 33.2 R14 IO13_ICSP_R 3 4 IO11_ICSP_R 33.2 R15 IO11 OUT 22B4<> 24D3<>
24A6<> 20B5> 20A5< BI
RESET_N_SHLD 5 6
V5_ALW_ON
J2A1
THLF H18587-001
1X8RCPT
A 1 PIN1:OPEN A
SILK=ICSP HDR
2 PIN2:IO REF
3 RESET_N_SHLD 20A5< 20B5> 24A5<>
S1
BI SWSPSTPB
4
5 SILK=RESET SW
6 VIN D90553-001
7
8 1 2
CONN
G79625-001 C37 C13
0.1UF 1UF
10% 10%
25V 6.3V
X5R X5R
0402LF 0402LF
INTEL CORPORATION
2111 NE 25TH AVENUE
TITLE: GALILEO Gen2
AMUX & EXTERNAL IO REV: 2.0 SHEET 24 OF 28
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V3P3_S5
EN_V3P3_S5 25C6< EN_V1P5_S5 25B6< EN_V1P0_S5 25B6<
D 1
C2L7 C2M5 C45
4700PF 10NF 6800PF D
10% 10% 10% R4A2
2 50V 16V 25V
X7R X7R X7R 10K
0402LF 0402LF 0402LF 5%
CH
0402LF
VO = (R1/R2)*0.8 + 0.8
S5_PGOOD OUT 6A6< 6B6<
V5_ALW_ON MAX LOAD: 2.0A

V3P3_S5
C3B4 IHLP1212BZER2R2M11
V3V 1 2
U3A1 10UF 10% L3A1
C3B3 2.2UH 3A
1 1 1 TPS652510 V7V 1 2 1 1 2 2
PLACE CLOSE TO C2L8 C2L9 C2L12 DISCRETE
10UF 10UF 10UF 10UF 10% 1 1 1
INPUT PINS 10%
16V
10%
16V
10%
16V V3V 29 16V 0805LF 1 R3A16 1 C2L6
22UF
C2L11
22UF
C2L4
22UF
2 X5R 2 X5R 2 X5R 28 40.2K C3A11
0805LF 0805LF 0805LF V7V 1% 4700PF 20%
6.3V 2
20%
6.3V
20%
6.3V
PGOOD 27 2 CH 10% 2 X5R X5R 2 X5R
0402LF 50V R3A18 0805LF 0805LF 0805LF
C 2 X7R C
13 VIN1 COMP1 8 VR1_COMP1 25A8< 25C6<
VR1_FB1 1/16W 0402LF 1 2 C97875-001
SS1_1 9 SS1 LX1_1 14 12.7K 1%
RLIM1_1 10 RLIM1 LX1_2 15 BST_V3P3_S5 25C7< 0402LF CH
C3A18 2 25D7< EN_V3P3_S5 11 EN1 MAX LOAD: 1.3A
25C3<> BST_V3P3_S5 BST1_1 12 BST1 V1P5_S5
25C3< VR1_FB1 7 FB1
.047UF 10%
16V L2M1
X7R 18 VIN2 COMP2 23 VR1_COMP2 25A7< 2.2UH 3A
0603LF SS1_2 22 SS2 LX2_1 16 1 1 2 2
RLIM1_2 21 RLIM2 LX2_2 17 DISCRETE
1 C3A19 2 25D7< EN_V1P5_S5 20 EN2
C3B6 19 1 R2M4 1 1 1
4700PF 25B3<> BST_V1P5_S5 BST1_2 BST2 40.2K C2M6 C3B1 C3B7
10% 25B3< VR1_FB2 24 FB2 VR1 BST_V1P5_S5 25B7< 1% 4700PF 22UF 22UF
2 50V .047UF 10% 2 CH 10% 20% 20%
X7R 16V 50V 6.3V 6.3V
0402LF X7R 38 VIN3 COMP3 3 VR1_COMP3 25A6< 0402LF 2 X7R R2M6 2 X5R 2 X5R
0603LF SS1_3 2 SS3 LX3_1 36 25B6< VR1_FB2 1/16W 0402LF 1 2 0805LF 0805LF
RLIM1_3 RLIM3 LX3_2 37 45.3K 1%
1 1 C4A2 2 25D6< EN_V1P0_S5 40 EN3 0402LF CH
C3A14 C3A15 39
4700PF 4700PF 25B3<> BST_V1P0_S5 BST1_3 BST3 MAX LOAD: 2.1A
10% 10% 25B3< VR1_FB3 4 FB3 UC 5 V1P0_S5
2 50V 2 50V .047UF 10% UC 26
X7R X7R 16V
0402LF 0402LF X7R UC 30 L4B1
B 1 R3A21 0603LF 31 B
147K UC 2.2UH 3A
1% R3A19 UC 32 1 1 2 2
2 0402LF 1 2 ROSC_VR 6 ROSC UC 33 DISCRETE
180K 1% UC 34
0402LF R2M1 F_PWM 25 F_PWM UC 35 BST_V1P0_S5 25B7< 1 1
R2L19
NOTE: 1 R3B2
180K 0
0402LF
0
CH POWERPAD 41
40.2K
1%
C2L14
4700PF
10%
C3B9
22UF
20%
C3B11
22UF
20%
1% CH 50V 6.3V 6.3V
2 0402LF X7R 2 X5R 2 X5R
CURRENT LIMIT 1 R4A7 0402LF 0402LF R2L20 0805LF 0805LF
147K 25B6< VR1_FB3
V3P3_S5 @ 2.45A DC 1%
2 0402LF IC 158K 1%
V1P5_S5 @ 1.80A DC G43225-001 0402LF CH
V1P0_S0 @ 2.50A DC
A A
VR1_COMP1 25C4> VR1_COMP2 25C4> VR1_COMP3 25B4>

R3A22 R3B1 R3A23
1 2 VR1_COMP1_R 1 2 VR1_COMP2_R 1 2 VR1_COMP3_R
24.9K 1% 24.9K 1% 24.9K 1%
0402LF CH 0402LF CH 0402LF CH
1 C3A16 1 C3A12 1 C3B2 1 C3B8 1 C3A17 1 C3A13
10PF 1000PF 10PF 1000PF 10PF 1000PF
5% 10% 5% 10% 5% 10%
2 COG 2 X7R 2 COG 2 X7R 2 COG 2 X7R INTEL CORPORATION
0402LF 0402LF 0402LF 0402LF 0402LF 0402LF 2111 NE 25TH AVENUE
TITLE: GALILEO Gen2
VOLTAGE REGULATORS REV: 2.0 SHEET 25 OF 28
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V3P3_S5
V3P3_S0
V3P3_S5
V3P3_S3
U2L1 U2M1
TPS22920 TPS22920
C2L10 A2 A1 C2L5 A2 A1
D 1UF VIN1 VOUT1 1UF VIN1 VOUT1 C3B5
10% 10% 1UF D
6.3V B2 VIN2 VOUT2 B1 6.3V B2 VIN2 VOUT2 B1 10%
X5R C2L13 X5R 6.3V
V3P3_S5 IS GENERATED W ON-BRD REGULATOR 0402LF
C2 C1
1UF 0402LF
C2 C1
X5R
VIN3 VOUT3 10%
6.3V VIN3 VOUT3 0402LF
X5R
6A6> IN
S3_3V3_EN D2 ON GND D1 0402LF 6A6> IN
S0_3V3_EN D2 ON GND D1
R2L2 IC IC
10K R2L18
5% 10K
CH 5%
0402LF CH
0402LF
V1P5_S3 V1P5_S5
V1P5_S5
V1P5_S0
C C
U2A4 U2A2
TPS22920 C2A2 TPS22920
C2A5 1UF
1UF 10%
C2A4 A2 A1 6.3V A2 A1
1UF VIN1 VOUT1 10%
6.3V X5R VIN1 VOUT1
10% X5R 0402LF
6.3V B2 B1 B2 B1 C2A1
X5R VIN2 VOUT2 0402LF VIN2 VOUT2 1UF
0402LF 10%
C2 VIN3 VOUT3 C1 C2 VIN3 VOUT3 C1 6.3V
X5R
V1P5_S5 IS GENERATED W ON-BRD REGULATOR D2 D1 D2 D1
0402LF
28A8< 6A6> IN
S3_1V5_EN ON GND 28B7< 27C6< 6A6> IN
S0_1V5_EN ON GND
1
R2A7 IC R2A6 IC
10K 10K
5% 5%
V1P0_S5 IS GENERATED W ON-BRD REGULATOR CH CH
0402LF 0402LF
2
B B
CAD NOTE:
PLACE DECOUPLING CAPS AS CLOSE AS POSSIBLE TO SWITCH PINS
V1P0_S5
V1P0_S0
U5
C7 TPS22920
1UF
10%
V1P0_S3 IS GENERATED INTERNALLY V1P0_S0 IS GENERATED W ON-BRD REGULATOR
6.3V A2 VIN1 VOUT1 A1
X5R
0402LF C8
B2 VIN2 VOUT2 B1 1UF
10%
C2 VIN3 VOUT3 C1 6.3V
X5R
0402LF
A 28B8< 6A6< 6A6> IN
S0_1V0_EN D2 ON GND D1 A
28C5<
R9 IC
10K
5%
CH
0402LF
INTEL CORPORATION
2111 NE 25TH AVENUE
TITLE: GALILEO Gen2
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
V1P5_S0
V3P3_S5
V3P3_S5
VTT
1
D 1 1 R2A4 VCC_USB1
C1A2 C1A1 10K
V1P5_S3 10UF 10UF 5% D
10% 10% 1 U2A3
6.3V 6.3V C3L2 CH 1 1 1
X7R 2 2 X7R 4.7UF 0402LF C3L4 C3L3 C3L7
0805LF 0805LF 10% TPS51200 2 10UF 10UF 10UF
6.3V 2 10% 10% 10%
X5R 6.3V 6.3V 2 6.3V R48 V5_ALW_ON
1 0603LF X7R 2 2 X7R X7R
10 VIN PGOOD 9 PG_3P3_S5_NU 0805LF 0805LF 0805LF 1K
R4L9 VREF 5%
10K EMPTY C3B15
2 VLDOIN VO 3 0402LF 0.1UF
1% 10% U29
CH VOSNS 5 10V EMPTY
0402LF DS1 EMPTY TPS2552DRV-1
2 A93548-034 0402LF 6 1
REFIN_VTT_REG 1 REFIN REFOUT 6 RED IN OUT
EMPTY ILIM 2
1 8
GND REFOUT IS INDEPENDENT OF ENABLE PIN USB_PWR_FAULT_N 3 FAULT_N GND 5 R49
R3L1 1 28B7< 26B3< 6A6> IN
S0_1V5_EN 7 EN PGND 4 1 4 7 49.9K
10K C3L1 C2A3 EN_N THPAD 1%
1% 1000PF 0.1UF EMPTY
10% THP 11 10% H31893-001
CH 16V 0603LF
0402LF 2 50V
X7R 2 X7R R58
2 0402LF 0402LF 10K
A36096-046 IC 5%
E17764-001 EMPTY
0402LF
C
OPTION TO POWER FROM USB C
RECOMMENDED POWER SUPPLY:

X = TYPE OF BLADE. REFER TO DATASHEET
EMSA050300X P5P-SZ
VIN_POE V5_ALW_ON
1
VIN J4A3 D4
PWR_JACK schottky_diode
DB2W31900L
DISCRETE
1
1 1
3 3
D5
2 2 VIN VIN_D schottky_diode
DB2W31900L
C49 C50 C47 C35 CONN U6 DISCRETE
C4B4 C4B3 C18
2
0.1UF 0.1UF 0.1UF .01UF C46 TPS62130 L1
1
10% 10% 10% 10% 0.1UF 1UF D33700-002 10UF
B 10% 10% .01UF 10% 2.2UH 3A B
25V 25V 25V 25V 25V 25V NORMALLY CLOSED D3 10% 25V 11 PVIN_11 SW 1 V5_ALW_ON_L 1 1 2 2 V5_ALW_ON_D
EMPTY EMPTY X5R X7R schottky_diode 25V
0402LF 0402LF 0402LF 0402LF X5R
0402LF
X5R
0603LF DB2W31900L X7R X5R
0805LF
12 PVIN_12 SW_2 2 DISCRETE C21
0402LF 10 AVIN_10 SW_3 3 R19 22UF
DISCRETE 100K 10V
5%
2
VOS 14 CH 20%
13 EN 0402LF X5R
V5_ALW_ON PG 4 PG_V5_ALW_ON 0805
9 SS/TR
V5_ALW_ON
8 DEF FB 5 FB_V5_ALW_ON R53
57.6K R55
C10 C19 1% 54.9K
0.1UF 3300PF 7 FSW EPAD 17 EMPTY 1%
10% 6 CH
25V 10%
50V AGND 0402LF 0402LF
X5R EMPTY
1 1 C48 0402LF 15
C4B1
47UF
C4B2
47UF .01UF 0402LF PGND_15
1 20% 20% 10% PGND_16 16 R54
C3B13 16V 16V 25V 10.5K
1UF 2 X5R 2 X5R X7R
10% 0402LF 1 OF 1 1%
1210LF 1210LF CH
2 10V
X5R REV=1 IC 0402LF
0402LF
A A
INTEL CORPORATION
2111 NE 25TH AVENUE
TITLE: GALILEO Gen2
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE: RESET_N HAS AN INTERNAL PU TO V3P3_S3
D
SS: D
S1A1
REBOOT BUTTON SWSPSTPB
SW
D90553-001
1 2
RESET_N 6B6<
OUT VOH:2.25V
28B8< 26A8< 6A6< 6A6> S0_1V0_EN VOL:0.15V
IN
C4L1
1UF
10% R4A9
2 6.3V
X5R
330
5%
0402LF CH
0402LF
1/16W
CAD NOTE:
PLACE AT LED AREA DS4A1
C S0_1V0_EN_LED 2 C
GREEN
LED
26A8< 6A6< 6A6> S0_1V0_EN

28C5< IN
R16
24.9K V3P3_S5 V3P3_RTC
1%
CH
0402LF
B PG_V1P0_S0 OUT 6A6< B
R3A9
C11 0 0
0.1UF 0402LF EMPTY
10%
16V
X7R
0402LF
CR3A1
2 C52251-001
27C6< 26B3< 6A6> S0_1V5_EN
IN 3
BAT_DIO 1
R3A1
24.9K DIO
1% R3A11 BAT54C
1K C3A8 C3A9
CH 1% SOT23C .1UF .1UF SS:
0402LF CH 10% 10% V3P3_RTC
0402LF 2 16V 2 16V
S0_PGOOD 6A6< 6B6< EMPTY EMPTY
OUT 1/16W 0402LF 0402LF
26B5< 6A6> S3_1V5_EN
IN CAD NOTE:
C3A5
0.1UF
PUT THE SILKSCREEN
A 10% NEXT TO THE CAP A
R3A2 16V J3A1
24.9K X7R
1% 0402LF 1X2HDR
CH BAT_POS 1 2
0402LF
S3_PGOOD
OUT 6A6< CAD NOTE: HDR
PG DELAY LABEL "+" AND "-" TERMINALS ON 2 PIN HDR
C3A6
0.1UF
10%
16V OFF-BOARD BATTERY
X7R
0402LF
INTEL CORPORATION
PG DELAY 2111 NE 25TH AVENUE
TITLE: GALILEO Gen2
POWER BUTTONS & MISC REV: 2.0 SHEET 28 OF 28
8 7 6 5 4 3 2 1

Intel Galileo X1000 Gen 2

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Intel Galileo X1000 Gen 2

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CR-1 : @GALILEO_LIB.

1 DESIGN TITLE PAGE

DDR3 M_DQ<15..0> BI 10C3<> 11C3<>

DDR_PWROK OUT 5B7< 6A6>

DDR_ISYSPWRGOOD OUT 5B7< 6A6>

21C6< 19D4> OUT

7D4<> USBH0_DP_R R79 USBH0_DP BI 15C6<>

7C4<> USBH2_DP_R R78 USBH2_DP BI 15B6<>

IUSBCOMP_N18 K33 USBCOMP

TXD OUTPUT FROM QUARK

A7 VSS VSS AP23

12A8<> 11B6< 5D7> IN

12A8<> 10A6< 5D7> IN

11C6< 10B6< 5D7<> M_BS<2:0> VTT

13 36.5 R1A18 11B6< 10C3< 10B6< 5C7<> M_CK_N<0> R4L10

11B6< 10B6< 5D7> BI

11B6< 10A6< 5D7> BI

11B6< 10B6< 5C7<> BI

11B6< 10B6< 5B7<> BI

11B6< 10B6< 5C7<> BI

28 +1.5V PETP0 33 PCIE0_TX0_P OUT 5B2>

24 +3.3VAUX PERP0 25 PCIE0_RX0_P IN 5B7<

A V3P3_S3 KIT_PARTS=(LATCH: QTY=1) A

V3P3_S5 CR1 V3P3_S5

R2L1 R1L1 R1L3

V3P3_S0 V3P3_S0_A V3P3_S0_A

VA1 VDC 17A8<> VC4

D2 5 NC2 620 20%

5% ADJ GND 1/2W 17A8<> VC1

19D5> 6D7> SPI0_SCK 16 SCLK

R2B19 R2B17 R3A17

R4B6 R4B5 R3A14

BIT2 BIT1 BIT0

EC_PWRBTN_N OUT 6B6<

BIT1 BIT0 (LOW) POWER BUTTON NOT USED

22D2> 6C7<> MUX0_I0 3 I0 Y 4 MUX0_Y 21C3<

MUX0_SEL 6 2 C14 V3P3_S5

21B4> MUX5_Y 3 I0 Y 4 MUX4_Y 22B8<

V3P3_S5 22B2> 6C7<> MUX5_I0 3 I0 Y 4 MUX5_Y 21C5<

22A2> 6B7<> MUX7_I0 3 I0 Y 4 MUX7_Y 22B8<

2 3 MUX0_I0 OUT 6C7<> 21D8<

LVL_B_OE1_N 20C7< 20D6> 22C7<

LVL_B_OE6_N 20C6> 20C7< 22B7<

LVL_B_OE7_N 20C6> 20C7< 22B7<

2 3 UART0_RXD 6B7< 7B7< 23C7<

LVL_C_OE1_N 20A7< 20C4> 23C5<

R2A3 LVL_C_OE5_N 20A7< 20C3> 23C5<

EN_V3P3_S5 25C6< EN_V1P5_S5 25B6< EN_V1P0_S5 25B6<

V5_ALW_ON MAX LOAD: 2.0A

VR1_COMP1 25C4> VR1_COMP2 25C4> VR1_COMP3 25B4>

RECOMMENDED POWER SUPPLY:

NOTE: RESET_N HAS AN INTERNAL PU TO V3P3_S3

26A8< 6A6< 6A6> S0_1V0_EN

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