UNIVERSIDADNACIONALMAYORDESANMARCOS

FACULTADDEINGENIERAELECTRNICA
ESCUELADEINGENIERAELECTRNICA

DISEODIGITAL

LABORATORIONo2

USODEL:

1. PROCESS(VHDL)
2. always@(VerilogHDL)

PARAELDISEODEELEMENTOSDEMEMORIA,REGISTROSY
CONTADORES







Profesor:AlfredoGranadosLy
 1. ImplementacindeunflipfloptipoDenVHDL

Libraryieee
Useieee.std_logic_1164.all

Entityff_dis
Port( D:instd_logic
Clk:instd_logic
Q:outstd_logic)
Endff_d

Architecturealgoritmoofff_dis
Begin
Process(clk)
Begin
Ifclk=1then
Q<=D
Endif
Endprocess
Endalgoritmo

2. ImplementacindeunLatchtipoDenVHDL.

libraryIEEE
useIEEE.STD_LOGIC_1164.ALL

entitylatch_dis
Port(d:instd_logic
clk:instd_logic
q:outstd_logic)
endlatch_d

architectureBehavioraloflatch_dis
begin
process(clk,d)
begin
ifclk='1'then
q<=d
 endif
endprocess
endBehavioral

3. ImplementacindeunFlipFlopDconClearyPresetasncronaenVHDL

libraryIEEE
useIEEE.STD_LOGIC_1164.ALL

entityflip_flop_cpis
Port(clear:instd_logic
preset:instd_logic
clk:instd_logic
d:instd_logic
q:outstd_logic)
endflip_flop_cp

architectureBehavioralofflip_flop_cpis
begin
process(clk,clear,preset)
begin
ifclear='1'then
q<='0'
elsifpreset='1'then
q<='1'
elsifclk='1'andclk'eventthen
q<=d
endif
endprocess
endBehavioral

Nota:proponerundiagramadetiempoparalasimulacindeestecircuito.

 4. Registrodeentrada/salidaparalelaconcargasncronaenVHDL.

libraryIEEE
useIEEE.STD_LOGIC_1164.ALL
entityregistro_pipois
Port(data:instd_logic_vector(7downto0)
load:instd_logic
clk:instd_logic
q:outstd_logic_vector(7downto0))
endregistro_pipo
architectureBehavioralofregistro_pipois
begin
process(clk)
begin
ifclk='1'andclk'eventthen
ifload='1'then
q<=data
endif
endif
endprocess
endBehavioral

Nota:proponerundiagramadetiempoparalasimulacindeestecircuito.

5. Contadorbinario4bitsporflancodesubidaenVHDL.

libraryIEEE
useIEEE.STD_LOGIC_1164.ALL
useIEEE.STD_LOGIC_ARITH.ALL
useIEEE.STD_LOGIC_UNSIGNED.ALL

entitycontadoris
Port(clk:instd_logic
q:bufferstd_logic_vector(3downto0))
endcontador
architectureBehavioralofcontadoris
begin
process(clk)
begin
ifclk='1'andclk'eventthen
q<=q+1
endif
endprocess
endBehavioral

Nota:proponerundiagramadetiempoparalasimulacindeestecircuito.
 6. Contadorbinario4bitsconCLEARyLOADasncronadedatosenVHDL.

libraryIEEE
useIEEE.STD_LOGIC_1164.ALL
useIEEE.STD_LOGIC_ARITH.ALL
useIEEE.STD_LOGIC_UNSIGNED.ALL

entitycontador_clear_loadis
Port(data:instd_logic_vector(3downto0)
load:instd_logic
clear:instd_logic
clk:instd_logic
q:bufferstd_logic_vector(3downto0))
endcontador_clear_load

architectureBehavioralofcontador_clear_loadis
begin
process(data,load,clear,clk)
begin
ifclear='1'then
q<="0000"
elsifload='1'then
q<=data
elsifclk='1'andclk'eventthen
q<=q+1
endif
endprocess
endBehavioral

Nota:proponerundiagramadetiempoparalasimulacindeestecircuito.

7. Circuitosapresentarcomoinformefinal:

FlipFloptipoT.
Registrode8bitsconentradaparalelaysalidaserial.
Registrode8bitsconentradaserialysalidaparalela.
Registrode8bitsconentradaserialysalidaserial.
ContadordeBCDde4bits.
Generadorcdigograyde4bits.
Contadorde4bitsconcontroldecuanta:up(0)down(1)
ContadordeBCDde8bitsconhabilitadoryreset.

 8. ImplementacindeunflipfloptipoDenVerilogHDL

moduleffd_v(clk,d,q)
inputclk,d
outputq
regq

always@(posedgeclk)
q<=d

endmodule

9. ImplementacindeunLatchtipoDenVerilogHDL.

modulelatchd_v(clk,d,q)
inputclk,d
outputq
regq

always@(clkord)
if(clk)
q=d

endmodule

10. Implementacin de un FlipFlop D con Clear y Preset asincrona en Verilog

HDL

moduleffd_cp(clk,d,clr,pre,q)
inputclk,d,clr,pre
outputq
regq

always@(posedgeclkorposedgeclrorposedgepre)
if(clr)
q=0
elseif(pre)
q=1
else
q=d

endmodule


11. Registrodeentrada/salidaparalelaconcargasncronaenVerilogHDL.

modulereg8ld_v(clk,load,data,q)
inputclk,load
input[7:0]data
output[7:0]q
reg[7:0]q

always@(posedgeclk)
if(load)
q=data

endmodule

12. Contadorbinario4bitsporflancodesubidaenVerilogHDL.

moduleconta4_v(clk,q)
inputclk
output[3:0]q
reg[3:0]q

always@(posedgeclk)
q=q+1

endmodule

13. Contador binario 4 bits con CLEAR y LOAD asncrona de datos en Verilog
HDL.

moduleconta4clrld_v(clk,clr,load,data,q)
inputclk,clr,load
input[3:0]data
output[3:0]q
reg[3:0]q

always@(posedgeclkorposedgeclrorposedgeload)
if(clr)
q=0
elseif(load)
q=data
else
q=q+1

endmodule