EJEMPLO 3.

3: SUMADOR
En la figura 3.3 se muestra el diagrama de un sumador de 4 bits. El circuito
tiene dos entradas (a, b) y una salida (sum). Se presentan dos soluciones.
En la primera, todas las entradas son de tipo SIGNED, mientras que en la
segunda todas las salidas son de tipo INTEGER. Nota que en la solucin 2
que se us una conversin de funcin en la lnea 13, para una tipo de a + b
de la suma. Notar tambin que la inclusin del paquete std_logic_arith
(lnea 4 de cada solucin), el cual se especifica el tipo de dato SIGNED.
Volver a llamar un valor SIGNED es representado como un vector, esto es,
similar a STD_LOGIC_VECTOR, no como un INTEGER.

Figura 3.3A Circuito para el ejemplo 3.3

SOLUCION DEL EJEMPLO 3.3.
PRIMERA SOLUCION:
Cdigo usado en el ISE 12.1
---------------------------------------------------------------------------------- Company: UNSA 2014
-- Engineer: EPIE 2014B
--- Create Date:
09:47:35 10/06/2014
-- Design Name:
-- Module Name:
SUMADOR - Behavioral
-- Project Name:
-- Target Devices: SPARTAN 3E
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- INTEGRANTES:
-* LLANQUECHA ARQQUE, DENNYS MARTIN
-* VELA VELARDE, VICTOR UZIEL
----------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using

-- Arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- Any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SUMADOR is
Port ( a : in SIGNED (3 DOWNTO 0);
b : in SIGNED (3 DOWNTO 0);
sum : out SIGNED (4 DOWNTO 0));
end SUMADOR;
architecture Behavioral of SUMADOR is
begin
sum <= a + b;
end Behavioral;
CODIGO DEL TESTBENCH:
----------------------------------------------------------------------- Company:
UNSA
-- Engineer:
EPIE-UNSA 2014B
--- Create Date:
09:49:32 10/06/2014
-- Design Name:
-- Module Name:
E:/M_S/SUMADOR/SUMADOR_TB.vhd
-- Project Name: SUMADOR
-- Target Device:
-- Tool versions:
-- Description:
--- VHDL Test Bench Created by ISE for module: SUMADOR
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--- Notes:
-- This testbench has been automatically generated using types
std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx
recommends
-- that these types always be used for the top-level I/O of a design
in order
-- to guarantee that the testbench will bind correctly to the postimplementation
-- simulation model.
--------------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY SUMADOR_TB IS
END SUMADOR_TB;
ARCHITECTURE behavior OF SUMADOR_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SUMADOR
PORT(
a : IN SIGNED (3 DOWNTO 0);
b : IN SIGNED (3 DOWNTO 0);
sum : OUT SIGNED (4 DOWNTO 0)
);
END COMPONENT;

--Inputs
signal a : SIGNED (3 DOWNTO 0) := (others => '0');
signal b : SIGNED (3 DOWNTO 0) := (others => '0');
--Outputs
signal sum : SIGNED (4 DOWNTO 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
--constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SUMADOR PORT MAP (
a => a,
b => b,
sum => sum
);
stim_proc: PROCESS
BEGIN
a <=
wait
a <=
wait

"0000" ;
for 50 ns;
"1111" ;
for 350 ns;

b <= "0100" ;
wait for 50 ns;
b <= "1111" ;
wait for 150 ns;
-- b <= "0100" after 50 ns, "1100" after 500 ns, "1011" after 400 ns;
END PROCESS;
-- Stimulus process
END;

SIMULACION:

SEGUNDA SOLUCION:

Figura 3.3B Circuito para el ejemplo 3.3m, sumador de 4 bits

CODIGO USADO EN LA SOLUCION:

----------------------------------------------------------------------- Company:
UNSA
-- Engineer:
EPIE-UNSA 2014B
--- Create Date:
09:31:12 10/06/2014
-- Design Name:
-- Module Name:
SUMADOR - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- INTEGRANTES:
* LLANQUECHA ARQQUE, DENNYS MARTIN
* VELA VELARDE, VICTOR UZIEL
---------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SUMADOR
Port ( a :
b :
sum
end SUMADOR;

is
in SIGNED (3 DOWNTO 0);
in SIGNED (3 DOWNTO 0);
: out INTEGER RANGE -16 TO 15);

architecture Behavioral of SUMADOR is

begin
sum <= CONV_INTEGER( a + b );
end Behavioral;
CODIGO DEL TESTBENCH:
ENTITY SUMADOR2_TB IS
END SUMADOR2_TB;
ARCHITECTURE behavior OF SUMADOR2_TB IS
-- Component Declaration for the Unit under Test (UUT)
COMPONENT SUMADOR
PORT (
a: IN SIGNED (3 DOWNTO 0);
b: IN SIGNED (3 DOWNTO 0);
sum: OUT INTEGER RANGE -16 TO 15
);
END COMPONENT;
--Inputs
signal a : SIGNED (3 DOWNTO 0) := (others => '0');
signal b : SIGNED (3 DOWNTO 0) := (others => '0');
--Outputs
signal sum : INTEGER RANGE -16 TO 15;
-- No clocks detected in port list. Replace <clock> below with
-- Appropriate port name

BEGIN
-- Instantiate the Unit under Test (UUT)
uut: SUMADOR PORT MAP (
a => a,
b => b,
sum => sum
);
-- Clock process definitions
a <= "0000" after 0 ns , "1010" after 50 ns , "1111" after 100
ns ,"1010" after 150 ns , "1111" after 200 ns ,"1010" after 250 ns ,
"1111" after 300 ns ;
b <= "0000" after 0 ns , "1111" after 50 ns , "0000" after 100 ns ,
"1111" after 150 ns , "0000" after 200 ns, "1111" after 250 ns ,
"0000" after 300 ns;
END;

SIMULACION: