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Circuito para La Prueba Potencia Tiempo de Los Medidores Electricos Estaticos
Circuito para La Prueba Potencia Tiempo de Los Medidores Electricos Estaticos
Habilitar el
Circuito
Conteo
Temporizacion
Previamente
ajustado 10/ 20 seg
Calculadora para el
no si
T =10
seg
Parar conteo
DISEÑO DE PLACA BASE
SIMULACION DEL CIRCUITO A TRAVES DEL MULTISIM
CONTADOR 74190
http://www.datasheetcatalog.org/datasheets/560/334560_DS.pdf
Group(ANSI) Group(DIN)
Family(ANSI) Family(DIN)
Symbol(ANSI) Symbol(DIN)
################## Model ##################
Model ID : 74190
Model manufacturer : Texas Instruments
Model template :
a%p [%tCLK?%t:d%t;CLK
+ %t~CTEN?%t:d%t;~CTEN
+ %t~U/D?%t:d%t;~U/D
+ %t~LOAD?%t:d%t;~LOAD
+ %tA?%t:d%t;A
+ %tB?%t:d%t;B
+ %tC?%t:d%t;C
+ %tD?%t:d%t;D]
+ [%tQA?%t:d%t;QA
+ %tQB?%t:d%t;QB
+ %tQC?%t:d%t;QC
+ %tQD?%t:d%t;QD
+ %t~RCO?%t:d%t;~RCO
+ %tMAX/MIN?%t:d%t;MAX/MIN] %m
Model data :
Footprint:
Pins information :
Logical Physical Section Type ERC Status Pin Swap Group Gate Swap
Group
A 15 GRP:A D:INPUT:TTL_RCV INCLUDE
B 1 GRP:A D:INPUT:TTL_RCV INCLUDE
C 10 GRP:A D:INPUT:TTL_RCV INCLUDE
D 9 GRP:A D:INPUT:TTL_RCV INCLUDE
~U/D 5 GRP:A D:INPUT:TTL_RCV INCLUDE
QA 3 GRP:A D:OUTPUT:TTL_DRV INCLUDE
QB 2 GRP:A D:OUTPUT:TTL_DRV INCLUDE
QC 6 GRP:A D:OUTPUT:TTL_DRV INCLUDE
QD 7 GRP:A D:OUTPUT:TTL_DRV INCLUDE
~CTEN 4 GRP:A D:INPUT:TTL_RCV INCLUDE
~LOAD 11 GRP:A D:INPUT:TTL_RCV INCLUDE
~RCO 13 GRP:A D:OUTPUT:TTL_DRV INCLUDE
MAX/MIN 12 GRP:A D:OUTPUT:TTL_DRV INCLUDE
CLK 14 GRP:A D:INPUT:TTL_RCV INCLUDE
GND 8 PWR:V0 D:GND INCLUDE
VCC 16 PWR:V1 D:VCC INCLUDE
TIMERS 555
http://www.datasheetcatalog.org/datasheet/nationalsemiconductor/DS007851.PDF
################## Component Detail Report ##################
Group(ANSI) Group(DIN)
Family(ANSI) Family(DIN)
Symbol(ANSI) Symbol(DIN)
################## Model ##################
Model ID : LM555
Model manufacturer : Generic
Model template : x%p %tGND %tTRI %tOUT %tRST %tCON %tTHR %tDIS
%tVCC %m
Model data :
.subckt LM555 0 2 3 4 5 6 7 8
rn1 8 5 5k
rn2 5 51 5k
rn3 51 0 5k
aop1 %vd(5 6) 56 op
aop2 %vd(2 51) 52 op
.model op limit (gain= 3000,
+ out_upper_limit=5,
+ out_lower_limit=-5,
+ limit_range=1 fraction=true)
aadc1 [56 52] [r s] ADC1
.MODEL ADC1 adc_bridge (in_low= 2.5 in_high = 2.5 rise_delay= 1e-12 fall_delay=
1e-12)
anand1 [r Q2] Q1 nand1
anand2 [s Q1] Q2 nand1
.model nand1 d_nand(rise_delay=1n)
adac1 [q1 q2] [66 62] DAC1
rad3 66 0 1
rad4 62 0 1
aadc4 [4] [40] ADC1
ainv2 40 41 inv1
adlatch q1 2u 41 3d Qb Qc dlt
.model dlt d_dlatch(rise_delay=1e-12)
apu1 2u pullup1
.model pullup1 d_pullup(load=10e-12)
apd1 3d pulldown1
.model pulldown1 d_pulldown(load=10e-12)
ainv1 Qb 31 inv1
.model inv1 d_inverter(rise_delay=1e-12)
adac72 [Qb] [72] DAC1
adac31 [31] [32] DAC1
r30 32 0 1g
b1 333 0 v=(v(32)*v(8)/5)
r3 333 0 1g
aslew %vd(333 0) %vd(3 0) Slew_Rate_Block
.MODEL Slew_Rate_Block slew(
+ rise_slope=10e+6
+ fall_slope=10e+6)
.MODEL DAC1 dac_bridge (out_low= 0.0 out_high= 5.0 out_undef=0.5)
rad5 72 0 1meg
rdisb 71 72 1
qdis 7 71 0 qdis
.MODEL qdis npn ().
################## Package ##################
Footprint:
Pins information :
Logical Physical Section Type ERC Status Pin Swap Group Gate Swap Group
GND 1 GRP:A A:GND INCLUDE
DIS 7 GRP:A A:INPUT INCLUDE
OUT 3 GRP:A A:OUTPUT INCLUDE
RST 4 GRP:A A:INPUT INCLUDE
VCC 8 GRP:A A:PWR INCLUDE
THR 6 GRP:A A:INPUT INCLUDE
CON 5 GRP:A A:INPUT INCLUDE
TRI 2 GRP:A A:INPUT INCLUDE
LISTADO DE MATERIALES
1 LM555CM TIMERS
2 74190N CONTADOR
1 CONTENEDOR CONTENEDOR
1 5.1kOhm 5% RESISTENCIA
1 200kOhm 5% RESISTENCIA
1 3MOhm 5% RESISTENCIA
2 220Ohm 5% RESISTENCIA
1 20 uf CAPACITOR
1 100nf CAPACITOR
1 PULSADOR NO PULSADOR