5 4 3 2 1

D
Enrico 14 D

Muxless Discrete/UMA Schematics Document

AMD Ontario CPU FT1
AMD GPU Seymour XT
FCH HUDSON M1
C C

PCB :10265
2010-04-21
REV : A00
B B

DY :None Installed
UMA:UMA and Muxless platform installed
DIS_PX:DIS and Muxless platform installed
PSL:10mW internal schematic
10mW: 10mW schematic installed
A Surge: Surege schematic installed <Variant Name> A

GIGA: GIGA schematic installed

10/100: 10/100 schematic installed Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
ROB: ROBOSON GPU installed
Title
Cover Page
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 1 of 109
5 4 3 2 1
 5 4 3 2 1

CHARGER
BQ24707 40
Project code : 91.4IU01.001 INPUTS OUTPUTS
PCB P/N :
AMD Brazos UMA/Discrete Block Diagram AD+
DCBATOUT
28,29

BT+
Revision : 10265-1 SYSTEM DC/DC
DDRIII DIMM1 TPS51125A 41
D DDR III 1333 D
1066MHZ INPUTS OUTPUTS 30
14,15
AMD APU-Ontario 3D3V_AUX_S5
RGB CRT (FT1 BGA 413-Ball) 5V_AUX_S5
CRT DDRIII DIMM2 DCBATOUT
50 5V_S5
1066MHZ 14,15
PCIe GPPs (4 parts) 3D3V_S5
27
DP0 (DP/HDMI/DVI/LVDS)
LVDS APU Core/NB Power
DP1 (DP/HDMI/DVI) DP0 42, 43
ISL6265CHRTZ-T
AMD dGPU 49
INPUTS OUTPUTS
31

PCIe x 4 Gen 2(Muxless)

Seymour-XT 4,5,6,7,8
DP1
HDMI APU_VDD
VRAM DCBATOUT
51 APU_VDDNB
83,84,85,86,87
gDDR3
64M*16b*4(512MB)/128M*16b*4(1024MB) DDRIII SUS
x4 UMI(Gen 1) TPS51216RUKR 44
INPUTS OUTPUTS
C
10/100 DCBATOUT 1D5V_S3 C
CardReader RJ45
PCIE x 1 Realtek
31
DDRIII VTT
SD/MMC/MS RTL8105 CONN 59 TPS51216RGER 44
Realtek USB2.0
74
RTS5138 FCH INPUTS OUTPUTS
32
Hudson-M1 DCBATOUT 0D75V_S0
APU VDDR/VDDP
USB 2.0 (14 parts) PCIE x 1 Mini-Card/Bluetooth TPS51218 46
USB 2.0 x 1 INPUTS OUTPUTS
USB 1.1 (2 parts) 802.11a/b/g
65
Internal Analog MIC AZALIA SATA III(6 parts), 6Gb/s DCBATOUT 1D1V_S5
Azalia INT CLK GEN AMD APU/FCH CORE Power
USB 2.0 x 3
MIC IN CODEC HW MONITOR
Right Side:
USB x3
TPS51218 46
ACPI 1.1 61 INPUTS OUTPUTS 33
& USB 2.0 x 1 CAMERA DCBATOUT 1V_S0
HP OUT
OP AMP (Option) 49 AMD GPU CORE
B IDT 92HD87B1 USB 2.0 RT8208BGQW 26 92 B
29 INPUTS OUTPUTS
LPC Bus DCBATOUT VGA_CORE
2CH SPEAKER AMD GPU CORE
RT8015B 26 47
17,18,19,20,21,22
INPUTS OUTPUTS
3D3V_S5 1D8V_S0

PCB LAYER
KBC L1: Top
SATA II

SATA II

SPI NUVOTON L2: VCC

27
NPCE795P L3: Signal
L4: Signal
L5: GND
<Core Design>
L6: Bottom
A A
Flash ROM Touch Int. Thermal
HDD ODD Wistron Corporation
56 56 2MB PAD KB P2800
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
60 69 69 25 28 Taipei Hsien 221, Taiwan, R.O.C.

Title

Fan Block Diagram

Size Document Number Rev
P2793 58 A3 Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 2 of 109

5 4 3 2 1 28
28
 5 4 3 2 1

REQUIRED SYSTEM STRAPS

D
AZ_SDOUT PCI_CLK1 CLK_PCI_LPC PCI_CLK4 TYPE EC_PWM2 EC_PWM3 D
LPC_CLK0 LPC_CLK1 LPC_CLK2
ENABLED
PULL LOW POWER Allow USE non_Fusion CLKGEN Enable
HIGH MODE PCIE GEN2 DEBUG CLOCK mode ENABLE EC ENABLED boot timer Reserved 2.2-kohm 5% pull-down 2.2-kohm 5% pull-down
STRAPS (Use Internal) function
DEFAULT DEFAULT

PERFORMANCE Force IGNORE Fusion DISABLE EC CLKGEN Disable boot LPC ROM Not connected. 2.2-kohm 5% pull-down
PULL
MODE PCIE GEN1 DEBUG CLOCK mode DISABLED fail timer
LOW
STRAPS function
DEFAULT DEFAULT
DEFAULT DEFAULT (Use External) DEFAULT
SPI ROM 2.2-kohm 5% pull-down Not connected.

Reserved Not connected. Not connected.

Note: EC_PWM2, EC_PWM3 default have internal 10kohm PU.

C C

USB Table PCIe Routing

APU
Pair USB Device
0 USB 2.0 EXT.Port1 LANE0 LAN
1 Mini Card1 (WLAN)
LANE1 WWAN
2 USB 2.0 EXT.Port1
3 NC LANE2 WLAN
4 NC
LANE3 CardReader
5 NC
6 USB 2.0 EXT.Port1
7 CCD Camera
B B
8 NEWCARD
9 Card Reader
10 NC
11 NC
12 NC
13 NC

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Table of Content
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 3 of 109
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

D D

APU1A 1 OF 5
PEG_C_TXP0 C401 1
DIS_PX
83 PEG_RXP0 AA6 P_GPP_RXP0 ONTARIO_FT1 P_GPP_TXP0 AB6 2 SCD1U10V2KX-5GP PEG_TXP0 83
83 PEG_RXN0 Y6 AC6 PEG_C_TXN0C402 DIS_PX
1 2 SCD1U10V2KX-5GP
P_GPP_RXN0 P_GPP_TXN0 PEG_TXN0 83

83 PEG_RXP1 AB4 AB3 PEG_C_TXP1 C403 DIS_PX

1 2 SCD1U10V2KX-5GP
P_GPP_RXP1 P_GPP_TXP1 PEG_TXP1 83
83 PEG_RXN1 AC4 AC3 PEG_C_TXN1C404 DIS_PX
1 2 SCD1U10V2KX-5GP
P_GPP_RXN1 P_GPP_TXN1 PEG_TXN1 83

83 PEG_RXP2 AA1 Y1 PEG_C_TXP2 C405 DIS_PX

1 2 SCD1U10V2KX-5GP
P_GPP_RXP2 P_GPP_TXP2 PEG_TXP2 83
83 PEG_RXN2 AA2 Y2 PEG_C_TXN2C406 DIS_PX
1 2 SCD1U10V2KX-5GP
P_GPP_RXN2 P_GPP_TXN2 PEG_TXN2 83
Y4 V3 PEG_C_TXP3 C407 DIS_PX
1 2 SCD1U10V2KX-5GP

PCIE I/F
83 PEG_RXP3 P_GPP_RXP3 P_GPP_TXP3 PEG_TXP3 83
83 PEG_RXN3 Y3 V4 PEG_C_TXN3C408 DIS_PX
1 2 SCD1U10V2KX-5GP
P_GPP_RXN3 P_GPP_TXN3 PEG_TXN3 83

1V_S0 R401 1 2 P_ZVDDP Y14 AA14 P_ZVSS 1 R402 2

2KR2F-3-GP P_ZVDD_10 P_ZVSS 1K27R2F-L-GP

17 UMI_FCH_APU_RX0P AA12 AB12 UMI_TX0P_C C409 1 2 SCD1U10V2KX-5GP

P_UMI_RXP0 P_UMI_TXP0 UMI_APU_FCH_TX0P 17
17 UMI_FCH_APU_RX0N Y12 AC12 UMI_TX0N_C C410 1 2 SCD1U10V2KX-5GP
C P_UMI_RXN0 P_UMI_TXN0 UMI_APU_FCH_TX0N 17 C

17 UMI_FCH_APU_RX1P AA10 AC11 UMI_TX1P_C C411 1 2 SCD1U10V2KX-5GP

P_UMI_RXP1 P_UMI_TXP1 UMI_APU_FCH_TX1P 17
17 UMI_FCH_APU_RX1N Y10 AB11 UMI_TX1N_C C412 1 2 SCD1U10V2KX-5GP
P_UMI_RXN1 P_UMI_TXN1 UMI_APU_FCH_TX1N 17
UMI_TX2P_C C413 1 2 SCD1U10V2KX-5GP

UMI I/F
17 UMI_FCH_APU_RX2P AB10 P_UMI_RXP2 P_UMI_TXP2 AA8 UMI_APU_FCH_TX2P 17
17 UMI_FCH_APU_RX2N AC10 Y8 UMI_TX2N_C C414 1 2 SCD1U10V2KX-5GP
P_UMI_RXN2 P_UMI_TXN2 UMI_APU_FCH_TX2N 17

17 UMI_FCH_APU_RX3P AC7 AB8 UMI_TX3P_C C415 1 2 SCD1U10V2KX-5GP

P_UMI_RXP3 P_UMI_TXP3 UMI_APU_FCH_TX3P 17
17 UMI_FCH_APU_RX3N AB7 AC8 UMI_TX3N_C C416 1 2 SCD1U10V2KX-5GP
P_UMI_RXN3 P_UMI_TXN3 UMI_APU_FCH_TX3N 17
ONTARIO-FT1-GP

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

APU_PCIE(1/5)
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 4 of 109

5 4 3 2 1
 5 4 3 2 1

APU1E 5 OF 5
R17 B14
SSID = CPU 14,15
14,15
14,15
M_A0
M_A1
M_A2
H19
J17
M_ADD0
M_ADD1
M_ADD2
ONTARIO_FT1
M_DATA0
M_DATA1
M_DATA2
A15
A17
M_DQ0
M_DQ1
M_DQ2
14,15
14,15
14,15
14,15 M_A3 H18 M_ADD3 M_DATA3 D18 M_DQ3 14,15
14,15 M_A4 H17 M_ADD4 M_DATA4 A14 M_DQ4 14,15
14,15 M_A5 G17 M_ADD5 M_DATA5 C14 M_DQ5 14,15
14,15 M_A6 H15 M_ADD6 M_DATA6 C16 M_DQ6 14,15
14,15 M_A7 G18 M_ADD7 M_DATA7 D16 M_DQ7 14,15
14,15 M_A8 F19 M_ADD8
14,15 M_A9 E19 M_ADD9 M_DATA8 C18 M_DQ8 14,15
14,15 M_A10 T19 M_ADD10 M_DATA9 A19 M_DQ9 14,15
14,15 M_A11 F17 M_ADD11 M_DATA10 B21 M_DQ10 14,15
D 14,15 M_A12 E18 M_ADD12 M_DATA11 D20 M_DQ11 14,15 D
14,15 M_A13 W17 M_ADD13 M_DATA12 A18 M_DQ12 14,15
14,15 M_A14 E16 M_ADD14 M_DATA13 B18 M_DQ13 14,15
14,15 M_A15 G15 M_ADD15 M_DATA14 A21 M_DQ14 14,15
M_DATA15 C20 M_DQ15 14,15
14,15 M_BS0 R18 M_BANK0
14,15 M_BS1 T18 M_BANK1 M_DATA16 C23 M_DQ16 14,15
14,15 M_BS2 F16 M_BANK2 M_DATA17 D23 M_DQ17 14,15
M_DATA18 F23 M_DQ18 14,15
14,15 M_DM0 D15 M_DM0 M_DATA19 F22 M_DQ19 14,15
14,15 M_DM1 B19 M_DM1 M_DATA20 C22 M_DQ20 14,15
14,15 M_DM2 D21 M_DM2 M_DATA21 D22 M_DQ21 14,15
14,15 M_DM3 H22 M_DM3 M_DATA22 F20 M_DQ22 14,15
14,15 M_DM4 P23 M_DM4 M_DATA23 F21 M_DQ23 14,15
14,15 M_DM5 V23 M_DM5
14,15 M_DM6 AB20 M_DM6 M_DATA24 H21 M_DQ24 14,15
14,15 M_DM7 AA16 M_DM7 M_DATA25 H23 M_DQ25 14,15
M_DATA26 K22 M_DQ26 14,15
14,15 M_DQS0 A16 M_DQS_H0 M_DATA27 K21 M_DQ27 14,15
14,15 M_DQS#0 B16 M_DQS_L0 M_DATA28 G23 M_DQ28 14,15
14,15 M_DQS1 B20 M_DQS_H1 M_DATA29 H20 M_DQ29 14,15
14,15 M_DQS#1 A20 M_DQS_L1 M_DATA30 K20 M_DQ30 14,15
14,15 M_DQS2 E23 M_DQS_H2 M_DATA31 K23 M_DQ31 14,15
14,15 M_DQS#2 E22 M_DQS_L2
14,15 M_DQS3 J22 M_DQS_H3 M_DATA32 N23 M_DQ32 14,15
J23 P21

MEMORY
14,15 M_DQS#3 M_DQS_L3 M_DATA33 M_DQ33 14,15
14,15 M_DQS4 R22 M_DQS_H4 M_DATA34 T20 M_DQ34 14,15
14,15 M_DQS#4 P22 M_DQS_L4 M_DATA35 T23 M_DQ35 14,15
14,15 M_DQS5 W22 M_DQS_H5 M_DATA36 M20 M_DQ36 14,15

I/F
C V22 P20 C
14,15 M_DQS#5 M_DQS_L5 M_DATA37 M_DQ37 14,15
14,15 M_DQS6 AC20 M_DQS_H6 M_DATA38 R23 M_DQ38 14,15
14,15 M_DQS#6 AC21 M_DQS_L6 M_DATA39 T22 M_DQ39 14,15
14,15 M_DQS7 AB16 M_DQS_H7
14,15 M_DQS#7 AC16 M_DQS_L7 M_DATA40 V20 M_DQ40 14,15
M_DATA41 V21 M_DQ41 14,15
14 M_DIM0_CLK_DDR0 M17 M_CLK_H0 M_DATA42 Y23 M_DQ42 14,15
14 M_DIM0_CLK_DDR#0 M16 M_CLK_L0 M_DATA43 Y22 M_DQ43 14,15
14 M_DIM0_CLK_DDR1 M19 M_CLK_H1 M_DATA44 T21 M_DQ44 14,15
14 M_DIM0_CLK_DDR#1 M18 M_CLK_L1 M_DATA45 U23 M_DQ45 14,15
15 M_DIM0_CLK_DDR2 N18 M_CLK_H2 M_DATA46 W23 M_DQ46 14,15
15 M_DIM0_CLK_DDR#2 N19 M_CLK_L2 M_DATA47 Y21 M_DQ47 14,15
15 M_DIM0_CLK_DDR3 L18 M_CLK_H3
15 M_DIM0_CLK_DDR#3 L17 M_CLK_L3 M_DATA48 Y20 M_DQ48 14,15
M_DATA49 AB22 M_DQ49 14,15
14,15 M_RST# L23 M_RESET# M_DATA50 AC19 M_DQ50 14,15
M_EVENT# N17 AA18
M_EVENT# M_DATA51 M_DQ51 14,15
M_DATA52 AA23 M_DQ52 14,15
M_DATA53 AA20 M_DQ53 14,15
14,15 M_DIM0_CKE0 F15 M_CKE0 M_DATA54 AB19 M_DQ54 14,15
14,15 M_DIM0_CKE1 E15 M_CKE1 M_DATA55 Y18 M_DQ55 14,15

M_DATA56 AC17 M_DQ56 14,15

M_DATA57 Y16 M_DQ57 14,15
14 M_A_DIM0_ODT0 W19 M0_ODT0 M_DATA58 AB14 M_DQ58 14,15
14 M_A_DIM0_ODT1 V15 M0_ODT1 M_DATA59 AC14 M_DQ59 14,15
15 M_B_DIM0_ODT0 U19 M1_ODT0 M_DATA60 AC18 M_DQ60 14,15
15 M_B_DIM0_ODT1 W15 M1_ODT1 M_DATA61 AB18 M_DQ61 14,15
M_DATA62 AB15 M_DQ62 14,15
B B
14 M_A_DIM0_CS#0 T17 M0_CS#0 M_DATA63 AC15 M_DQ63 14,15
14 M_A_DIM0_CS#1 W16 M0_CS#1
15 M_B_DIM0_CS#0 U17 M1_CS#0
V16 M23 M_VREF_APU
15 M_B_DIM0_CS#1 M1_CS#1 M_VREF
U18 R502 1D5V_S3
14,15 M_RAS# M_RAS#
V19 39R2F-GP
14,15 M_CAS# M_CAS#
V17 M22 M_ZVDDIO_MEM_S
2 1
14,15 M_W E#

APU_VREF
M_WE# M_ZVDDIO_MEM_S
ONTARIO-FT1-GP

DDR_VREF_S3
1D5V_S3

R501 1 2 0R0402-PAD M_VREF_APU R503

1KR2J-1-GP
1

2 1 M_EVENT#
C502 C501
SCD1U10V2KX-5GP SC1KP50V2KX-1GP
2

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
AMD Confirm: PU Needed even if not used
Title
LAYOUT: place them close to APU APU_DDR(2/5)
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 5 of 109
5 4 3 2 1
 5 4 3 2 1

APU_TEST33_H_M_CLKTST_H SCD1U10V2KX-5GP
1 2C602 1 R602 2 51R2F-2-GP
SSID = CPU Brazos: Sabine: APU_TEST33_L_M_CLKTST_L SCD1U10V2KX-5GP
1 2C603 1 R603 2 51R2F-2-GP
DP1 --> HDMI DP0 --> LVDS
SVC SVD Boot Voltage Boot Voltage DP1 --> CRT
(VCC/GND) (open) DP2 --> HDMI
0 0 1.1 1.1
0 1 1.0 1.2 APU_TEST25_H_BYPASSCLK_H 1 R604 2 510R2F-L-GP
APU1B 2 OF 5
1 0 0.9 1.1 ANALOG/DISPLAY/MISC APU_TEST18_PLLTEST1 2 R605 1 1KR2J-1-GP
1 2 C610 SCD1U16V2KX-3GP GTXP2 A8 H3 DP_ZVSS 1 R609 2 150R2F-1-GP
51 APU_HDMI_DATA2 GTXN2 TDP1_TXP0 DP_ZVSS APU_TEST19_PLLTEST0
1 1 0.8 0.9 51 APU_HDMI_DATA2# 1 2 C607 SCD1U16V2KX-3GP B8
TDP1_TXN0 2 R606 1 1KR2J-1-GP
G2 L_BKLT_EN_R R610 1 2 0R0402-PAD L_BKLT_EN 27

DP MISC
GTXP1 DP_BLON LVDS_VDD_EN_R
51 APU_HDMI_DATA1 1 2 C606 SCD1U16V2KX-3GP B9 H2 R607 1 2 0R0402-PAD LVDS_VDD_EN 49
GTXN1 TDP1_TXP1 DP_DIGON L_BKLT_CTRL_R
D HDMI 51 APU_HDMI_DATA1# 1 2 C601 SCD1U16V2KX-3GP A9
TDP1_TXN1 DP_VARY_BL
H1 R608 1 2 0R0402-PAD L_BKLT_CTRL 49 D

DISPLAYPORT
1 2 C604 SCD1U16V2KX-3GP GTXP0 D10
51 APU_HDMI_DATA0 TDP1_TXP2
51 APU_HDMI_DATA0# 1 2 C605 SCD1U16V2KX-3GP GTXN0 C10 B2 PCH_HDMI_CLK_R 51
TDP1_TXN2 TDP1_AUXP
TDP1_AUXN
C2 PCH_HDMI_DATA_R 51 HDMI
1 2 C608 SCD1U16V2KX-3GP GTXP3 A10

1
51 APU_HDMI_CLK TDP1_TXP3 1D8V_S0
1 2 C609 SCD1U16V2KX-3GP GTXN3 B10 C1 DP1_HPD
51 APU_HDMI_CLK# TDP1_TXN3 TDP1_HPD DP1_HPD 51
B5 A3 LVDS_DDC_CLK 49 APU_TEST25_L_BYPASSCLK_L 1 R611 2 510R2F-L-GP
49 LVDSA_DATA2 LTDP0_TXP0 LTDP0_AUXP
49 LVDSA_DATA2# A5
LTDP0_TXN0 LTDP0_AUXN
B3 LVDS_DDC_DATA 49 LVDS 1D8V_S0
LVDS D6 D3 DP2_HPD X02
49 LVDSA_DATA1 LTDP0_TXP1 LTDP0_HPD
C6 1 R612 2150R2F-1-GP ALLOW_STOP 1 R613 2 1KR2J-1-GP
Panel 49 LVDSA_DATA1# LTDP0_TXN1

DISPLAYPORT
C12 CRT_RED 50
DAC_RED
49 LVDSA_DATA0 A6 D13 1 R615 2150R2F-1-GP
LTDP0_TXP2 DAC_RED#
49 LVDSA_DATA0# B6 A12 CRT_GREEN 50
LTDP0_TXN2 DAC_GREEN
DAC_GREEN#
B12 1 R617 2150R2F-1-GP
D8 A13 1D8V_S0

0
49 LVDSA_CLK LTDP0_TXP3 DAC_BLUE CRT_BLUE 50
49 LVDSA_CLK# C8 B13
LTDP0_TXN3 DAC_BLUE# APU_TEST36_GIO_TSTDTM0_SERIALCLK 1 R619 2 1KR2J-1-GP
17 APU_CLKP V2 E1 CRT_HSYNC 50
CLKIN_H DAC_HSYNC APU_TEST37_GIO_TSTDTM0_CLKINIT
100MHz 17 APU_CLKN V1 E2 CRT_VSYNC 50 1 R620
DY 2 1KR2J-1-GP
CLKIN_L DAC_VSYNC

DAC
VGA
APU_BP0_TSTCLK_USCLK1 1 R621 2 1KR2J-1-GP

CLK
17 DISP_CLKP D2
DISP_CLKIN_H DAC_SCL
F2 DDCCLK 50 DY
100MHz 17 DISP_CLKN D1
DISP_CLKIN_L DAC_SDA
D4 DDCDATA 50
J1 D12 DAC_ZVSS 2 R622 1 499R2F-2-GP
42 APU_SVC_R SVC DAC_ZVSS
42 APU_SVD_R J2
SVD
0721RN602 SRN0J-6-GP
TEST4
R1 APU_THERMDA 1 TP602 TPAD14

SER
R601 1 4 APU_SIC P3 R2 APU_THERMDC 1 TP603 TPAD14 1 R623
DY 2 1KR2J-1-GP
18 SCLK3 SIC TEST5
1 0R2J-2-GP
2 2 DY 3 APU_SID P4 R6 APU_TEST6_DIRECRACKMON 1 TP604 TPAD14
71 APU_RST_L_BUF DY 18 SDATA3 SID TEST6
T5 APU_BP0_TSTCLK_USCLK0 1 TP616 TPAD14 1 R624
DY 2 1KR2J-1-GP
0R0402-PAD1 R625 APU_RST#_R TEST14 APU_BP0_TSTCLK_USCLK1 R627
17,83 APU_RST# 2 T3 E4
H_CPUPWRGD 0R0402-PAD1 R626 APU_PWRGD_R RESET# TEST15 APU_TEST16_BP2 TP605 TPAD14
17,36,42,71 H_CPUPWRGD 2 T4 K4 1 1 21KR2J-1-GP
PWROK TEST16 APU_TEST17_BP3 TP606 TPAD14
L1 1
0R0402-PAD1 R628 TEST17 APU_TEST18_PLLTEST1
2 U1 L2

CTRL
17 APU_PROCHOT#_VDDIO PROCHOT# TEST18 APU_TEST18_PLLTEST1 71
APU_THERMTRIP#_VDDIO U2 M2 APU_TEST19_PLLTEST0 APU_TEST19_PLLTEST0 71
APU_ALERT# THERMTRIP# TEST19 APU_TEST25_H_BYPASSCLK_H
27,40 H_PROCHOT# T2 K1
ALERT# TEST25_H APU_TEST25_L_BYPASSCLK_L
K2

TEST
TEST25_L APU_TEST28_H_PLLCHARZ TP607 TPAD14 X01
C 71 APU_TDI N2 L5 1 C
TDI TEST28_H APU_TEST28_L_PLLCHARZ TP608 TPAD14
71 APU_TDO N1 M5 1
TDO TEST28_L APU_TEST31_MEM_TEST TP609 TPAD14 5V_S0
71 APU_TCK P1 M21 1
TCK TEST31 APU_TEST33_H_M_CLKTST_H
71 APU_TMS P2 J18
TMS TEST33_H APU_TEST33_L_M_CLKTST_L
M4 J19

JTAG
71 APU_TRST# TRST# TEST33_L

1
71 APU_DBRDY M3 U15 APU_TEST34_H_TSTCLKIN_H 1 TP610 TPAD14
DBRDY TEST34_H APU_TEST34_L_TSTCLKIN_L TP611 TPAD14 R664
71 APU_DBREQ# M1 T15 1
DBREQ# TEST34_L APU_TEST35
H4 100KR2J-1-GP
TEST35 APU_TEST36_GIO_TSTDTM0_SERIALCLK TP612 TPAD14
42 APU_VDDNB_RUN_FB_H F4 N5 1
VDDCR_NB_SENSE TEST36 APU_TEST37_GIO_TSTDTM0_CLKINIT TP613 TPAD14
42 APU_VDD_RUN_FB_H G1 R5 1

2
APU_VDDIO_SUS_FB_H VDDCR_CPU_SENSE TEST37 DP2_HPD
1 F3
TPAD14 TP614 VDDIO_MEM_S_SENSE

1
0R0402-PAD1 2 R630 APU_RUN_FB_L F1
42 APU_VDD_RUN_FB_L VSS_SENSE
K3 APU_TEST38 1 TP615 TPAD14 R647
0R0402-PAD1 R631 TEST38
42 APU_VDDNB_RUN_FB_L 2 B4
RSVD#B4 DMAACTIVE#
T1 ALLOW_STOP 17 100KR2J-1-GPDY
W11
RSVD#W11 ONTARIO_FT1
V5

2
0819 RSVD#V5
ONTARIO-FT1-GP
APU_RST# C631 1 DY2SC10P50V2JN-4GP
1D8V_S0 X01 H_CPUPWRGD C632 1 DY2SC10P50V2JN-4GP
RN605
4 1 H_CPUPWRGD
3 2 APU_RST# 0811 AMD Nick change
X01
SRN300J-3-GP 0811 Remove level shifter 1D8V_S0
3D3V_S0

2
1

R629
R635
10KR2J-3-GP 1KR2J-1-GP
APU_THERMTRIP#_VDDIO_Q

0809 Change to 1k APU_ALERT# R643

1
1D8V_S0 1 2 APU_ALERT#_FCH 19 APU_TEST35
2

RN607 0R0402-PAD

2
1 4 APU_SVD_R 3D3V_S5
2 3 APU_SVC_R R632

B Thripthrip# add integrated PU 10K DY 1KR2J-1-GP

B
SRN1KJ-7-GP
1

1
DY R646
84.T3904.C11 10KR2J-3-GP
2ND = 84.03904.P11
2

3rd = 84.03904.L06
B

MMBT3904-4-GP
3D3V_S0
APU_THERMTRIP#_VDDIO E C H_THERMTRIP# 18,36
Q601
X01
CPU exceeds to 125℃

1
2
RN634
SRN1KJ-7-GP

4
3
49 LVDS_DDC_DATA
49 LVDS_DDC_CLK

3D3V_S0
RN608
8 1 APU_SID
7 2 APU_ALERT#
6 3 APU_THERMTRIP#_VDDIO
5 4 APU_SIC

SRN1KJ-4-GP X01
RN

1D8V_S0
RN635 0R4P2R-PAD
RN601 APU_SID 1 4 SML1_DATA 27,85
8 1 APU_TRST# APU_SIC 2 3 SML1_CLK 27,85
A 7 2 APU_TMS A
6 3 APU_TCK
5 4 APU_TDI

SRN1KJ-4-GP
<Core Design>
R640
1 2 APU_DBREQ#
300R2J-4-GP
0802 Change to H_PROCHOT# Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
3D3V_S0 Taipei Hsien 221, Taiwan, R.O.C.

1 R641 2 H_PROCHOT# Title

1KR2J-1-GP APU_COntrol&Debug(3/5)
Size Document Number Rev
Custom
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 6 of 109
5 4 3 2 1
 5 4 3 2 1
SSID = CPU
VDDCR_CPU:
APU_VDD
10uF X 7 1uF X 4
0.1uF X 5 180pF X 2
D D
C713

C705

C714

C706

C715

C708

C709
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
SC4D7U6D3V5KX-3GP
1

DY DY DY DY
2

1D8V_S0
11A for 18W APU1C 3 OF 5
2A for 18W
4.5A for 9W 2A for 9W
E5 ONTARIO_FT1 U8
VDDCR_CPU VDD_18
E6 W8
F5
VDDCR_CPU
VDDCR_CPU
VDD_18
VDD_18 U6 VDD_18:
C717

C711

C718

C712

C719

C721

C723

C725

C726
F7 U9
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC10U6D3V5KX-1GP
10uF X 1 1uF X 4
SC180P50V2JN-1GP

SC180P50V2JN-1GP
C716

VDDCR_CPU VDD_18
1

1
C720

C724
G6 VDDCR_CPU VDD_18 W6
DY DY DY DY G8 T7 DY DY
H5
VDDCR_CPU VDD_18
V7 0.1uF X 1 180pF X 1
2

2
VDDCR_CPU VDD_18
H7 VDDCR_CPU
J6 VDDCR_CPU
J8 VDDCR_CPU
L7 VDDCR_CPU
M6 VDDCR_CPU
M8 VDDCR_CPU
N7 VDDCR_CPU 1D8V_S0
APU_VDDNB 10A for 18W R8 VDDCR_CPU 0.15A for 18W
C C
8A for 9W 0.15A for 9W
E8 VDDCR_NB VDD_18_DAC W9 VDD_18_DAC:
E11
VDDCR_NB: VDDCR_NB 10uF X 1 1uF X 1

C742

C743
E13

SC1U6D3V2KX-GP
SC180P50V2JN-1GP

C744
VDDCR_NB

1
SC4D7U6D3V5KX-3GP

SC4D7U6D3V5KX-3GP

SC4D7U6D3V5KX-3GP
C729

F9
SC10U6D3V5KX-1GP

VDDCR_NB
180pF X 1
1

10uF X 5 1uF X 5
C730

C731

DY
F12 VDDCR_NB DY
G11

2
VDDCR_NB
0.1uF X 4 180pF X 2 G13
2

VDDCR_NB
H9 VDDCR_NB VDDPL_10 1V_S0 0.2A for 18W
H12
K11
VDDCR_NB
VDDCR_NB L701
VDDPL_10: 0.2A for 9W
K13
L10
VDDCR_NB
VDDCR_NB VDDPL_10 U11 1 2 10uF X 1 1uF X 1

POWER
L12 PBY160808T-221Y-N-GP
VDDCR_NB
0.1uF X 1 180pF X 1

C745

C746

C747

C748
L14 220 ohm 2A

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP

SC10U6D3V5KX-1GP
SC180P50V2JN-1GP
VDDCR_NB

1
M11
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
VDDCR_NB
SCD1U10V2KX-5GP
SC180P50V2JN-1GP

SC180P50V2JN-1GP

C701

C740
M12 DY
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC180P50V2JN-1GP
C734

C735

C739

C741
VDDCR_NB
1

1
SCD1U10V2KX-5GP
C733

C737

C738

M13

2
DY DY DY VDDCR_NB
DY N10 VDDCR_NB 1V_S0
N12 5.5A for 18W
2

2
VDDCR_NB
N14
P11
VDDCR_NB
VDDCR_NB
VDD_10: 5.5A for 9W
P13 U13
VDDCR_NB VDD_10
VDD_10 W13 10uF X 2 1uF X 2
V12
VDD_10
0.1uF X 2 180pF X 1

C749

C750

C751

C752

C753

C754

C755
G16 T12

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
SC180P50V2JN-1GP
VDDIO_MEM_S VDD_10

1
G19 VDDIO_MEM_S
1D5V_S3 2A for 18W E17 DY DY DY
VDDIO_MEM_S
B 2A for 9W J16 B

2
VDDIO_MEM_S
L16 VDDIO_MEM_S
L19 VDDIO_MEM_S
VDDIO_MEN_S: N16

SCD1U10V2KX-5GP
VDDIO_MEM_S

SCD1U10V2KX-5GP
3D3V_S0
C756

C757

C761
R16

SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C760

C762
VDDIO_MEM_S
1

1
10uF X 2 1uF X 4 DY DY
R19
W18
VDDIO_MEM_S
VDDIO_MEM_S
0.1uF X 3 180pF X 2 U16 A4
VDD_33:
2

2
VDDIO_MEM_S VDD_33
0.5A for 18W 1uF X 1

C771

C772
ONTARIO-FT1-GP

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
1

1
0.5A for 9W
0.1uF X 1

2
SCD1U10V2KX-5GP
C763

C765

C766

C767

C768
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
1

1
C769

C770
DY DY

2
<Core Design>
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
APU_Power(4/5)
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 7 of 109
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

D D

APU1D 4 OF 5

A7 ONTARIO_FT1 N13
VSS VSS
B7 VSS VSS N20
B11 VSS VSS N22
B17 VSS VSS P10
B22 VSS VSS P14
C4 VSS VSS R4
D5 VSS VSS R7
D7 VSS VSS R20
D9 VSS VSS T6
D11 VSS VSS T9
D14 VSS VSS T11
B15 VSS VSS T13
D17 VSS VSS U4
D19 VSS VSS U5
E7 VSS VSS U7
E9 VSS VSS U12
E12 VSS VSS U20
E20 VSS VSS U22
F8 VSS VSS V8
F11 VSS VSS V9
F13 VSS VSS V11
C G4 V13 C
VSS VSS
G5 VSS VSS W1
G7 VSS VSS W2

GROUND
G9 VSS VSS W4
G12 VSS VSS W5
G20 VSS VSS W7
G22 VSS VSS W12
H6 VSS VSS W20
H11 VSS VSS Y5
H13 VSS VSS Y7
J4 VSS VSS Y9
J5 VSS VSS Y11
J7 VSS VSS Y13
J20 VSS VSS Y15
K10 VSS VSS Y17
K14 VSS VSS Y19
L4 VSS VSS AA4
L6 VSS VSS AA22
L8 VSS VSS AB2
L11 VSS VSS AB5
L13 VSS VSS AB9
L20 VSS VSS AB13
L22 VSS VSS AB17
M7 VSS VSS AB21
N4 VSS VSS AC5
N6 VSS VSS AC9
N8 VSS VSS AC13
N11 VSS VSSBG_DAC A11
B B
ONTARIO-FT1-GP

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
APU_VSS(5/5)
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 8 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
TRAVIS
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 9 of 109

5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Reserved
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 10 of 109

5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Reserved
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 11 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Reserved
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 12 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Reserved
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 13 of 109
5 4 3 2 1
 5 4 3 2 1

SSID = MEMORY

D D

DM1

5,15 M_A0 98 NP1

A0 NP1
5,15 M_A1 97 NP2
A1 NP2
5,15 M_A2 96
A2
5,15 M_A3 95 110 M_RAS# 5,15
A3 RAS#
5,15 M_A4 92 113 M_WE# 5,15
A4 WE#
5,15 M_A5 91 115 M_CAS# 5,15
A5 CAS#
5,15 M_A6 90
A6
5,15 M_A7 86 114 M_A_DIM0_CS#0 5
A7 CS0#
5,15 M_A8 89 121 M_A_DIM0_CS#1 5
A8 CS1#
5,15 M_A9 85
A9
5,15 M_A10 107 73 M_DIM0_CKE0 5,15
A10/AP CKE0
5,15 M_A11 84 74 M_DIM0_CKE1 5,15
A11 CKE1
5,15 M_A12 83
A12
5,15 M_A13 119 101 M_DIM0_CLK_DDR0 5
A13 CK0
5,15 M_A14 80 103 M_DIM0_CLK_DDR#0 5
A14 CK0#
5,15 M_A15 78
A15
5,15 M_BS2 79 102 M_DIM0_CLK_DDR1 5
A16/BA2 CK1
104 M_DIM0_CLK_DDR#1 5
CK1#
5,15 M_BS0 109
BA0
5,15 M_BS1 108 11 M_DM0 5,15
BA1 DM0
28 M_DM1 5,15
DM1
5,15 M_DQ0 5
DQ0 DM2
46 M_DM2 5,15 Intel HR DM tied to GND
5,15 M_DQ1 7 63 M_DM3 5,15
15
DQ1 DM3
136 AMD still following previous design
5,15 M_DQ2 DQ2 DM4 M_DM4 5,15
5,15 M_DQ3 17 153 M_DM5 5,15
DQ3 DM5
5,15 M_DQ4 4 170 M_DM6 5,15
DQ4 DM6
5,15 M_DQ5 6 187 M_DM7 5,15
DQ5 DM7
5,15 M_DQ6 16
DQ6
5,15 M_DQ7 18 200 PCH_SMBDATA 15,65
DQ7 SDA
5,15 M_DQ8 21 202 PCH_SMBCLK 15,65
DQ8 SCL 3D3V_S0
5,15 M_DQ9 23
DQ9
5,15 M_DQ10 33 198
DQ10 EVENT#
5,15 M_DQ11 35
DQ11
5,15 M_DQ12 22 199
DDR_VREF_S3 DQ12 VDDSPD
5,15 M_DQ13 24
DQ13 SA0_DIM0
5,15 M_DQ14 34 197

1
DQ14 SA0 SA1_DIM0 C1401 C1402
5,15 M_DQ15 36 201
DQ15 SA1 SCD1U10V2KX-5GP SC2D2U6D3V3KX-GP
39
C
5,15 M_DQ16
41
DQ16
77
DY C

2
5,15 M_DQ17 DQ17 NC#1
51 122
SC2D2U6D3V3KX-GP

5,15 M_DQ18
1

DQ18 NC#2 1D5V_S3

C1412

5,15 M_DQ19 53 125

C1411 C1413 DQ19 NC#/TEST
40
SC1KP50V2KX-1GP DY SC1KP50V2KX-1GP
5,15 M_DQ20
42
DQ20
75
2

5,15 M_DQ21 DQ21 VDD1

5,15 M_DQ22 50 76
DQ22 VDD2
5,15 M_DQ23 52 81
DQ23 VDD3
5,15 M_DQ24 57 82
DQ24 VDD4
5,15 M_DQ25 59 87
DQ25 VDD5
5,15 M_DQ26 67 88
DQ26 VDD6
5,15 M_DQ27 69 93
DQ27 VDD7
5,15 M_DQ28 56 94
DQ28 VDD8
5,15 M_DQ29 58 99
DQ29 VDD9
5,15 M_DQ30 68 100
0D75V_S0 DQ30 VDD10
5,15 M_DQ31 70 105
DQ31 VDD11
5,15 M_DQ32 129 106
DQ32 VDD12
5,15 M_DQ33 131 111
DQ33 VDD13
5,15 M_DQ34 141 112
1

DQ34 VDD14
DYC1418
SC10U6D3V5KX-1GP
5,15 M_DQ35 143
130
DQ35 VDD15
117
118
5,15 M_DQ36 DQ36 VDD16
132 123
2

5,15 M_DQ37 DQ37 VDD17

5,15 M_DQ38 140 124
DQ38 VDD18 SA0_DIM0
5,15 M_DQ39 142
DQ39 X01
5,15 M_DQ40 147 2
DQ40 VSS SA1_DIM0
5,15 M_DQ41 149 3 RN1401
DQ41 VSS PCH_SMBDATA
5,15 M_DQ42 157 8 1 4 SMB_DATA 18
DQ42 VSS PCH_SMBCLK
5,15 M_DQ43 159 9 2 3 SMB_CLK 18

2
DQ43 VSS
5,15 M_DQ44 146 13
DQ44 VSS R1401 R1402
5,15 M_DQ45 148 14 SRN22-3-GP
DQ45 VSS
5,15 M_DQ46 158 19 0R0402-PAD 0R0402-PAD
DQ46 VSS
0D75V_S0 Place these caps 5,15 M_DQ47 160
DQ47 VSS
20
PCH_SMBDATA C1423 1
163 25 2SC10P50V2JN-4GP

1
close to VTT1 and 5,15 M_DQ48 DQ48 VSS PCH_SMBCLK
165 26 C1424 1 2SC10P50V2JN-4GP
5,15 M_DQ49 DQ49 VSS
VTT2. 5,15 M_DQ50 175 31
DQ50 VSS
5,15 M_DQ51 177 32
DQ51 VSS
5,15 M_DQ52 164 37
DQ52 VSS
166 38
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

5,15 M_DQ53 DQ53 VSS

C1419

C1420

C1421

C1422

5,15 M_DQ54 174 43

1

DQ54 VSS
5,15 M_DQ55 176 44
DQ55 VSS
B
DY DY 5,15 M_DQ56 181
DQ56 VSS
48
B
183 49
2

5,15 M_DQ57 DQ57 VSS

5,15 M_DQ58 191 54
DQ58 VSS
5,15 M_DQ59 193 55
DQ59 VSS
5,15 M_DQ60 180 60
DQ60 VSS
5,15 M_DQ61 182 61
DQ61 VSS
5,15 M_DQ62 192 65
DQ62 VSS
5,15 M_DQ63 194 66
DQ63 VSS
71
VSS
5,15 M_DQS#0 10 72
DQS0# VSS
5,15 M_DQS#1 27 127
DQS1# VSS
5,15 M_DQS#2 45 128
DQS2# VSS 1D5V_S3
5,15 M_DQS#3 62
DQS3# VSS
133 SODIMM A DECOUPLING
5,15 M_DQS#4 135 134
DQS4# VSS
5,15 M_DQS#5 152 138
DQS5# VSS
5,15 M_DQS#6 169
DQS6# VSS
139 X01
5,15 M_DQS#7 186 144
DQS7# VSS

SE220U2VDM-8GP

SC4D7U6D3V5KX-3GP
145

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
SC4D7U6D3V5KX-3GP

SC4D7U6D3V5KX-3GP
SC10U10V5ZY-1GP

SC10U10V5ZY-1GP
VSS

TC1401

C1405

C1406

C1407

C1408

C1409

C1410
12 150

C1404
5,15 M_DQS0

1
DQS0 VSS

C1403
5,15 M_DQS1 29 151
DQS1 VSS DY
47 155
5,15 M_DQS2
64
DQS2 VSS
156
DY DY DY

2
5,15 M_DQS3 DQS3 VSS
5,15 M_DQS4 137 161
DQS4 VSS
5,15 M_DQS5 154 162
DQS5 VSS
5,15 M_DQS6 171 167
DQS6 VSS
5,15 M_DQS7 188 168
DQS7 VSS
172
VSS
5 M_A_DIM0_ODT0 116 173
ODT0 VSS
5 M_A_DIM0_ODT1 120 178
ODT1 VSS

SCD1U10V2KX-5GP
179

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
VSS
C1414

C1416

C1417
DDR_VREF_S3 126 184

C1415
1

1
VREF_CA VSS
1
VREF_DQ VSS
185 Layout Note:
189
VSS Place these Caps near
5,15 M_RST# 30 190
2

2
RESET# VSS
195 SO-DIMMA.
VSS
196
VSS
0D75V_S0 203 205
0721: Reserve Cap VTT1 VSS
204 206
VTT2 VSS

M_RST#
DDR3-204P-25-GP
1

A C1425 A

DYSCD1U10V2KX-5GP 62.10017.K11
2

H=5.2mm
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
DDR3-SODIMM1
Size Document Number Rev
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 14 of 109

5 4 3 2 1
 5 4 3 2 1

SSID = MEMORY

DM2

5,14 M_A0 98 NP1

A0 NP1
5,14 M_A1 97 NP2
96
A1 NP2 X01
5,14 M_A2 A2
5,14 M_A3 95 110 M_RAS# 5,14
A3 RAS#
D 5,14 M_A4 92 113 M_WE# 5,14 D
A4 WE#
5,14 M_A5 91 115 M_CAS# 5,14
A5 CAS#
5,14 M_A6 90 M_DIM0_CKE0
A6 3D3V_S0
5,14 M_A7 86 114 M_B_DIM0_CS#0 5 M_DIM0_CKE1
A7 CS0#
5,14 M_A8 89 121 M_B_DIM0_CS#1 5
A8 CS1#
5,14 M_A9 85
A9

1
5,14 M_A10 107 73 M_DIM0_CKE0 5,14

1
A10/AP CKE0
5,14 M_A11 84 74 M_DIM0_CKE1 5,14 R1531 R1532
A11 CKE1 R1501
5,14 M_A12 83
A12 69D8R2F-GP 69D8R2F-GP 0721 change 4k7 to 10k
119 101 10KR2J-3-GP
5,14 M_A13 A13 CK0 M_DIM0_CLK_DDR2 5
5,14 M_A14 80
A14 CK0#
103 M_DIM0_CLK_DDR#2 5 DYDY

2
78

2
5,14 M_A15 A15
79 102 M_DIM0_CLK_DDR3 5
5,14 M_BS2 A16/BA2 CK1 SA0_DIM1
104 M_DIM0_CLK_DDR#3 5
CK1#
109
5,14 M_BS0 BA0 SA1_DIM1
108 11 M_DM0 5,14
5,14 M_BS1 BA1 DM0
28 M_DM1 5,14
DM1
5,14 M_DQ0 5 46 M_DM2 5,14 Intel HR DM tied to GND

2
DQ0 DM2
5,14 M_DQ1 7 63 M_DM3 5,14
15
DQ1 DM3
136 AMD still following previous design R1502
5,14 M_DQ2 DQ2 DM4 M_DM4 5,14
5,14 M_DQ3 17 153 M_DM5 5,14 0R0402-PAD
DQ3 DM5
5,14 M_DQ4 4 170 M_DM6 5,14
DQ4 DM6
6 187

1
5,14 M_DQ5 DQ5 DM7 M_DM7 5,14
5,14 M_DQ6 16
DQ6
5,14 M_DQ7 18 200 PCH_SMBDATA 14,65
DQ7 SDA
5,14 M_DQ8 21 202 PCH_SMBCLK 14,65
DQ8 SCL 3D3V_S0
5,14 M_DQ9 23
DQ9
5,14 M_DQ10 33
DQ10 EVENT#
198 Intel HR B channel address is 01
5,14 M_DQ11 35
22
DQ11
199 AMD B channel address is 10
5,14 M_DQ12 DQ12 VDDSPD
5,14 M_DQ13 24
DQ13 SA0_DIM1
5,14 M_DQ14 34 197

1
DQ14 SA0 SA1_DIM1

C1501

C1502
36 201

SCD1U10V2KX-5GP

SC2D2U6D3V3KX-GP
5,14 M_DQ15 DQ15 SA1
39
5,14 M_DQ16
41
DQ16
77
DY
5,14 M_DQ17

2
DQ17 NC#1
5,14 M_DQ18 51 122
DQ18 NC#2 1D5V_S3
5,14 M_DQ19 53 125
DQ19 NC#/TEST
5,14 M_DQ20 40
DQ20
5,14 M_DQ21 42 75
DQ21 VDD1
5,14 M_DQ22 50 76
DQ22 VDD2
5,14 M_DQ23 52 81
DQ23 VDD3
C
5,14 M_DQ24 57 82 C
DQ24 VDD4
5,14 M_DQ25 59 87
DQ25 VDD5
5,14 M_DQ26 67 88
DQ26 VDD6
5,14 M_DQ27 69 93
DQ27 VDD7
5,14 M_DQ28 56 94
DQ28 VDD8
5,14 M_DQ29 58 99
DQ29 VDD9
5,14 M_DQ30 68 100
DQ30 VDD10
5,14 M_DQ31 70 105
DQ31 VDD11
5,14 M_DQ32 129 106
DQ32 VDD12
5,14 M_DQ33 131 111
DQ33 VDD13
5,14 M_DQ34 141 112
DQ34 VDD14
5,14 M_DQ35 143 117
DQ35 VDD15
DDR_VREF_S3 5,14 M_DQ36 130 118
DQ36 VDD16
5,14 M_DQ37 132 123
DQ37 VDD17
5,14 M_DQ38 140 124
DQ38 VDD18 1D5V_S3
5,14 M_DQ39 142
DQ39
5,14 M_DQ40 147
DQ40 VSS
2 SODIMM B DECOUPLING
SC2D2U6D3V3KX-GP

5,14 M_DQ41 149 3

DQ41 VSS
1

C1516 5,14 M_DQ42 157 8

DQ42 VSS
C1515 C1517 5,14 M_DQ43 159 9
DQ43 VSS
DY

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
C1503

C1504

C1506

C1508

C1509

C1510
146 13

SC10U6D3V5KX-1GP
SCD1U10V2KX-5GP

SC4D7U6D3V5KX-3GP

SC4D7U6D3V5KX-3GP
SC10U10V5ZY-1GP

SC10U10V5ZY-1GP
SCD1U10V2KX-5GP 5,14 M_DQ44 DQ44 VSS

C1505

C1507
2

5,14 M_DQ45 148 14

1
DQ45 VSS
5,14 M_DQ46 158 19
DQ46 VSS
160 20
5,14 M_DQ47
163
DQ47 VSS
25 DY DY DY DY

2
5,14 M_DQ48 DQ48 VSS
5,14 M_DQ49 165 26
DQ49 VSS
5,14 M_DQ50 175 31
DQ50 VSS
5,14 M_DQ51 177 32
DQ51 VSS
5,14 M_DQ52 164 37
DQ52 VSS
5,14 M_DQ53 166 38
DQ53 VSS
5,14 M_DQ54 174 43
DQ54 VSS
5,14 M_DQ55 176 44
DQ55 VSS
181 48

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
5,14 M_DQ56 DQ56 VSS

C1511

C1512

C1513
183 49

SCD1U10V2KX-5GP
5,14 M_DQ57

1
DQ57 VSS

C1514
5,14 M_DQ58 191
DQ58 VSS
54 Layout Note:
5,14 M_DQ59 193 55
DQ59 VSS Place these Caps near
180 60

2
5,14 M_DQ60 DQ60 VSS
Place these caps 5,14 M_DQ61 182
DQ61 VSS
61 SO-DIMMB.
5,14 M_DQ62 192 65
0D75V_S0 close to VTT1 and DQ62 VSS
5,14 M_DQ63 194 66
DQ63 VSS
VTT2. 71
B VSS B
5,14 M_DQS#0 10 72
DQS0# VSS
5,14 M_DQS#1 27 127
DQS1# VSS
5,14 M_DQS#2 45 128
DQS2# VSS
C1518

C1519

C1520

C1521

62 133
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

5,14 M_DQS#3
1

DQS3# VSS
DY 5,14 M_DQS#4 135
152
DQS4# VSS
134
138
DY 5,14 M_DQS#5
169
DQS5# VSS
139
2

5,14 M_DQS#6 DQS6# VSS

5,14 M_DQS#7 186 144
DQS7# VSS
145
VSS
5,14 M_DQS0 12 150
DQS0 VSS
5,14 M_DQS1 29 151
DQS1 VSS
5,14 M_DQS2 47 155
DQS2 VSS
5,14 M_DQS3 64 156
DQS3 VSS
5,14 M_DQS4 137 161
DQS4 VSS
5,14 M_DQS5 154 162
DQS5 VSS
5,14 M_DQS6 171 167
DQS6 VSS
5,14 M_DQS7 188 168
DQS7 VSS
172
VSS
5 M_B_DIM0_ODT0 116 173
ODT0 VSS
5 M_B_DIM0_ODT1 120 178
ODT1 VSS
179
VSS
DDR_VREF_S3 126 184
VREF_CA VSS
1 185
VREF_DQ VSS
189
VSS
5,14 M_RST# 30 190
RESET# VSS
195
VSS
VSS
196 SO-DIMMB is placed farther from
0D75V_S0 203 205
VTT1 VSS the Processor than SO-DIMMA
204 206
VTT2 VSS

DDR3-204P-24-GP

62.10017.K01
H=9.2mm

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
DDR3-SODIMM2
Size Document Number Rev
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 15 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 16 of 109
5 4 3 2 1
 5 4 3 2 1

SSID = FCH 3D3V_S0

2
R1702
UMA 10KR2J-3-GP

1
dGPU_PRSNT#
FCH1A 1 OF 5

2
1
C1702 HUDSON-1 R1703
SC150P50V2KX-GP X01 DIS_PX 10KR2J-3-GP
PCIE_RST#_C P1 W2 PCI_CLK0_R 1 TP1702TPAD14

2
R1704 1 33R2J-2-GP A_RST#_R PCIE_RST# PCICLK0 PCI_CLK1_R R1705 0R0402-PAD
2 L1 W1 1 2

1
27,36 A_RST# A_RST# PCICLK1_GPO36 PCI_CLK1 21
PCI_CLK2_R R1718 0R0402-PAD
C1703 1 2 SCD1U10V2KX-5GP A_RX0P_C AD26
PCICLK2_GPO37
W3
W4 PCI_CLK3_R R1706
1
1
2
2 0R0402-PAD PCI_CLK2 21 33MHZ
4 UMI_FCH_APU_RX0P A_RX0N_C UMI_TX0P PCICLK3_GPO38 PCI_CLK4_R CLK_PCI_LPC 21,71
D C1704 1 2 SCD1U10V2KX-5GP AD27 Y1 R1707 1 2 0R0402-PAD D
4 UMI_FCH_APU_RX0N UMI_TX0N PCICLK4_14M_OSC_GPO39 PCI_CLK4 21
C1705 1 2 SCD1U10V2KX-5GP A_RX1P_C AC28
4 UMI_FCH_APU_RX1P UMI_TX1P PCI CLKS
C1706 1 2 SCD1U10V2KX-5GP A_RX1N_C AC29 V2 PCI_RST# 1 TP1703TPAD14 0811 EMI
4 UMI_FCH_APU_RX1N UMI_TX1N PCIRST#
C1707 1 2 SCD1U10V2KX-5GP A_RX2P_C AB29
4 UMI_FCH_APU_RX2P UMI_TX2P
C1708 1 2 SCD1U10V2KX-5GP A_RX2N_C AB28 R1721
4 UMI_FCH_APU_RX2N UMI_TX2N
C1709 1 2 SCD1U10V2KX-5GP A_RX3P_C AB26 AA1 0R2J-2-GP
4 UMI_FCH_APU_RX3P UMI_TX3P AD0_GPIO0
C1710 1 2 SCD1U10V2KX-5GP A_RX3N_C AB27 AA4 PCI_CLK3_R 1 2
4 UMI_FCH_APU_RX3N UMI_TX3N AD1_GPIO1 DY
AA3
PCI EXPRESS I/F AD2_GPIO2

1
4 UMI_APU_FCH_TX0P AE24 AB1
UMI_RX0P AD3_GPIO3
4 UMI_APU_FCH_TX0N AE23 AA5 C1722
0721 Change CAP 10V to 16V AD25
UMI_RX0N AD4_GPIO4
AB2 DY
4 UMI_APU_FCH_TX1P UMI_RX1P AD5_GPIO5 SC10P50V2JN-4GP

2
4 UMI_APU_FCH_TX1N AD24 AB6
UMI_RX1N AD6_GPIO6
4 UMI_APU_FCH_TX2P AC24 AB5
UMI_RX2P AD7_GPIO7 dGPU_PRSNT#
4 UMI_APU_FCH_TX2N AC25
UMI_RX2N AD8_GPIO8
AA6 0712
4 UMI_APU_FCH_TX3P AB25 AC2
UMI_RX3P AD9_GPIO9 3D3V_S0
4 UMI_APU_FCH_TX3N AB24 AC3
UMI_RX3N AD10_GPIO10
AC4
PCIE_CALRP_R AD11_GPIO11
1R1709 590R2F-GP
2 AD29 AC1
PCIE_CALRN_R PCIE_CALRP AD12_GPIO12
1D1V_PCIE_S0 1 R1710 2 AD28 AD1

2
2KR2F-3-GP PCIE_CALRN AD13_GPIO13
AD2
C1701 1 PCIE_TXP0_C AD14_GPIO14
31 PCIE_TXP0 2 SCD1U10V2KX-5GP AA28 AC6 R1711
KBC
C1712 1 PCIE_TXN0_C GPP_TX0P AD15_GPIO15
LAN 2 SCD1U10V2KX-5GP AA29 AE2 DY

10KR2J-3-GP
31 PCIE_TXN0 GPP_TX0N AD16_GPIO16
Y29 AE1
GPP_TX1P AD17_GPIO17
Y28 AF8

1
C1713 1 PCIE_TXP2_C GPP_TX1N AD18_GPIO18
65 PCIE_TXP2 2 SCD1U10V2KX-5GP Y26 AE3
C1714 1 PCIE_TXN2_C GPP_TX2P AD19_GPIO19 PCIE_RST#_C
WLAN 65 PCIE_TXN2 2 SCD1U10V2KX-5GP Y27 AF1 R1708 1 2 33R2J-2-GP
GPP_TX2N AD20_GPIO20 PLT_RST# 31,65,71,83
W28 AG1
GPP_TX3P AD21_GPIO21 PE_GPIO0 83
W29 AF2

1
GPP_TX3N AD22_GPIO22 C1711
AE9
AD23_GPIO23 PCI_AD23 21 SC150P50V2KX-GP
31 PCIE_RXP0 AA22 AD9
GPP_RX0P AD24_GPIO24 PCI_AD24 21
LAN 31 PCIE_RXN0 Y21 AC11 X01

2
GPP_RX0N AD25_GPIO25 PCI_AD25 21
AA25
GPP_RX1P AD26_GPIO26
AF6
PCI_AD26 21 Debug Strap folloiwng Intel HR netname
AA24 AF4
GPP_RX1N AD27_GPIO27 PCI_AD27 21
65 PCIE_RXP2 W23 AF3 1D5V_VGA_PWOK 83,86
GPP_RX2P AD28_GPIO28
WLAN 65 PCIE_RXN2 V24 AH2
GPP_RX2N AD29_GPIO29
W24 AG2
GPP_RX3P AD30_GPIO30
W25
GPP_RX3N AD31_GPIO31
AH3 LDT_STP# connection is just
AA8
CBE0#
AD5
for chipset automation purpose.
PCI I/F CBE1#
CBE2#
AD8 It is an automatic test for
AA10
C
CBE3#
AE8
AMD validation team only C
FRAME#
AB9
DEVSEL# 3D3V_S0
EXT clock_Gen M23
PCIE_RCLKP_NB_LNK_CLKP IRDY#
AJ3 0709
P23 AE7
PCIE_RCLKN_NB_LNK_CLKN TRDY# R1713
AC5

2
RN1702 2 FCHDISP_CLKP_R PAR 1KR2J-1-GP
6 DISP_CLKP 3 U29 AF5
0R4P2R-PAD 1 FCHDISP_CLKN_R NB_DISP_CLKP STOP# R1712 APU_STOP#
100MHZ 4 U28 AE6 1 2
6 DISP_CLKN NB_DISP_CLKN PERR#
AE4 X01 DY Muxless support DY 1D8V_S0

10KR2J-3-GP
TPAD14-GP TP1705 NB_HT_CLKP SERR#
1 T26 AE11
NB_HT_CLKP REQ0#
RN

TPAD14-GP TP1706 1 NB_HT_CLKN T27 AH5 PE_GPIO0 ->VGA_RESET

1
NB_HT_CLKN REQ1#_GPIO40 RTC_SENSE 60
X02 REQ2#_CLK_REQ8#_GPIO41
AH4 PE_GPIO1 ->VGA_PowerEnable
RN1703 2 3 FCHAPU_CLKP_R V21 AC12 GPIO42 1 TP1707 TPAD14
6 APU_CLKP CPU_HT_CLKP REQ3#_CLK_REQ5#_GPIO42
SRN22-3-GP 1 FCHAPU_CLKN_R
100MHZ 6 APU_CLKN 4 T21
CPU_HT_CLKN GNT0#
AD12
AJ5
RN1701 2 FCHGFX_CLKP_R GNT1#_GPO44
83 CLK_PCIE_VGA 3 V23 AH6 R1714
SRN22-3-GP 1 4 FCHGFX_CLKN_R T23
SLT_GFX_CLKP GNT2#_GPO45
AB12 GPIO46 1 TP1708 TPAD14 PE_GPIO1 92,93 checklist:No PU Res INT_SERIRQ 2 1 3D3V_S0
83 CLK_PCIE_VGA# SLT_GFX_CLKN GNT3#_CLK_REQ7#_GPIO46 DY
AB11 PM_CLKRUN# Integrated Resistor PU10K 10KR2J-3-GP
CLKRUN# PM_CLKRUN# 27
L29
GPP_CLK0P LOCK#
AD7 integrated PU
L28 SC10P50V2JN-4GP
GPP_CLK0N C1716 1
AJ6 2
RN1704 2 CLK_MINI1_R INTE#_GPIO32
65 CLK_PCIE_WLAN 3 N29 AG6
0R4P2R-PAD 1 CLK_MINI1#_R GPP_CLK1P INTF#_GPIO33 R1719 1
WLAN 65 CLK_PCIE_WLAN# 4 N28 AG4 222R2J-2-GP X01
GPP_CLK1N INTG#_GPIO34 R1720 1 LPC_CLK0 21,27
2 0R0402-PAD

RN
AJ4 SATA_ODD_DA# 56
INTH#_GPIO35 LPC_CLK1 21 32K_X1 C1715 1
M29 2 SC18P50V2JN-1-GP
GPP_CLK2P
RN

M28
GPP_CLK2N 0806 RN1706 1 4 LPC_AD0 27,71
0R4P2R-PAD 2 3 LPC_AD1 27,71
RN1705 2 3 LAN_CLK_R T25
31 CLK_PCIE_LAN GPP_CLK3P
LAN 0R4P2R-PAD 1 LAN_CLK#_R LPCCLK0_R

RN
31 CLK_PCIE_LAN# 4 V25 H24

1
GPP_CLK3N LPCCLK0 LPCCLK1_R

3
CLOCK GENERATOR LPCCLK1
H25 0819
L24 J27 LPC_AD0_R R1715
GPP_CLK4P LAD0 RN1707 1 4 X1701
RN

L23 J26 LPC_AD1_R LPC_AD2 27,71 20MR3-GP

GPP_CLK4N LAD1 0R4P2R-PAD 2 3 LPC_AD3 27,71
GPP CLK port Device CLKREQ# H29 LPC_AD2_R
LPC LAD2 X-32D768KHZ-67-GP
P25 H28 LPC_AD3_R

2
GPP_CLK5P LAD3

2
0 New Card 0 M25
GPP_CLK5N LFRAME#
G28
LPC_FRAME# 27,71
J25
LDRQ0#
1 WLAN 1 P29
GPP_CLK6P LDRQ1#_CLK_REQ6#_GPIO49
AA18
P28 AB19 INT_SERIRQ
GPP_CLK6N SERIRQ_GPIO48 INT_SERIRQ 27
2 WWAN 2 32K_X2 C17171 SC18P50V2JN-1-GP
2
N26
GPP_CLK7P
3 LAN 3 if LAN support Wake on S5, N27
GPP_CLK7N
G21 ALLOW_STOP 6
B
4 X do not use clock from FCH, T29
ALLOW_LDTSTP_DMA_ACTIVE#
H21 B
GPP_CLK8P PROCHOT# APU_PROCHOT#_VDDIO 6
have use X'tal T28
GPP_CLK8N LDT_PG
K19
H_CPUPWRGD 6,36,42,71
5 X G22 APU_STOP#
R1716 CPU LDT_STP#
J24
48M_OSC LDT_RST# APU_RST# 6,83
6 X 32 CLK_PCH_48M 1 2 L25
14M_25M_48M_OSC
7 X 22R2J-2-GP C1 32K_X1
32K_X1
Use 48Mhz CLK For 5138 25M_X1 32K_X2
1

8 X L26
25M_X1 RTC 32K_X2
C2
C1721 DY R1701 1
D2 2 0R0402-PAD
SC10P50V2JN-4GP RTCCLK INTRUDER_ALERT# 1 TP1701TPAD14 PCH_SUSCLK_KBC 27
2

B2
25M_X2 INTRUDER_ALERT#
L27 B1 RTC_AUX_S5
25M_X2 VDDBT_RTC_G
0811 EMI HUDSON-M1-1-GP

1
C1718
SC1U6D3V2KX-GP
2

25M_X1

R1717
1 2 1MR2J-1-GP 25M_X2

A X01 A
1

R1766
1KR2J-1-GP
<Core Design>
2

X02
X01 Wistron Corporation
2

C1719 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

SC18P50V2JN-1-GP X02 Taipei Hsien 221, Taiwan, R.O.C.
1

Title
C1720
SC18P50V2JN-1-GP HUDSON-M1_ACPI/PCI/CLK(1/6)
2

X1702
XTAL-25MHZ-155-GP Size Document Number Rev
A2
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 17 of 109

5 4 3 2 1
 5 4 3 2 1

0720 POP
3D3V_S5 SSID = FCH
Integrated PU is not
RN1802
1 4 USB_OC#2 supported when the pin is
2 3 USB_OC#1
configured for USB over FCH1D 4 OF 5
SRN10KJ-5-GP current function.
RN1801 HUDSON-1
1 4 SCLK1
SDATA1 R1811
2 3 0720: Change From 2.2K and POP J2
PCI_PME#_GEVENT4# USBCLK_14M_25M_48M_OSC
A10
11K8R2F-GP
K1
RI#_GEVENT22# USB_RCOMP
SRN10KJ-5-GP D3 G19 2 1
SPI_CS3#_GBE_STAT1_GEVENT21# USB_RCOMP
27,36,44,46,47 PM_SLP_S3# F1
SLP_S3# USB MISC
RN1803 27,44 PM_SLP_S5# H1
FCH_TEST0 R1804 1 PM_PWRBTN#_R SLP_S5#
1 8 27 PM_PWRBTN# 2 0R0402-PAD F2
FCH_TEST1 PWR_BTN#
D 2 7 36 FCH_PWRGD H5 D
FCH_TEST2 PWR_GOOD USB 1.1
3 DY 6
FCH_TEST0
G6
SUS_STAT# USB_FSD1P_GPIO186
J10
4 5 B3 H11
FCH_TEST1 TEST0 USB_FSD1N
C4
FCH_TEST2 TEST1_TMS
SRN2K2J-2-GP F6 H9
R1807 1 EC_A20M#_R TEST2 USB_FSD0P_GPIO185
27 H_A20GATE 2 0R0402-PAD AD21 J8
R1808 1 EC_KB_RST#_R GA20IN_GEVENT0# USB_FSD0N
27 H_RCIN# 2 0R0402-PAD AE21 Pair USB Device
EC_SCI# KBRST#_GEVENT1#
27 EC_SCI# K2 B12
R1801 1 EC_SMI#_R LPC_PME#_GEVENT3# USB_HSD13P
2 0R0402-PAD J29 A12 0 USB 2.0 EXT.Port1
integrated PU 0817 Add 27 EC_SMI#
H2
LPC_SMI#_GEVENT23# USB_HSD13N
27 PCH_WAKE# R1825 1 2 0R0402-PAD GEVENT5#
J1
SYS_RESET#_GEVENT19# USB_HSD12P
F11 1 Mini Card1 (WLAN)
R1826 1 20R2J-2-GP PCIE_WAKE#_R H6 E11
27,31 PCIE_WAKE#
R1803 1 DY 2 10KR2J-3-GP EC_SCI# DY F3
WAKE#_GEVENT8# USB_HSD12N
2 USB 2.0 EXT.Port1
R1805 1 EC_SWI# IR_RX1_GEVENT20#
DY 2 10KR2J-3-GP 6,36 H_THERMTRIP# J6 E14
R1809 10KR2J-3-GP NB_PWRGD THRMTRIP#_SMBALERT#_GEVENT2# USB_HSD11P
3D3V_S0 1 2 AC19
NB_PWRGD USB_HSD11N
E12 3 NC
PM_PWRBTN# ACPI/WAKE UP EVENTS
R1806 1 2 10KR2J-3-GP 27 RSMRST#_KBC R1810 1 2 0R0402-PAD RSMRST#_R G1 J12 4 NC
RSMRST# USB_HSD10P
J14
USB_HSD10N
AMD recommand external PU AD19 5 NC

1
CLK_REQ4#_SATA_IS0#_GPIO64
31 PCIE_CLK_LAN_RQ1# AA16 A13 USB_PP9 32
C1801 CLK_REQ3#_SATA_IS1#_GPIO63 USB_HSD9P
DY AB21
SMARTVOLT1_SATA_IS2#_GPIO50 USB_HSD9N
B13 USB_PN9 32 6 USB 2.0 EXT.Port1
SCD1U10V2KX-5GP AC18

2
CLK_REQ0#_SATA_IS3#_GPIO60
AF20
SATA_IS4#_FANOUT3_GPIO55 USB_HSD8P
D13 7 CCD Camera
0812 AE19
SATA_IS5#_FANIN3_GPIO59 USB_HSD8N
C13
R1815 1 2 0R0402-PAD HDA_SPKR_R AF19 8 NEWCARD
3D3V_S0 29 HDA_SPKR SPKR_GPIO66
AD22 G12 USB_PP7 49
14 SMB_CLK SCL0_GPIO43 USB_HSD7P
14 SMB_DATA
AE22
SDA0_GPIO47 USB_HSD7N
G14 USB_PN7 49 9 Card Reader
SCLK1 F5
SDATA1 SCL1_GPIO227 USB 2.0
F4
SDA1_GPIO228 USB_HSD6P
G16 USB_PP6 82 10 NC
AH21 G18 USB_PN6 82
R1816 1 CLK_PCIE_WLAN_REQ#_R CLK_REQ2#_FANIN4_GPIO62 USB_HSD6N
65 CLK_PCIE_WLAN_REQ# 2 AB18
CLK_REQ1#_FANOUT4_GPIO61 11 NC
R1812 1
DY 2 10KR2J-3-GP EC_SMI# 0R0402-PAD E1 D16
IR_LED#_LLB#_GPIO184 USB_HSD5P
AJ21
SMARTVOLT2_SHUTDOWN#_GPIO51 USB_HSD5N
C16 12 NC
integrated PU H4
DDR3_RST#_GEVENT7#
D5
GBE_LED0_GPIO183 USB_HSD4P
B14 13 NC
D7 A14
GBE_LED1_GEVENT9# USB_HSD4N
G5
GBE_LED2_GEVENT10#
K3 E18
R1817 1 CLKREQG# GBE_STAT0_GEVENT11# USB_HSD3P
integrated PU 85 PEG_CLKREQ# 2 0R0402-PAD AA20 E16
CLK_REQG#_GPIO65_OSCIN USB_HSD3N
R1813 1 H_A20GATE GPIO
DY 2 10KR2J-3-GP J16 USB_PP2 82
R1814 1 H_RCIN# USB_OC7# USB_HSD2P
C DY 2 10KR2J-3-GP TPAD14-GP TP1801 1 H3 J18 USB_PN2 82
C
EC_SWI# BLINK_USB_OC7#_GEVENT18# USB_HSD2N
27 EC_SWI# D1
TPAD14-GP TP1802 USB_OC5# USB_OC6#_IR_TX1_GEVENT6#
1 E4 B17 USB_PP1 65
56 ODD_DA_Q
A00 D4
USB_OC5#_IR_TX0_GEVENT17# USB_HSD1P
A17 RN1806
USB_OC4#_IR_RX0_GEVENT16# USB_HSD1N USB_PN1 65
R1818 1 20R2J-2-GP SATA_ODD_PRSNT#_R E8 SCL2 1 4
56 SATA_ODD_PRSNT# USB_OC3#_AC_PRES_TDO_GEVENT15#
RN1804
DY F7 A16 USB_PP0 61
SDAT2 2 3
61 USB_OC#2 USB_OC2#_TCK_GEVENT14# USB_HSD0P
E7 B16 USB_PN0 61
SMB_CLK 61 USB_OC#1 USB_OC1#_TDI_GEVENT13# USB_HSD0N
1 4 F8 SRN10KJ-5-GP
SMB_DATA EC1801 1 USB_OC0#_TRST#_GEVENT12#
2 3 2
SC22P50V2JN-4GP 21 HDA_SDOUT USB OC

SRN2K2J-1-GP HD AUDIO if not used SMBUS or GPIO ,PD 10K

R1819 1 2 33R2J-2-GP HDA_BITCLK M3 D25 SCL2
29 HDA_CODEC_BITCLK R1820 33R2J-2-GP HDA_SDOUT AZ_BITCLK SCL2_GPIO193 SDAT2
1 2 N1 F23
29 HDA_CODEC_SDOUT HDA_SDIN0 AZ_SDOUT SDA2_GPIO194 SCLK3
29 HDA_SDIN0 L2 B26
AZ_SDIN0_GPIO167 SCL3_LV_GPIO195 SDATA3 SCLK3 6
M2 E26
AZ_SDIN1_GPIO168 SDA3_LV_GPIO196 SDATA3 6
M1 F25
AZ_SDIN2_GPIO169 EC_PWM0_EC_TIMER0_GPIO197
M4 E22
R1821 33R2J-2-GP HDA_SYNC AZ_SDIN3_GPIO170 EC_PWM1_EC_TIMER1_GPIO198
1 2 N2 F22
29 HDA_CODEC_SYNC R1822 33R2J-2-GP HDA_RST# AZ_SYNC EC_PWM2_EC_TIMER2_GPIO199 EC_PWM2 21
1 2 P2 E21
29 HDA_CODEC_RST# AZ_RST# EC_PWM3_EC_TIMER3_GPIO200 EC_PWM3 21
G24 0719 AMD Confirm

1
RN1805 EC1802 GBE_COL KSI_0_GPIO201
T1 G25
8 1 HDA_SDIN0 SC180P50V2JN-1GP DY GBE_CRS T4
GBE_COL GBE LAN KSI_1_GPIO202
E28
HDA_CODEC_BITCLK GBE_CRS KSI_2_GPIO203 3D3V_S5
7 2 L6 E29

2
GBE_MDCK KSI_3_GPIO204
6 3 2 R1823 1GBE_MDIO L5 D29
5
DY 4 HDA_CODEC_RST#
3D3V_S5
10KR2J-3-GP T9
GBE_MDIO KSI_4_GPIO205
D28
GBE_RXCLK KSI_5_GPIO206
U1 C29 RN1809
SRN10KJ-6-GP GBE_RXD3 KSI_6_GPIO207
RN1807 U3 C28
GBE_RXD2 KSI_7_GPIO208 SCLK3
1 4 T2 1 4
GBE_RXD1 SDATA3
2 3 U2 B28 2 3
GBE_RXD0 KSO_0_GPIO209
T5 A27
GBE_RXERR GBE_RXCTL_RXDV KSO_1_GPIO210
SRN10KJ-5-GP V5 B27
GBE_RXERR KSO_2_GPIO211 SRN2K2J-1-GP
P5 D26
GBE_TXCLK KSO_3_GPIO212
Rename 0712 M5
GBE_TXD3 KSO_4_GPIO213
A26
R1824 RN1808 P9 C26
100KR2J-1-GP GBE_TXD2 KSO_5_GPIO214
Confirm with SW, RSMRST# from KBC is push-pull. 1 4 T7
GBE_TXD1 KSO_6_GPIO215
A24
2 1 RSMRST#_KBC 2 3 P7 B25
It can be drived high by SW. GBE_TXD0 KSO_7_GPIO216
M7 A25
GBE_TXCTL_TXEN KSO_8_GPIO217
SRN10KJ-5-GP P4 D24
GBE_PHY_PD KSO_9_GPIO218
M9 B24
GBE_PHY_INTR GBE_PHY_RST# KSO_10_GPIO219
V7 C24
B GBE_PHY_INTR KSO_11_GPIO220 B
B23
TPAD14-GP TP1803 TP_DEBUG_DAT KSO_12_GPIO221
1 E23 A23
TPAD14-GP TP1804 TP_DEBUG_CLK PS2_DAT_SDA4_GPIO187 KSO_13_GPIO222
1 E24 D22
TPAD14-GP TP1805 SPI_CS2# PS2_CLK_SCL4_GPIO188 KSO_14_GPIO223
1 F21 C22
TPAD14-GP TP1806 GPO160 SPI_CS2#_GBE_STAT2_GPIO166 KSO_15_GPIO224
1 G29 A22
FC_RST#_GPO160 KSO_16_GPIO225
B22
KSO_17_GPIO226
D27
PS2KB_DAT_GPIO189
F28
PS2KB_CLK_GPIO190 EMBEDDED CTRL
F29
PS2M_DAT_GPIO191
E27
PS2M_CLK_GPIO192

HUDSON-M1-1-GP

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
HUDSON-M2(2/6)
Size Document Number Rev
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 18 of 109
5 4 3 2 1
 5 4 3 2 1

0721 Change CAP to 10n FCH1B 2 OF 5

HUDSON-1

56 SATA_TXP0 C1901 1 2SCD01U16V2KX-3GP SATA_TXP0_C AH9 SATA_TX0P FC_CLK AH28

SSID = FCH
56 SATA_TXN0 C1902 1 2SCD01U16V2KX-3GP SATA_TXN0_C AJ9 AG28
SATA_TX0N FC_FBCLKOUT
SATA HDD FC_FBCLKIN AF26
56 SATA_RXN0_C AJ8 SATA_RX0N
56 SATA_RXP0_C AH8 SATA_RX0P FC_OE#_GPIOD145 AF28 GPIOD[150:128] are open drain GPIO pins
FC_AVD#_GPIOD146 AG29
56 SATA_TXP1 C1903 1 2SCD01U16V2KX-3GP SATA_TXP1_C AH10 AG26 where as GPO160 is an open drain GPO pin.
C1904 1 SATA_TX1P FC_WE#_GPIOD148
56 SATA_TXN1 2SCD01U16V2KX-3GP SATA_TXN1_C AJ10 SATA_TX1N FC_CE1#_GPIOD149 AF27 These pins are not programmed to GPIO mode by default.
SATA ODD FC_CE2#_GPIOD150 AE29
D 56 SATA_RXN1_C AG10 SATA_RX1N FC_INT1_GPIOD144 AF29 D
56 SATA_RXP1_C AF10 SATA_RX1P FC_INT2_GPIOD147 AH27

PLACE SATA AC DECOUPLING AG12 GPIOD AJ27

SATA_TX2P FC_ADQ0_GPIOD128
AF12 AJ26
CAPS CLOSE TO FCH SATA_TX2N FC_ADQ1_GPIOD129
AH25
FC_ADQ2_GPIOD130
AJ12 SATA_RX2N FC_ADQ3_GPIOD131 AH24
AH12 SATA_RX2P FC_ADQ4_GPIOD132 AG23 If use as GPIO, need to pull up to 1.8V_RUN
FC_ADQ5_GPIOD133 AH23
AH14 SATA_TX3P FC_ADQ6_GPIOD134 AJ22
AJ14 SATA_TX3N FC_ADQ7_GPIOD135 AG21
FC_ADQ8_GPIOD136 AF21
AG14 SATA_RX3N FC_ADQ9_GPIOD137 AH22
AF14 SATA_RX3P FC_ADQ10_GPIOD138 AJ23
FC_ADQ11_GPIOD139 AF23
AG17 SATA_TX4P FC_ADQ12_GPIOD140 AJ24
AF17 SATA_TX4N FC_ADQ13_GPIOD141 AJ25
FC_ADQ14_GPIOD142 AG25
AJ17 SATA_RX4N FC_ADQ15_GPIOD143 AH26
AH17 SATA_RX4P
SERIAL ATA
AJ18 SATA_TX5P
AH18 SATA_TX5N FANOUT0_GPIO52 W5
FANOUT1_GPIO53 W6 SATA_ODD_PW RGT 56 support ODD Zero power
AH19 Y9 FCH_PROCHOT#_C 1
SATA_RX5N FANOUT2_GPIO54 TP1902
AJ19 SATA_RX5P
FANIN0_GPIO56 W7
1D1V_SATA_S0 1KR2F-3-GP V9
R1902 1 FANIN1_GPIO57
2 SATA_CALP AB14 SATA_CALRP FANIN2_GPIO58 W8
C R1903 1 2 SATA_CALN AA14 C
931R2F-1-GP SATA_CALRN GPIO171
TEMPIN0_GPIO171 B6
A6 FCH_USB3.0PORT_EN#
TEMPIN1_GPIO172 MB_THRMDA_FCH
68 SATA_LED# AD11 SATA_ACT#_GPIO67 TEMPIN2_GPIO173 A5
B5 APU_TALERT# R1904 1 2 0R0402-PAD APU_ALERT#_FCH 6
TEMPIN3_TALERT#_GPIO174
TEMP_COMM C7
HW MONITOR PSW _CLR#
VIN0_GPIO175 A3
AD16 B4 VRAM_SIZE1
SATA_X1 VIN1_GPIO176 VRAM_SIZE2
VIN2_GPIO177 A4
C5 MEM_1V5
VIN3_GPIO178 MEM_1V35
[checklist]:integrated Clock Mode=>Left unconnected VIN4_GPIO179 A7
B7 VIN_VDDIO
VIN5_GPIO180 VIN_VDDR
VIN6_GBE_STAT3_GPIO181 B8
AC16 A8 GPIO182
SATA_X2 VIN7_GBE_LED3_GPIO182

FCH_SPI_DI SPI ROM

J5 SPI_DI_GPIO164 NC#G27 G27 VDDIO MEM_1V5 MEM_1V35
TPAD14-GP TP621 FCH_SPI_SI E2 Y2
TPAD14-GP TP620 FCH_SPI_CLK SPI_DO_GPIO163 NC#Y2
K4 SPI_CLK_GPIO162 1.5V H Don't Care
TPAD14-GP TP619 FCH_SPI_CS0# K9
TPAD14-GP TP618 FCH_SPI_W P# SPI_CS1#_GPIO165
G2 ROM_RST#_GPIO161 1.35V L H
TPAD14-GP TP617
HUDSON-M1-1-GP

B XTAL B

1'nd 82.30020.851
2'nd 82.30020.791 3D3V_S5

[VRAM_SIZE1:VRAM_SIZE2]

1
RN1902
GPIO171
R1908 LL=512M / HL=1G / LH=2G
1 8 1G

10KR2J-3-GP
2 7 FCH_USB3.0PORT_EN#
3 6 MEM_1V5

2
4 5 MB_THRMDA_FCH

SRN10KJ-6-GP VRAM_SIZE1
VRAM_SIZE2

1
R1909 R1910
RN1901

10KR2J-3-GP

10KR2J-3-GP
1 8 VIN_VDDR
2 7 GPIO182

2
3 6 VIN_VDDIO
4 5 MEM_1V35 512M
SRN10KJ-6-GP

<Core Design>
A if not used HWM or GPIO ,PD 10K A

Wistron Corporation
R1911 1 2 PSW _CLR# 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
10KR2J-3-GP Taipei Hsien 221, Taiwan, R.O.C.

Title

HUDSON-M1 SATA/HWM/SPI(3/6)
Size Document Number Rev
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 19 of 109

5 4 3 2 1
 5 4 3 2 1

3D3V_S0 3D3V_FCH_VDDIO_S0
SSID = FCH
R2002 1 2 0R0402-PAD

SC4D7U6D3V5KX-3GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
1

1
C2002

C2003

C2004

C2001
2

2
1D8V_S0

A00 1 DY 2 VDDIO_18_FC
FCH1C 3 OF 5

SC4D7U6D3V5KX-3GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
D R2003 1D1V_VDDCR_S0 1D1V_S0 D
HUDSON-1

1
0R2J-2-GP 131mA

2
C2005
DY DY POWER

C2006

C2007

C2008
DY DY R2030 R2004 0R0603-PAD X01
AH1 N13 510mA 1 2

2
0R0402-PAD-2-GP VDDIO_33_PCIGP VDDCR_11
V6 R15
VDDIO_33_PCIGP VDDCR_11

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC10U6D3V5KX-1GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
Y19 N17

1
VDDIO_33_PCIGP VDDCR_11

1
AE5 U13
VDDIO_33_PCIGP VDDCR_11 DY DY

C2009

C2014

C2010

C2015

C2011
AC21 U17
3D3V_S0 VDDIO_33_PCIGP VDDCR_11
AA2 V12

2
L2002 VDDIO_33_PCIGP VDDCR_11
AB4 V18
BLM15AG221SS1D-GP VDDIO_33_PCIGP VDDCR_11
AC8 W12
VDDPL_3.3V_PCIE VDDIO_33_PCIGP CORE S0 VDDCR_11 1D1V_CKVDD_S0 1D1V_S0
1 2 AA7
VDDIO_33_PCIGP VDDCR_11
W18 33 ohm 3A
68.00084.E21 AA9
VDDIO_33_PCIGP

SC2D2U6D3V3KX-GP

SCD1U10V2KX-5GP
AF7 L2003

1
VDDIO_33_PCIGP CLKGEN I/O
220 ohm 300mA AA19 K28 TBD 1 2
DY VDDIO_33_PCIGP VDDAN_11_CLK

C2012

C2013
K29 PBY160808T-330Y-N-GP
VDDAN_11_CLK

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

SC10U6D3V5KX-1GP
PCI/GPIO I/O J28 68.00206.141

1
VDDAN_11_CLK
K26
VDDAN_11_CLK

C2016

C2017

C2018

C2019

C2020
FLASH I/O
VDDAN_11_CLK
J21 DY
71mA AF22 J20

2
VDDIO_18_FC VDDAN_11_CLK
AE25 K21
1D1V_S0 1D1V_PCIE_S0 VDDIO_18_FC VDDAN_11_CLK
AF24 J22
L2004 VDDIO_18_FC VDDAN_11_CLK
AC22
PBY160808T-330Y-N-GP VDDIO_18_FC
1 2 V1 VDDRF_GBE_S 1 2 R2005
VDDRF_GBE_S 0R0402-PAD
68.00206.141 TBD
X01
SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP
PCI EXPRESS VDDIO_33_GBE_S
M10 2mA
SC10U6D3V5KX-1GP
C2021

1
33 ohm 3A 43mA AE28
VDDPL_33_PCIE
C2022

C2023

C2024

C2025
DY GBE LAN
2

2
600mA U26 L7 63mA 3D3V_S5
VDDAN_11_PCIE VDDCR_11_GBE_S
V22 L9
VDDAN_11_PCIE VDDCR_11_GBE_S
V26
VDDAN_11_PCIE
V27
VDDAN_11_PCIE
V28
VDDAN_11_PCIE VDDIO_GBE_S
M6 145mA

SCD1U10V2KX-5GP
V29 P8

1
VDDAN_11_PCIE VDDIO_GBE_S

SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP
W22
VDDAN_11_PCIE

C2026

C2027

C2028
3D3V_S0
W26
VDDAN_11_PCIE DY

2
L2005
C BLM15AG221SS1D-GP C
VDDPL_3.3V_SATA SERIAL ATA
1 2 93mA AD14
VDDPL_33_SATA
3.3V_S5 I/O
68.00084.E21 VDDIO_33_S
A21 32mA
SC2D2U6D3V3KX-GP

SCD1U10V2KX-5GP

AJ20 D21 1D1V_S5

VDDAN_11_SATA VDDIO_33_S
220 ohm 300mA AF18 B21
1

VDDAN_11_SATA VDDIO_33_S
AH20 K10
DY VDDAN_11_SATA VDDIO_33_S
C2029

C2030

AG19 L10 R2001 1 2 0R0402-PAD

VDDAN_11_SATA VDDIO_33_S
AE18 J9
2

VDDAN_11_SATA VDDIO_33_S

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
AD18 T6

1
VDDAN_11_SATA VDDIO_33_S
567mA AE16
VDDAN_11_SATA VDDIO_33_S
T8

C2031

C2032
1D1V_S0 1D1V_SATA_S0

2
L2006
PBY160808T-330Y-N-GP CORE S5 VDDCR_11_S
USB I/O
VDDCR_11_S
F26 113mA
1 2 658mA A18
VDDAN_33_USB_S VDDCR_11_S
G26
68.00206.141 A19 1D1V_S5
VDDAN_33_USB_S
SC10U6D3V5KX-1GP

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

A20 M8 TBD VDDIO_AZ L2007

VDDAN_33_USB_S VDDIO_AZ_S BLM15AG221SS1D-GP
B18
1

VDDAN_33_USB_S VDDCR_11_USB_S
33 ohm 3A B19 A11 197mA 1 2
DY DY VDDAN_33_USB_S VDDCR_11_USB_S
C2033

C2034

C2035

C2036

C2037

B20 B11
VDDAN_33_USB_S VDDCR_11_USB_S

SC10U6D3V5KX-1GP
C18
2

1
VDDAN_33_USB_S

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
C20
VDDAN_33_USB_S

C2038

C2039

C2040
D18
VDDAN_33_USB_S VDDPL_33_SYS
M21 47mA 3D3V_VPPL_SYS_S0 DY
D19

2
VDDAN_33_USB_S PLL
D20
VDDAN_33_USB_S VDDPL_11_SYS_S
L22 62mA 1D1V_VPPL_SYS_S5
3D3V_S5 3D3V_USB_S5 E19
L2008 VDDAN_33_USB_S
VDDPL_33_USB_S
F19 17mA 3D3V_USB_S5
HCB2012KF-221T30-GP 3D3V_S5
1 2 TBD C11 D6 5mA 3D3V_VDDAN_HWM_S5 L2009
VDDAN_11_USB_S VDDAN_33_HWM_S BLM15AG221SS1D-GP
68.00216.161 D11
VDDAN_11_USB_S
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SCD1U10V2KX-5GP

2ND = 68.00206.121 L20 TBD VDDXL_3.3V 1 2

1

VDDXL_33_S
68.00084.E21
DY

SC2D2U6D3V3KX-GP
C2041

C2042

C2043

C2044

C2045

220 ohm 3A DY HUDSON-M1-1-GP

1
SCD1U10V2KX-5GP
2

DY

C2046

C2047
220 ohm 300mA

2
If support USB 3.0 or LAN wake-up, pls tie to 3.3V_S5
otherwise, tie to 3.3V_S0
1D1V_S5
B L2001 B
BLM15AG221SS1D-GP
1 2 VDDAN_1.1V_USB
68.00084.E21
SC2D2U6D3V3KX-GP

SCD1U10V2KX-5GP
1

1
C2048

C2049

220 ohm 300mA

2

220 ohm 300mA

3D3V_S5 3D3V_VDDAN_HWM_S5
Codec power use3.3V,VDDIO_AZ have to tied to 3.3V
220 ohm 300mA Codec power use1.5V,VDDIO_AZ have to tied to 1.5V
220 ohm 300mA L2010 1D1V_S5 1D1V_VPPL_SYS_S5
3D3V_S0 3D3V_VPPL_SYS_S0 1 2
If use 1.5V_S5 power,have to add LDO for it extra
BLM15AG221SS1D-GP L2012
L2011 68.00084.E21 1 2 3D3V_S5 VDDIO_AZ
1

1 2 C2050 C2051 BLM15AG221SS1D-GP

BLM15AG221SS1D-GP SC2D2U6D3V3KX-GP SCD1U10V2KX-5GP 68.00084.E21
1

68.00084.E21 C2052 C2053 1 R2006 2 0R0402-PAD

2

2
1

C2054 C2055 SC2D2U6D3V3KX-GP SCD1U10V2KX-5GP

SC2D2U6D3V3KX-GP SCD1U10V2KX-5GP
2

1
C2056
2

HW Montior Not implemented Del reservaton 1D5V_S5 SC2D2U6D3V3KX-GP

2
or HW Montior balls not used GPIO
=> Decoupled cap not used If support USB 3.0 or LAN wake-up, tie to 1.1V_S5
otherwise, tie to 1.1V_S0
HW Montior Not implemented
or HW Montior balls used as GPIO
A => Bead not used A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

HUDSON-M1 Power(4/6)
Size Document Number Rev
A2
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 20 of 109
5 4 3 2 1
 5 4 3 2 1

SSID = FCH

REQUIRED STRAPS
D
VDDIO_AZ 3D3V_S0 3D3V_S5 REQUIRED SYSTEM STRAPS D

R2107
AZ_SDOUT PCI_CLK1 CLK_PCI_LPC PCI_CLK4 LPC_CLK0 LPC_CLK1 LPC_CLK2

R2103

1
PULL LOW POWER Allow USE non_Fusion CLKGEN Enable
1

1
MODE PCIE GEN2 DEBUG CLOCK mode ENABLE EC ENABLED boot timer
DY DY DY DY HIGH
R2102

R2104

R2105

R2120

R2106
DY STRAPS (Use Internal) function

2
DEFAULT DEFAULT
2

10KR2J-3-GP
Disable boot
10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP
PULL PERFORMANCE Force IGNORE Fusion DISABLE EC CLKGEN
MODE PCIE GEN1 DEBUG CLOCK mode DISABLED fail timer
LOW
STRAPS function
DEFAULT DEFAULT
DEFAULT DEFAULT (Use External) DEFAULT
18 HDA_SDOUT

17 PCI_CLK1
17,71 CLK_PCI_LPC
17 PCI_CLK4

17 PCI_CLK2

C TYPE EC_PWM2 EC_PWM3 C

17,27 LPC_CLK0
17 LPC_CLK1 ENABLED

18 EC_PW M3
Reserved 2.2-kohm 5% pull-down 2.2-kohm 5% pull-down
18 EC_PW M2
0816
1

R2110 1

R2111 1

LPC ROM Not connected. 2.2-kohm 5% pull-down

R2121 1

R2114

R2119
R2108

R2109

R2112

R2113

DY DY DY
2

2
2

SPI ROM 2.2-kohm 5% pull-down Not connected.

2K2R2F-GP

2K2R2F-GP
10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP
10KR2J-3-GP

Reserved Not connected. Not connected.

Note: EC_PWM2, EC_PWM3 default have internal 10kohm PU.

B B

DEBUG STRAPS

PCI_AD27 17
PCI_AD26 17
PCI_AD25 17
PCI_AD24 17
PCI_AD23 17
PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23

USE PCI Disable ILA USE FC USE DEFAULT

PULL PLL AUTORUN PLL PCIE STRAPS Disable PCI
HIGH MEM BOOT
1 R2115

1 R2101

1 R2116

1 R2117

1 R2118

(DEFAULT) (DEFAULT) (DEFAULT) (DEFAULT) (DEFAULT)

BYPASS Enable ILA BYPASS FC USE EEPROM Enable PCI

DYDYDYDYDY PULL PCI PLL AUTORUN PLL PCIE STRAPS MEM BOOT
LOW
A <Core Design> A
2

2
2K2R2J-2-GP

2K2R2J-2-GP

2K2R2J-2-GP

2K2R2J-2-GP

2K2R2J-2-GP

Note: FCH has 15K internal PU FOR PCI_AD[27:23] Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
HUDSON_STRAPPING_(5/6)
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 21 of 109
5 4 3 2 1
 5 4 3 2 1

SSID = FCH
FCH1E 5 OF 5
HUDSON-1

Y14 VSSIO_SATA VSS AJ2

D Y16 VSSIO_SATA VSS A28 D
AB16 VSSIO_SATA VSS A2
AC14 VSSIO_SATA VSS E5
AE12 VSSIO_SATA VSS D23
AE14 VSSIO_SATA VSS E25
AF9 VSSIO_SATA VSS E6
AF11 VSSIO_SATA VSS F24
AF13 VSSIO_SATA VSS N15
AF16 VSSIO_SATA VSS R13
AG8 VSSIO_SATA VSS R17
AH7 VSSIO_SATA VSS T10
AH11 VSSIO_SATA VSS P10
AH13 VSSIO_SATA VSS V11
AH16 VSSIO_SATA VSS U15
AJ7 VSSIO_SATA VSS M18
AJ11 VSSIO_SATA VSS V19
AJ13 VSSIO_SATA VSS M11
AJ16 VSSIO_SATA VSS L12
VSS L18
A9 VSSIO_USB VSS J7
B10 VSSIO_USB VSS P3
K11 VSSIO_USB VSS V4
B9 VSSIO_USB VSS AD6
D10 VSSIO_USB VSS AD4
D12 VSSIO_USB VSS AB7
D14 VSSIO_USB VSS AC9
D17 VSSIO_USB VSS V8
E9 VSSIO_USB VSS W9
F9 VSSIO_USB VSS W10
C F12 AJ28 C
VSSIO_USB VSS
F14 VSSIO_USB VSS B29
F16 VSSIO_USB VSS U4
C9 VSSIO_USB VSS Y18
G11 VSSIO_USB GROUND VSS Y10
F18 VSSIO_USB VSS Y12
D9 VSSIO_USB VSS Y11
H12 VSSIO_USB VSS AA11
H14 VSSIO_USB VSS AA12
H16 VSSIO_USB VSS G4
H18 VSSIO_USB VSS J4
J11 VSSIO_USB VSS G8
J19 VSSIO_USB VSS G9
K12 VSSIO_USB VSS M12
K14 VSSIO_USB VSS AF25
K16 VSSIO_USB VSS H7
K18 VSSIO_USB VSS AH29
H19 VSSIO_USB VSS V10
VSS P6
VSS N4
Y4 EFUSE VSS L4
VSS L8
D8 VSSAN_HWM
M19 VSSXL VSSPL_SYS M20

P21 VSSIO_PCIECLK VSSIO_PCIECLK H23

P20 VSSIO_PCIECLK VSSIO_PCIECLK H26
B B
M22 VSSIO_PCIECLK VSSIO_PCIECLK AA21
M24 VSSIO_PCIECLK VSSIO_PCIECLK AA23
M26 VSSIO_PCIECLK VSSIO_PCIECLK AB23
P22 VSSIO_PCIECLK VSSIO_PCIECLK AD23
P24 VSSIO_PCIECLK VSSIO_PCIECLK AA26
P26 VSSIO_PCIECLK VSSIO_PCIECLK AC26
T20 VSSIO_PCIECLK VSSIO_PCIECLK Y20
T22 VSSIO_PCIECLK VSSIO_PCIECLK W21
T24 VSSIO_PCIECLK VSSIO_PCIECLK W20
V20 VSSIO_PCIECLK VSSIO_PCIECLK AE26
J23 VSSIO_PCIECLK VSSIO_PCIECLK L21
VSSIO_PCIECLK K20

HUDSON-M1-1-GP

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 22 of 109

5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A A
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Enrico 14 AMD A00
5 4 3 2 Date: Friday, April 22, 2011 Sheet
1 23 of 109
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 24 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A A
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Enrico 14 AMD A00
5 4 3 2 Date: Friday, April 22, 2011 Sheet
1 25 of 109
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 26 of 109
5 4 3 2 1
 5 4 3 2 1

SSID = KBC X01 3D3V_AUX_KBC

MODEL_ID_DET(GPIO07) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

3D3V_AUX_KBC
PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE DV14_DIS 100.0K 10.0K 3.0V
A00

2
SA 100.0K 10.0K 3.0V Reserved 100.0K 20.0K 2.75V

1
R2710 MODELID
R2724 SB 100.0K 20.0K 2.75V 100.0K 33.0K 2.48V
47KR2F-GP 10KR2F-2-GP DV15_UMA

1
SC 100.0K 33.0K 2.48V Reserved 100.0K 47.0K 2.24V
3D3V_AUX_KBC

2
3D3V_S0 A00 100.0K 47.0K 2.24V 100.0K 64.9K 2.0V
R2702 0R0603-PAD Reserved
1 2 VBAT PCB_VER_AD
MODEL_ID_DET
Reserved 100.0K 64.9K 2.0V 100.0K 76.8K 1.87V

C2710
Reserved
2

1
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
C2709
1

1
2
R2771 0817 R2726 Reserved 100.0K 76.8 1.87V 100.0K 100.0K 1.65V
R2739 Reserved

1
2D2R3-1-U-GP C2703 100KR2F-L1-GP C2718
100KR2F-L1-GP

2
D C2702 SC2D2U10V3KX-1GP Reserved 100.0K 100.0K 1.65V SCD1U10V2KX-5GP 100.0K 143.0K 1.358V D

1
3D3V_AUX_KBC_VCC SCD1U10V2KX-5GP Reserved
1

2
SCD1U10V2KX-5GP

2
100.0K 174.0K 1.204V
SC2D2U10V3KX-1GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
Reserved
C2704

C2705

C2706

C2707

C2708
EC_AGND
1

1
C2701

Reserved 100.0K 215.0K 1.048V

EC_AGND
DY EC_AGND
2

115

102
19
46
76
88

4
U2701A 1 OF 2 C2711 1 2SC220P50V2KX-3GP
DY

VCC
VCC
VCC
VCC
VCC

AVCC

VDD
U2701B 2 OF 2
40 AD_IA KCOL[0..16] 69
104 7 PLT_RST#_EC
2 1 R2735
VREF LRESET# A_RST# 17,36
EC_AGND C2714 1 DY 2 SCD1U10V2KX-5GP 2 0R0402-PAD 31 53 KCOL0
LCLK LPC_CLK0 17,21 28 FAN_TACH1 GPIO56/TA1 KBSOUT0/JENK# KCOL1
97 3 LPC_FRAME# 17,71 117 52
PCB_VER_AD GPIO90/AD0 LFRAME# LPC_AD3 18 PM_PWRBTN# GPIO20/TA2 KBSOUT1/TCK KCOL2
98 1 LPC_AD3 17,71 18,31 PCIE_WAKE# 63 51
0816 99
GPIO91/AD1 LAD3
128 LPC_AD2 64
GPIO14/TB1 KBSOUT2/TMS
50 KCOL3
38 PSID_EC GPIO92/AD2 LAD2 LPC_AD2 17,71 18,36,44,46,47 PM_SLP_S3# GPIO01/TB2 KBSOUT3/TDI
100 127 LPC_AD1 49 KCOL4
28 CPU_THRM GPIO93/AD3 LAD1 LPC_AD1 17,71 KBSOUT4/JEN0#
126 LPC_AD0 32 48 KCOL5
3D3V_AUX_KBC LAD0 LPC_AD0 17,71 68 CHG_AMBER_LED# GPIO15/A_PWM KBSOUT5/TDO
101 125 118 47 KCOL6
28 FAN1_DAC GPIO94/DA0 SERIRQ INT_SERIRQ 17 29 KBC_BEEP GPIO21/B_PWM KBSOUT6/RDY#
105 8 62 43 KCOL7
49 LCD_TST GPIO95/DA1 GPIO11/CLKRUN# PM_CLKRUN# 17 0810 Add GPIO13/C_PWM KBSOUT7
106 9 65 42 KCOL8
GPIO96/DA2 GPIO65/SMI# L_BKLT_EN 6 GPIO32/D_PWM KBSOUT8
0816 29 ECSCI#_KBC 81 41 KCOL9
40 AD_IA_HW
1

ECSCI#/GPIO54 EC_GPIO10 TP2701 TPAD14 GPIO66/G_PWM KBSOUT9/SDP_VIS# KCOL10

124 1 66 40
R2728 SERIES_ID GPIO10/LPCPD# ECSWI#_KBC GPIO33/H_PWM KBSOUT10/P80_CLK KCOL11
79 123 22 39
Inspiron
100KR2J-1-GP 95
GPIO2 GPIO67/PWUREQ#
121 X01 68 WLAN_LED#
16
GPIO45/E_PWM KBSOUT11/P80_DAT
38 KCOL12
GPIO3/AD6 GPIO85/GA20 H_A20GATE 18 68 PWRLED# GPIO40/F_PWM KBSOUT12/GPIO64
96 122 37 KCOL13
28 VGA_THRM GPIO4/AD5 KBRST#/GPIO86 H_RCIN# 18 KBSOUT13/GPIO63
108 36 KCOL14
28 SYS_THRM
2

PSL_IN2 GPIO5/AD4 ECRST# KBSOUT14/GPIO62 KCOL15

93 85 35
SERIES_ID MODEL_ID_DET PSL_IN2#_GPIO6 VCC_POR# KBSOUT15/GPIO61/XOR_OUT KCOL16
94 27 BLON_OUT 49 34
GPIO7/AD7 GPIO52/PSDAT3/RDY# GPIO60/KBSOUT16 <------AMD Dont Have BL Keyboard
114 25 X01 33
1

68 BATT_WHITE_LED# ECSMI#_KBC GPIO16 GPIO50/PSCLK3/TDO AD_IA_HW2 40 GPIO57/KBSOUT17

6 11 PCH_WAKE# 18 113 KROW[0..7] 69
R2727 GPIO24 GPIO27/PSDAT2 65 E51_RxD GPIO87/CIRRXM/SIN_CR KROW0
109 10 KB_DET# 69 111 54
Vostro 100KR2J-1-GP 69 CAP_LED# GPIO30 GPIO26/PSCLK2 65 E51_TxD GPIO83/SOUT_CR/TRIST# KBSIN0 KROW1
14 71 TPDATA 69 55
36 S5_ENABLE GPIO34/CIRRXL GPIO35/PSDAT1 KBSIN1 KROW2
15 72 <------ TP 30 56
X01 85 PCIE_RST# 80
GPIO36 GPIO37/PSCLK1 TPCLK 69 29 AMP_MUTE#
77
GPIO55/CLKOUT/IOX_DIN_DIO KBSIN2
57 KROW3
39 BAT_IN# 17 PCH_SUSCLK_KBC
2

GPIO41 GPIO00/EXTCLK KBSIN3 KROW4

70,82 LID_CLOSE# 17 58
GPIO42/TCK KBSIN4 KROW5
20 70 BAT_SCL 39,40 <------ BATTERY / CHARGER 59
18 RSMRST#_KBC GPIO43/TMS GPIO17/SCL1 KBSIN5 KROW6
18,44 PM_SLP_S5# 21 69 BAT_SDA 39,40 13 60
GPIO44/TDI GPIO22/SDA1 PECI KBSIN6 KROW7
23 67 SML1_CLK 6,85 <------ CPU -Temp / eDP(Reserved) 12 61
60 EC_SPI_WP# GPIO46/CIRRXM/TRST# GPIO73/SCL2 VTT KBSIN7
38 RCID 26 68 SML1_DATA 6,85
PSL_IN1 GPIO51 GPIO74/SDA2
C 73 119 PM_LAN_ENABLE 31 C
0817 PSL_OUT 74
PSL_IN1_GPIO70 GPIO23/SCL3
120 EC_ENABLE#_1 NPCE795PA0DX-GP-U
VBKUP PSL_OUT_GPIO71 GPIO31/SDA3 PROCHOT_EC
RTC_AUX_S5 2 R2772 1 0R0402-PAD 75 24
VBKUP GPIO47/SCL4
82 28
65 WIFI_RF_EN GPIO75 GPIO53/SDA4 LCD_TST_EN 49
83
65 BLUETOOTH_EN GPO76/SHBM
84
36,46 1D1V_S5_PWRGD GPIO77
91
GPIO81
61 USB_PWR_EN#
110
GPO82/IOX_LDSH/TEST# X01
112 90 EC_SPI_CS#_R 2 R2736 1 33R2J-2-GP
GPIO84/IOX_SCLK/XORTR# F_CS0# EC_SPI_CS# 60
107 92 EC_SPI_CLK_R 2 R2719 1 33R2J-2-GP
36 IMVP_PWRGD GPIO97 F_SCK EC_SPI_CLK 60 3D3V_AUX_KBC 3D3V_AUX_KBC
86 EC_SPI_DI_R 2 R2737 1 0R0402-PAD
F_SDI/F_SDIO1 EC_SPI_DI 60
87 EC_SPI_DO_R 2 R2722 1 33R2J-2-GP R2770
F_SDIO/F_SDIO0 EC_SPI_DO 60
VCORF 44 KB_DET# 1 2

1
VCORF ECRST#
0817 Vendorrecommand Add 10 nF-0.1uF close to pin
1

R2705 100KR2J-1-GP
AGND

C2712 R2773 10KR2J-3-GP

GND
GND
GND
GND
GND
GND

VGA_THRM C2719
1 DYSCD1U10V2KX-5GP
2 SC1U10V3ZY-6GP 100KR2J-1-GP X02
2

2
SCD1U10V2KX-5GP

1
SYS_THRM C2720
1 DY 2 NPCE795PA0DX-GP-U
DY 0R0402-PAD R2783
18
45
78
89
116
5

103

2
C2715 1 2
SCD1U10V2KX-5GP PMBS3906-GP
CPU_THRM C2721
1 DY 2 1
28,36,85 PURE_HW_SHUTDOWN#

2
Q2701

SC1U6D3V2KX-GP
EC_AGND

D2705
NOTE:

3
18 EC_SMI# 1
Locate resistors R2719 and R2722 close DY
EC_AGND to the NPCE791L. 3 ECSMI#_KBC

2
2 R2711 1
0R0402-PAD
BAS16-6-GP
NOTE:
83.00016.K11
X02 Connect GND and AGND planes via either
EC_AGND 2ND = 83.00016.F11
0R resistor or one point layout connection.
0R0402-PAD 1 2 R2781

D2701
X01
EC_GPIO47 High Active EC GPIO standard PH/PL
1
0729 Add from page94 to here 18 EC_SWI# DY R2780 1
ECSWI#_KBC 2 0R0402-PAD 3D3V_AUX_KBC
3
B 2 B
BAS16-6-GP RN2701
83.00016.K11 Q2702
BAT_SCL 3 2
R2774 PROCHOT_EC G
2ND = 83.00016.F11 BAT_SDA 4 1
1 2 L_BKLT_EN R2733
DY D H_PROCHOT#_EC 2 1 H_PROCHOT# 6,40
1

0R0402-PAD SRN4K7J-8-GP
0R0402-PAD 1 2 R2782
100KR2J-1-GP R2732 S RN2703
DY
100KR2J-1-GP

BAT_IN# 4 1
2N7002K-2-GP AC_IN#_KBC
D2704 3 2
2

18 EC_SCI#
1
DY 84.2N702.J31 0630 Modify: SRN100KJ-6-GP
ECSCI#_KBC Removed LID_CLOSE#
3 2nd = 84.07002.I31 PH 10K on RN2705. X01
2 RN2705
S5_ENABLE 4 1
BAS16-6-GP EC_ENABLE#_1 3 DY 2
X01
PSL_IN2
83.00016.K11
2ND = 83.00016.F11
PSL SOLUTION 10mW SOLUTION SRN10KJ-5-GP
2 R2778 1 0R0402-PAD ECRST# R27131 2 10KR2J-3-GP
PSL X01
BAT54CPT-GP
R2704
3D3V_AUX_S5 3D3V_AUX_KBC VBACKUP 3D3V_S0
1 1 2 RTC_POWER R2756
2 1 RTC_POWER 1 R2734 2 RTC_POWER
330KR2J-L1-GP R2712
0R0402-PAD 0R2J-2-GP
68 KBC_PWRBTN# 3 83.R2003.E81 10mW FAN_TACH1 1 2
10mW 2ND = 83.00054.Q81
2
3D3V_AUX_S5
X01 3D3V_AUX_S5
PSL 10KR2J-3-GP

C2722
D2702 1 2 AC_IN#_KBC 1 R2763 PSL_IN1
KBC_ON# R2775 2 E51_RxD
1 2 AC_OK 2 R2768 1 PSL_IN1 0R2J-2-GP 1 R2708 2 10KR2J-3-GP
DY
RN2706 SCD1U10V2KX-5GP 40 PWR_CHG_ACOK 10mW
S

0R0402-PAD 0R0402-PAD
KBC_ON#_R
4
3
1
2 KBC_ON#_GATE G G
Q2703 PSL 0702 Modify:
PSL_IN1
DMP2130L-7-GP Rename EC_GPIO70 to PSL_IN1
SRN10KJ-5-GP X01
D2703 D 2ND = 84.03413.A31 0804 Add short pad separate
1

2 BLUETOOTH_EN 1 R2709 2 10KR2J-3-GP

D

C2713 DY 84.02130.031
10mW 3 SCD1U10V2KX-5GP
2

A AC_IN# 40 A

2ND = 83.00054.Q81 1
3D3V_AUX_KBC G
Q2704 PSL_OUT
83.R2003.E81 3D3V_AUX_KBC
BAT54CPT-GP X01 D KBC_ON#
10mW <Core Design>
2N7002K-2-GP 1 R2767 KBC_ON#_R EC_ENABLE#_1
AC_IN#_KBC DY 2
0R2J-2-GP
S
G Q2705 2N7002K-2-GP 84.2N702.J31 Wistron Corporation
PSL_OUT G
20100906 X01 Modify: S5_ENABLE PSL_IN1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
D 2nd = 84.07002.I31
1

Add C2722 0.1uF between Q2703 G&S pin for DY Taipei Hsien 221, Taiwan, R.O.C.
fixed leakage voltage to 3D3V_AUX_KBC under D
S KBC_ON# KBC_ON#_R
PSL 1 R2766 2
DC mode.
S 0702 Modify: 0R2J-2-GP DY R2769 Title
20100917 X01:
Q2706 10mW 100KR2J-1-GP
Add Q2706 2N7002 to avoid leakage loop from 84.2N702.J31
Rename EC_GPIO71 to PSL_OUT
KBC Nuvoton NPCE795PA0DX Rev
2

3D3V_S5 to 3D3V_AUX_KBC issue when 10mW 2N7002K-2-GP

2ND = 84.2N702.031 Size Document Number
latched fail timing. Un-stuff C2713 to follow the standard schematics. 84.2N702.J31 A2
A00
2nd = 84.07002.I31 Enrico 14 AMD
Date: Friday, April 22, 2011 Sheet 27 of 109

5 4 3 2 1
 5 4 3 2 1

SSID = Thermal
X01
3D3V_AUX_KBC
Fan controller P2793
0721 Pull-down: full speed, R2830 dummy.
5V_S0

1
U2802
3D3V_S0 1 R2828 2 3D3V_S0_thermal DY R2816
0R0402-PAD 107KR2F-GP
1 2 R2830
DY 0R2J-2-GP 1 FON# GND 8

1
C2830 C2827 5V_S0 2 VIN GND 7
FAN_VCC

2
3 VOUT GND 6
ADJ 27 FAN1_DAC 4 VSET GND 5 X02

SC10U6D3V5KX-1GP
D D

1
SCD1U10V2KX-5GP
C2818 C2832
P2793AB0-GP DY

SC4D7U6D3V3KX-GP
1

SCD1U10V2KX-5GP
R2817 C2831

2
0R2J-2-GP DYSCD1U10V2KX-5GP

2
3D3V_S0

2
Layout notice : AFTP2802
Both DXN and DXP routing 10 mil

1
R2820 AFTE14P-GP
trace width and 10 mil spacing. AFTP2803
X01 10KR2J-3-GP
AFTE14P-GP
P2800_DXP
DY
U2801 FAN1

1
2
1

2ND = 84.03904.P11
SC390P50V3JN-GP

SC2200P50V2KX-2GP
5

1
3

1
84.03904.L06
NTC-100K-8-GP

C2829

C2828
3D3V_S0_thermal 5 4 SYS_THRM 27 27 FAN_TACH1 1 R2829 2 FAN_TACH1_C 3
DY Q2808 VCC TDR
R2802

1 6 3 0R0402-PAD 2
PMBS3904-1-GP 7
DXP TDL
2
CPU_THRM 27 *Layout* 15 mil
2

2
T8_P2800 DXN GND ADJ FAN_VCC FAN_VCC
8 1 1
2

OTZ ADJ

1
P2800_DXN X02 4
2.System Sensor, Put on palm rest

2
P2800EB0-GP R2819 D2802 FOX-CON3-6-GP-U
THERM_SYS_SHDN#1 X01 AFTP2801

1
2 C2816
R2823
0R0402-PAD 1.H/W T8 Shutdown 1 2 FAN_VCC
C2815
DY CH551H-30PT-GP C2817 AFTE14P-GP
20.D0210.103
X02 DY DY

SC4D7U6D3V3KX-GP
5V_S0 DY 83.R5003.C8F SC2200P50V2KX-2GP
74.02800.B71

SCD1U16V2KX-3GP
2

2
0R2J-2-GP
C C
2ND = 83.R5003.H8H
3rd = 83.5R003.08F
ADJ floating : OTZ shutdown temperature=85°C
ADJ pull-down : OTZ shutdown temperature=90°C 3D3V_AUX_S5
3D3V_S0
ADJ pull-up : OTZ shutdown temperature=95°C

1
D2801 R2831
BAT54PT-GP 100KR2J-1-GP
83.00054.T81 DY
2ND = 83.BAT54.D81 Q2805

2
3rd = 83.BAT54.S81 S THERM_SYS_SHDN#

2
27,36,85 PURE_HW _SHUTDOW N# D
X02
G R2810 1 2 0R0402-PAD 3D3V_S0

1
C2811 2N7002K-2-GP

VGA Thermal sensor P2800 R2818

10KR2J-3-GP
DY DY SCD1U10V2KX-5GP 84.2N702.J31

2
2nd = 84.07002.I31

2
X02
B P2800_VGA_DXP B
85 P2800_VGA_DXP 0806 Rename U2803
Layout notice : 11/4 Vendor recommand 3D3V_S0
1

Both DXN and DXP routing 10 mil 3D3V_VGA_S0_thermal5 4 VGA_THRM 27

DY C2812 VCC TDR
trace width and 10 mil spacing. 6 DXP TDL 3 1R2813 2
SC2200P50V2KX-2GP 7 DY 2 DY 470KR2J-2-GP
2

DXN GND
1

2
8 1

150R2F-1-GP
OTZ ADJ

R2832
P2800_VGA_DXN R2815

0R2J-2-GP
85 P2800_VGA_DXN
100KR2J-1-GP DY DY

R2805
DY
0806 Rename P2800EB0-GP
U2805
2

1
R2814
3D3V_S0 1
DY
20R2J-2-GP
3D3V_VGA_S0_thermal 74.02800.B71 0809 Vendor review and pop ADJ_G709 1 SET VCC 5

THERM_SYS_SHDN# 1 DY
2 GND DY
2T8_G709 3 OUT# HYST 4
1

C2813 C2814 R2811 0R2J-2-GP

24K3R2F-1-GP
1

2
DY DY C2808

1
G709T1UF-GP R2861
SC10U6D3V5KX-1GP
2

DY

R2812
86.9 ℃ SCD1U10V2KX-5GP DY DY 0R2J-2-GP
SCD1U10V2KX-5GP

2
2

1
R(KΩ)= 0.0012*T^2- 0.9308T+ 96.147
<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
Thermal/Fan
Document Number
Controllor EMC2102 Rev
A3 A00
Enrico 14 AMD
Date: Friday, April 22, 2011 Sheet 28 of 109

5 4 3 2 1
 5 4 3 2 1

AUD_SPK_R+ 5V_S0 +PVDD 5V_S0

SSID = AUDIO AUD_SPK_R-
AUD_SPK_L-
AUD_SPK_R+
AUD_SPK_R-
AUD_SPK_L-
58
58
58
+AVDD
R2903 0R0603-PAD
AUD_SPK_L+ 1 2
+PVDD AUD_SPK_L+ 58 R2902 0R0603-PAD
AMP_MUTE# 1 2
27 AMP_MUTE# +AVDD

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC10U6D3V5MX-3GP
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
C2905

C2906

C2908

C2909

C2910
2

1
AUD_VREG
R2904 0R0603-PAD
1 2

2
Close to codec AUD_AGND

AUD_DVDDCORE

41
40
39
38
37
36
35
34
33
32
31
D D
U2901 AUD_AGND

1
AUD_AGND

PORTD_-L
PORTD_+L

AVDD2
THERMAL_PAD
EAPD
PVDD
PORTD_+R
PORTD_-R

PVDD
PVSS

VREG/+2_5V
C2901
SC10U6D3V5MX-3GP

2
PUMP_CAPP
0625 Modify:

2
AUD_DMIC_CLK&AUD_DMIC_IN0 connector CLOSE TO CODEC
to LVDS pin define. C2914
1 30 SC2D2U10V3KX-1GP

1
DVDD_LV CAP+ PUMP_CAPN
2 DMIC_CLK/GPIO_1 CAP- 29
3D3V_S0 3 28 AUD_V_B
HDA_CODEC_SDOUT DMIC_0/GPIO_2 V-
18 HDA_CODEC_SDOUT 4 SDATA_OUT AVSS2 27
HDA_CODEC_BITCLK 5 26 AUD_HP1_JACK_R R2906 1 2 60D4R2F-GP
18 HDA_CODEC_BITCLK BITCLK PORTB_R AUD_HP1_JACK_R2 82
Close to codec 18 HDA_SDIN0 1R2901 2HDA_CODEC_SDIN0 6 SDATA_IN PORTB_L 25 AUD_HP1_JACK_L R2905 1 2 60D4R2F-GP AUD_HP1_JACK_L2 82
33R2J-2-GP 7 24 AUD_AGND
HDA_CODEC_SYNC DVDD AVSS2 AUD_EXT_MIC_R C2922
18 HDA_CODEC_SYNC 8 SYNC 71.92H87.A03 PORTA_R 23 2 1 SC1U10V3KX-3GP MIC_IN_R 82
HDA_CODEC_RST# 9 22 AUD_EXT_MIC_L C2921 2 1 SC1U10V3KX-3GP
SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

18 HDA_CODEC_RST# RESET# PORTA_L MIC_IN_L 82

1

2
C2903

C2904

C2902

AUD_PC_BEEP 10 21 +AVDD
PCBEEP AVDD1

VREFOUT_C
VREFOUT_A
Put C2921 and C2922 close to codec
2

PORTC_R
VREFFILT
PORTF_R
SENSE_A
SENSE_B

PORTC_L
PORTF_L
0707 Modify:
updated U2901 part number from data base.

CAP2
0707 Modify:
Change R2911,R2914,R2917 change AUD_CAP2
to 0ohm 0603 from short pad.
92HD87B1A5NDGXTBX8-GP AUD_VREFFLT

11
12
13
14
15
16
17
18
19
20
2010/06/30 Change to 92HD87 (71.92H87.A03) R2911 0R0603-PAD
0809 Vendor recommand 1 2 AUD_V_B
C C
AUD_VREG

AUD_VREFOUT_B

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP
SC4D7U6D3V3KX-GP
AUD_SENSE_A
AUD_SENSE_B

AUD_PC_BEEP

AUD_VREFFLT

SC1U6D3V2KX-GP
R2920 R2914 0R0603-PAD

C2917

C2918

C2915

C2916
INT_MIC_L_R

AUD_CAP2
1 2 1 2

1
3D3V_S0
2K2R2J-2-GP

2
1

R2917 0R0603-PAD
R2908 AUD_VREFOUT_B 1 2
10KR2J-3-GP
AUD_AGND AUD_AGND AUD_AGND AUD_AGND
0730 Add internal MIC SC1U10V3KX-3GP
2

C2924
AMP_MUTE# 2 1
Close to codec
INT_MIC_L_R 58,82
AUD_AGND

AUD_VREFOUT_B

HDA_CODEC_BITCLK
120KR2J-L-GP
R2909
From SB MIC IN
AUD_PC_BEEP C2912 2 1 SCD1U10V2KX-5GP SB_SPKR_R 1 2 HDA_SPKR 18
C2913 2 1 SCD1U10V2KX-5GP KBC_BEEP_R 1 2 0719 Modify:
AUD_PC_BEEP KBC_BEEP 27
1

R2910 470KR2J-2-GP Move RN2901 to closed AUDIO CODEC from speaker connector.
C2923
SC1U10V2KX-1GP DY C2907
SC4D7P50V2CN-1GP
Trace width>15 mils From EC
2

B AUD_VREFOUT_B B

2
1
RN2901
SRN4K7J-8-GP

3
4
Azalia I/F EMI
HDA_CODEC_SDOUT 82 MIC_IN_R
82 MIC_IN_L
1

R2912
47R2J-2-GP
DY +AVDD +AVDD
R2913
2

1 2 AUD_HP1_JD# 82
1

1
PCH_AZ_CODEC_SDOUT1

R2915 20KR2F-L-GP R2916

2K49R2F-GP 2K49R2F-GP
2

A AUD_SENSE_A AUD_SENSE_B <Core Design> A

1
1

R2918
C2919 20KR2F-L-GP Wistron Corporation
SC1000P50V3JN-GP-U R2919 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2

2 1 Taipei Hsien 221, Taiwan, R.O.C.

2

EXT_MIC_JD# 82
1

C2920 AUD_AGND 39K2R2F-L-GP Title

DY SCD1U10V2KX-5GP AUD_AGND Audio Codec 92HD87B1
2

Close to Pin13 Size Document Number Rev

Close to Pin14 A3 A00
Enrico 14 AMD
Date: Friday, April 22, 2011 Sheet 29 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

AMP
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 30 of 109
5 4 3 2 1
 A B C D E

X01 3D3V_S0

SSID = LOM

1
EVDD10
LAN CHIP 3D3V_LAN_S5

DY
R3102
10KR2J-3-GP

R3117

1CLK_LAN_REQ#_EN 2
0R0603-PAD

1
1 2
R3101
C3106
10KR2J-3-GP

1
11/18 change L3101 to slime type Q3101
4
60 mils X01 SC1U10V3ZY-6GP DY PMBS3904-1-GP 4

2
2
DVDD10 84.03904.L06
L3101 R3115 2ND = 84.03904.P11
0R0603-PAD
LANOUP_1.05S 1 2CTRL10A_R 1 2 DVDD10
C3115 DY
IND-4D7UH-192-GP
1

1
SC4D7U6D3V3KX-GP
C3120 C3113 C3109 C3114 C3117
CLK_LAN_REQ#_R 2 3 PCIE_CLK_LAN_RQ1# 18
0721

3D3V_LAN_S5
3D3V_LAN_S5

3D3V_LAN_S5

3D3V_LAN_S5
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
R3133
2

LANXOUT
1
DY2

DVDD10

DVDD10
LANXIN
X5R 0R2J-2-GP

GPO
R3113
2K49R2F-GP
1 2 For Switch Regulator enable
3D3V_LAN_S5

2
48
47
46
45
44
43
42
41
40
39
38
37
U3101 R3105
49 0R0402-PAD
40 mils

AVDD33
AVDD33

AVDD10
CKXTAL2
CKXTAL1
AVDD33
NC#41
LED0
DVDD3
GPO
LED1/EESK
RSET
3D3V_LAN_S5 GND
R3106

1
0R2J-2-GP
1 2
1 36 LANOUP_1.05S DY
59 LAN_MDI0P MDIP0 REGOUT
1

C3118 C3121 C3119 2 35 AVDD33_REG

3 59 LAN_MDI0N DVDD10 MDIN0 VDDREG AVDD33_REG 3
3 AVDD10 VDDREG 34
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

4 33 ENSW REG
2

59 LAN_MDI1P MDIP1 ENSWREG EEDI/SDA

59 LAN_MDI1N 5 MDIN1 EEDI 32
DVDD10 6 31
NC#6 LED3/EEDO R3107 1
7 NC#7 EECS 30 2 10KR2J-3-GP
AVDD33_REG 8 29 DVDD10
DVDD10 NC#8 DVDD10 3D3V_S0
9 NC#9 LANWAKE# 28 PCIE_W AKE# 18,27
10 27 3D3V_LAN_S5
NC#10 DVDD33 ISOLATE#
11 NC#11 ISOLATE# 26 2 1
3D3V_LAN_S5 12 25 PLT_RST#_LAN R3110
R3104 0R0603-PAD NC#12 PERST#

1
1 2 1KR2J-1-GP
R3109

REFCLK_N
X02

REFCLK_P
C3101 C3111

CLKREQ#
1

DVDD10

EVDD10
SC4D7U6D3V3KX-GP

15KR2F-GP

NC#14
NC#15

HSON
HSOP
SCD1U16V2ZY-2GP

HSIN
HSIP

GND

2
2

X5R RTL8105E-VC-GRT-GP

13
14
15
16
17
18
19
20
21
22
23
24
1 DVDD10
TPAD14-GP TP3101

X01
0720 CLK_LAN_REQ#_R
PCIE_TXP0
PCIE_TXN0
CLK_PCIE_LAN 3D3V_LAN_S5
CLK_PCIE_LAN#
2 PCIE_W AKE# 10KR2J-3-GP2 2
DY 1 R3122
EVDD10

PCIE_RXP0_C

2
3D3V_S0 3D3V_LAN_S5 PCIE_RXN0_C X01
R3119
DY
SCD1U10V2KX-4GP
1 2 C3131 X02
1
0R3J-0-U-GP
LANXOUT C3102 1 2 SC18P50V2JN-1-GP

3
R3120
X3101
1 2
DY XTAL-25MHZ-155-GP
0R3J-0-U-GP
3D3V_S5 PA102FMG-GP-U
LANXIN C3103 1 2 SC18P50V2JN-1-GP

2
Q3103 main: 84.00102.031 X02
2nd: 84.03403.031
S D 3D3V_LAN_S5
1

C3105 SCD1U10V2KX-5GP
1

R3121 X02
1

PCIE_RXP0_C 1 2 PCIE_RXP0 17
C3130 10KR2J-3-GP C3125 C3129 C3128
PCIE_RXN0_C 1
G

2
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP PCIE_RXN0 17
SC1U10V2KX-1GP C3104 SCD1U10V2KX-5GP
2

1
2

PCIE_TXP0
2

PCIE_TXP0 17
PCIE_TXN0
2

1
2

1 R3118 2PM_LAN_ENABLE_R PCIE_TXN0 17

2

RN3101
X01
LAN_ENABLE_R_C

1KR2J-1-GP SRN10KJ-5-GP CLK_PCIE_LAN 17

RTL8111E-Stuff CLK_PCIE_LAN# 17
1
3D3V_LAN_S5 RTL8105E-DY <Core Design> 1
4
3

Q3102
27 PM_LAN_ENABLE G Q3104
R3103 1 DY 2 1KR2J-1-GP GPO Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
1

PMBS3904-1-GP
2

X02 D Taipei Hsien 221, Taiwan, R.O.C.

R3134 R3114
17,65,71,83 PLT_RST# 2 3 PLT_RST#_LAN Title
100KR2J-1-GP S 1 2 EEDI/SDA

2N7002K-2-GP 2 1 10KR2J-3-GP LOM

1

R3108 DY 0R2J-2-GP Size Document Number Rev

A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 31 of 109
A B C D E
 5 4 3 2 1

SSID = SDIO

XD_D7 1 TP3204 TPAD14-GP

D D
XD_D6/MS_BS XD_D6/MS_BS 74
XD_D5/SD_D2/MS_D5 XD_D5/SD_D2/MS_D5 74
17 CLK_PCH_48M
XD_D4/SD_D3/MS_D1 XD_D4/SD_D3/MS_D1 74
XD_D3/SD_D4/MS_D4 1 TP3205 TPAD14-GP
0809 Vendor recommand
C3209
1 2 RREF

SC100P50V2JN-3GP

R3201

24
23
22
21
20
19
1 2 U3201
6K2R2F-GP

XD_D7
SP14
SP13
SP12
SP11
CLK_IN
3D3V_S0 1 18 XD_D2/SD_CMD
RREF SP10 XD_D2/SD_CMD 74
USB_PN9_R 2 17 CR_GPIO0 1 TP3201 TPAD14-GP
USB_PP9_R DM GPIO0 XD_D1/SD_D5/MS_D0
43mA 3 DP SP9 16 XD_D1/SD_D5/MS_D0 74
4 15 XD_D0/SD_CLK/MS_D2 XD_D0/SD_CLK/MS_D2 74
3V3_IN SP8 XD_W P/SD_D6/MS_D6 1 TP3206 TPAD14-GP
0809 Vendor recommand 3D3V_CARD_S0 5 CARD_3V3 SP7 14
V18 6 13 XD_W E#/SD_CD#
SCD1U10V2KX-5GP

V18 SP6 XD_W E#/SD_CD# 74

1

XD_CD#
C3204

C3203

250mA
SC4D7U6D3V3KX-GP

SP1
SP2
SP3
SP4
SP5
25
2

GND

SC1U6D3V2KX-GP
C3208
RTS5138-GR-GP

7
8
9
10
11
12
1
C C

71.05138.003

2
Close to chip
XD_ALE/SD_D7/MS_D3 XD_ALE/SD_D7/MS_D3 74
3D3V_CARD_S0 XD_CLE/SD_D0/MS_D7 XD_CLE/SD_D0/MS_D7 74
XD_CE#/SD_D1 XD_CE#/SD_D1 74
XD_RE#/MS_INS# XD_RE#/MS_INS# 74
R3208
XD_RDY/SD_W P/MS_CLK_R 2 1 XD_RDY/SD_W P/MS_CLK 74
1

C3207
22R2J-2-GP
C3206 SC4D7U6D3V3KX-GP XD_CD# 1 TP3203 TPAD14-GP
SCD1U10V2KX-4GP
2

0809 Vendor recommand

B B

A00
USB_PN9_R R3206 1 2 0R0603-PAD USB_PN9 18

USB_PP9_R R3207 1 2 0R0603-PAD USB_PP9 18

X01 EMI 12/13

CLK_PCH_48M
SC10P50V2JN-4GP
EC3201
1

DY
2

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 32 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 33 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 34 of 109
5 4 3 2 1
 A B C D E

4 4

3 3

(Blanking)

2 2

1 <Core Design> 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 35 of 109
A B C D E
 5 4 3 2 1

0816

D ROSA Run Power Power Sequence 3D3V_S5

D

10KR2J-3-GP
R3627
2
X01 R3674
46 1V_S0_PWRGD 1 DY 2
0R2J-2-GP

D3605
47 1D8V_S0_PWRGD 1 R3629 2 0R0402-PAD 2

3VCORE_EN_R 1 R3628 2 0R0402-PAD VCORE_EN 42

15V_S5
1 R3634 2 0R0402-PAD 1

1
18,27,44,46,47 PM_SLP_S3#
DY C3633
AO4468 MAX 11.6A +5V_RUN BAW56-5-GP SCD015U25V2KX-GP
83.00056.Q11

2
1
Rds(on) = 11~14mOhm
X01 VGS=+/-20V +5V_RUN Comsumption 2ND = 83.00056.G11
R3604 5V_S5 5V_S0
Peak current 7.73A 3RD = 83.00056.K11
33KR2F-GP
2nd = 84.08882.037
84.04468.037
2

AO4468-GP 0816
5 D G 4
6 D S 3 3D3V_S5
7 D S 2
8 D S 1
X01

1
U3601

1
2 R3605 1 5V_RUN_ENABLE R3624
3D3V_AUX_S5 0R0402-PAD C3603 10KR2J-3-GP
1 C3608 SC10U10V5ZY-1GP

2
DYSC6800P25V2KX-1GP

2
2

C 1 R3606 2 PS_S3CNTRL C
100KR2J-1-GP
D G S AO4468 MAX 11.6A
Rds(on) = 11~14mOhm +3.3V_RUN
6

Q3602 3D3V_S5 VGS=+/-20V 3D3V_S0 +3.3V_RUN Comsumption

2N7002KDW-GP
2nd = 84.08882.037 Peak current 8.14A
84.2N702.A3F 84.04468.037 D3603
1

2nd = 84.DM601.03F AO4468-GP 2

18,27,44,46,47 PM_SLP_S3#
S G D 5 D G 4
6 D S 3 X01 3
7 2
X01 8
D S
1 1 R3626 2 0R0402-PAD
1
D S 42 VRM_VDD_PWRGD
18,27,44,46,47 PM_SLP_S3# U3602
R3607 BAW56-5-GP
RUN_ENABLE 1 23.3V_RUN_ENABLE 83.00056.Q11

1
10KR2J-3-GP X01 C3604 2ND = 83.00056.G11
1

SC10U6D3V5KX-1GP 3RD = 83.00056.K11 1 R3673 2 0R0402-PAD IMVP_PWRGD 27

2
C3605
SCD015U25V2KX-GP D3604
2

27,46 1D1V_S5_PWRGD 2

3 RUNPWROK_D 1 R3625 2 0R0402-PAD FCH_PWRGD 18

44 1D5V_S3_PWRGD 1

BAW56-5-GP
1D1V_S5 1D1V_S0 83.00056.Q11
1.5V_RUN for VGA Comsumption 2ND = 83.00056.G11
Peak current 7.39A 3RD = 83.00056.K11
U3611
8 D S 1
+1.5V_RUN_CPU Comsumption 7 D S 2
6 D S 3
Peak current 3A 5 D G 4
X01
+1.5V_RUN for Mini-Card Comsumption R3633 AO4468-GP
1

B 1 21.1V_RUN_ENABLE 84.04468.037 B
Peak current 1A C3614
33KR2F-GP 2nd = 84.08882.037 SC10U6D3V5KX-1GP
2
1

C3615
SCD033U25V2KX-GP
2

H_THERMTRIP# 6,18
X01

2
+1.5V_RUN 6,17,42,71 H_CPUPWRGD 1 DY R3601
2
1KR2J-1-GP
H_PWRGD_R 1
PMBS3904-1-GP
DYQ3601
X01 Total= 500mA

SCD1U10V2KX-5GP

3
1D5V_S3 1D5V_S0
X01

1
U3606

C3602
AO3404A-GP 17,27 A_RST# 1
R3622
2
DY1KR2J-1-GP DY

2
D S

84.03404.B31 BAS16-6-GP
G

2nd = 84.03400.B37 X01 2

1 R3630 21.5V_RUN_ENABLE
1

10KR2J-3-GP AO4468 MAX 11.6A 3 PURE_HW_SHUTDOWN# 27,28,85

X01 Rds(on) = 28~42mOhm DY C3609
1

SC10U6D3V5KX-1GP 1 83.00016.K11
2

C3610 DY VGS=+/-20V 41 3V_5V_EN

2ND = 83.00016.F11
SCD01U50V2KX-1GP D3601
2

1
1 R3603 2 S5_ENABLE 27

DY R3602
200KR2J-L1-GP
1KR2J-1-GP

2
DIS uses 84.08039.037 TPCA8039-H Peak current=34A
UMA uses 84.07686.037 SI7686DP Peak current=35A
X01
A A

1D1V_S0 1V_PWR

R3671 1 2 0R0805-PAD

R3666 1 2 0R0805-PAD <Core Design>

R3667 1 2 0R0805-PAD

R3668 1 2 0R0805-PAD
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
R3669 1 Taipei Hsien 221, Taiwan, R.O.C.
2 0R0805-PAD
Title
R3670 1 2 0R0805-PAD
Power On Logic
Size Document Number Rev
A2
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 36 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

<Core Design>

A Wistron Corporation A
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

Power Plane Enable Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 37 of 109
 5 4 3 2 1

SSID = PWR.Support

DCin CONN
D
5V_S5
0721 Remove PSID schematic D

2
PR3802

1
15KR2J-1-GP
PR3803 3D3V_S5 3D3V_S5

2
10KR2J-3-GP

1
1 PMBS3904-1-GP
PQ3802

2
2
BAV99-8-GP

1
PR3811 PSID_DISABLE#_R_C 2 1
100KR2J-1-GP PR3806
PD3803 2K2R2J-2-GP

3
G
1
PQ3801

2
FDV301N-NL-GP
PR3801 PR3807
PS_ID_R 1 2 PS_ID_R2 D S PS_ID 1 2

D
PSID_EC 27
0R0603-PAD
33R2J-2-GP
PQ3803

1
G

. .
27 RCID
PD3804 PR3808

2
DY B240A-13-GP 1 DY 2 PR3812 D

.
.
.
C 100KR2J-1-GP C
33R2J-2-GP
DY S
DY

1
2N7002E-1-GP

84.2N702.D31

This cap should be used

+DC_IN AD+
only as last resort for
EMI suppression.
X01
PU3801
1 S D 8
DCIN1 S D

SC1U25V5KX-1GP

SC10U25V5KX-GP
SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

SCD01U50V2KX-1GP
2 7

1
PC3801
S D

240KR3-GP
3 6 X01

PC3806
1

1
1 8

PC3805

PC3803

PC3804
G D

PR3809
4 5
K

DY DY

1
2 9 PD3801 SI4835DDY-T1-GE3-GP

2
3 10 PC3802
P6SBMJ27APT-GP DY

2
4 11 SCD1U50V3KX-GP Id= -10A

2
5 12
Qg= -22nC
A

6 13
7 14 Rdson=14~13mohm
1128-SB
B ACES-CONN14G-GP B

2
PR3810
PQ3805R2 47KR3J-L-GP
PQ3804 E
AD_OFF_L
C B
DY

1
R1
B R1 C AD_OFF_R
40 PW R_CHG_AD_OFF DY
20.F1498.007 R2
E
PDTA124EU-1-GP
PDTC124EU-1-GP

AFTP3812 1 PS_ID_R
AFTP3813 1 +DC_IN
AFTP3814 1 GND

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DCIN_JACK
Size Document Number Rev
Custom
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 38 of 109

5 4 3 2 1
 5 4 3 2 1

SSID = BATT CONN

D D

Batt Connecter X01

27 BAT_IN#
BATT1
X01 10
1
AFTP3901
2
1 BAT_ALERT 3
BT+ 4
R3904 1 2 100R2J-2-GP PBAT_PRES1# 5
6
7
8

K
9

1
PD3902 11
C3902 C3901
SCD1U50V3KX-GP SC2200P50V2KX-2GP DY SMF18AT1G-GP ALP-CON9-4-GP

A
1128-SB 20.81507.009
1 AFTP3906

C C

R3903 1 2 100R2J-2-GP PBAT_SMBDAT1

27,40 BAT_SDA

R3902 1 2 100R2J-2-GP PBAT_SMBCLK1

27,40 BAT_SCL

1
EC3902 DY DY EC3901
SC10P50V2JN-4GP SC10P50V2JN-4GP

2
1 PBAT_PRES1#
AFTP3902
1 PBAT_SMBDAT1
AFTP3903
1 PBAT_SMBCLK1
AFTP3904
1 BT+
AFTP3905

B B
Close to Batt Connector
For actual location, need to be swap all pin
BAT_IN#

BAT_SDA

BAT_SCL

D3901
3

D3902 D3903
3

1 2
1 2 1 2
BAV99-8-GP
BAV99-8-GP BAV99-8-GP

83.BAV99.D11
83.BAV99.D11 83.BAV99.D11 3D3V_AUX_KBC
2nd = 83.00099.K11 2nd = 83.00099.K11 2nd = 83.00099.K11
3rd = 83.00099.T11 3rd = 83.00099.T11 3rd = 83.00099.T11
A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

BATT CONN
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 39 of 109
5 4 3 2 1
 5 4 3 2 1

SSID = Charger

D D

AD+_TO_SYS DCBATOUT BT+

PU4003
PU4002 1 S D 8
D S S D
EE need pull high and net name AD+ 8
7 D S
1
2 1 2
2
3 S D
7
6

1
6 D S 3 PR4002 AD+ 4 G D 5

100KR2J-1-GP
PR4003
5 D G 4 D01R2512F-4-GP

GAP-CLOSE-PWR-3-GP
SI4835DDY-T1-GE3-GP
0802 Rename H_PROCHOT# SI4835DDY-T1-GE3-GP

2
10KR2J-3-GP
3D3V_AUX_S5

2
Id= -10A

1
PWR_CHG_REGN

PR4004
AD+_G_2
Id= -10A

PG4002

PG4004

PG4005

PG4001

PG4006
GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP
PG4003 PR4005 Qg= -22nC

10KR2F-2-GP
Qg= -22nC GAP-CLOSE-PWR-3-GP 470KR2J-2-GP
Rdson=14~13mohm
1

PR4001
PR4006
Rdson=14~13mohm

1
PR4030 PR4034 0R2J-2-GP

2
6,27 H_PROCHOT#
DY100KR2J-1-GP

DC_IN_D
100KR2J-1-GP 2
DY 1

1
D

PQ4002
2

AD+_G_1
PQ4005 1 2
2N7002A-7-GP 3 4

SC1U25V3KX-1-GP
PC4002
DY G PWR_CHG_CMPOUT PWR_CHG_ACOK 2 5 SCD1U25V2KX-GP
X01

SCD1U50V3KX-GP
1

PWR_DCBATOUT_CHG

PC4003
1 6

1
PC4004
S

SC2200P50V2KX-2GP
PR4032 DY AD+
2N7002KDW-GP
DY

SCD1U50V3KX-GP

SCD1U25V2ZY-1GP
2

PWR_CHG_ACN
PWR_CHG_ACP

SC10U25V5KX-GP

SC10U25V5KX-GP
84.2N702.A3F

SCD1U50V3KX-GP
120KR2F-L-GP

1
2

X01

PC4024

PC4009

EC4001

EC4002
2nd = 84.DM601.03F

PC4008

PC4006
X01

1
PWR_CHG_REGN

SCD47U25V3KX-2GP
PR4008

2
CHG_AGND CHG_AGND DY DY
1

PWR_CHG_CMPIN 2010/11/10 PR4007

X01 20R5J-GP PD4001

2
5
6
7
8

SI4178DY-T1-GE3-GP
C PWR_CHG_VCC PR4009 SD103AWS-1-GP C
1 2

D
D
D
D
316KR2F-GP CHG_AGND 0R3J-0-U-GP
1

PC4010
1 2 K A 1 2

SCD047U25V2KX-GP

PU4004
PR4029 1 2 PC4007
2

1
30K9R2F-GP PR4010 20R5J-GP PU4005 SC1U25V3KX-1-GP
DY

PC4011

G
4

ACP

ACN
2

S
S
S
PWR_CHG_IOUT CHG_AGND 20
2

VCC
1

3
2
1
2010/11/10 X01 PR4011

2
SCD01U50V2KX-1GP
49K9R2F-L-GP PR4031

19K1R2F-GP PWR_CHG_ACDET 6 17 PWR_CHG_BTST

PQ4004 ACDET BTST
1

Charger Current=1.4~3.6A
D

2010/11/10 X01
1

2N7002A-7-GP
PC4012

PWR_CHG_CMPOUT 16
REGN
2

DY
1

1
G PR4014 3
AD_IA_HW 27
2

PR4013 CMPOUT PWR_CHG_HIDRV PL4001

18
100KR2F-L1-GP 3D3MR2J-GP HIDRV IND-5D6UH-52-GP BT+
1
4 DY2 X01
S

CMPIN

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP
please help to check 19 PWR_CHG_PHASE 1 2BT+_R 1 2

SC10U25V5KX-GP
GAP-CLOSE-PWR-3-GP
PC4013
2

2
PHASE

GAP-CLOSE-PWR-3-GP
CHG_AGND PWR_CHG_CMPIN SC3300P50V3KX-1GP PR4016
which net connect it DELETE PR4015 X01

SCD1U50V3KX-GP
D01R2512F-4-GP

PC4019
PWR_CHG_BAT_SCL 9 PWR_CHG_LODRV

2
27,39 BAT_SCL 2 1 SCL LODRV
15

PC4016

PC4017

PC4018
CHG_AGND PG4007 GAP-CLOSE-PWR-3-GP

PG4010

PC4015
1

1
PG4009
SCD1U25V2KX-GP

1
CHG_AGND 2010/11/10 X01

5
6
7
8

SI4178DY-T1-GE3-GP
27,39 BAT_SDA 2 1 PWR_CHG_BAT_SDA 8
SDA DELETE PC4014 X01 DY DY

D
D
D
D
3D3V_AUX_S5 PG4008 GAP-CLOSE-PWR-3-GP

1
1

2
PC4020
PWR_CHG_CMPIN

2
PU4001
13 PWR_CHG_SRP 1 2
SRP
1

PWR_CHG_ILIM 10 PR4021 10R2F-L-GP

ILIM

1
1

PR4017 PWR_CHG_SRN

G
12 1 2 4
SRN

S
S
S
DY
PR4028
15KR2F-GP
100KR2J-1-GP
2 1 PWR_CHG_IFAULT
11 IFAULT#
PR4020 7D5R2F-GP DY 2010/11/10 X01
DY 2010/11/10 X01

3
2
1
38 PWR_CHG_AD_OFF
2

PR4018 CHG_AGND
2

B 0R2J-2-GP B
1

10KR2F-2-GP

3D3V_AUX_S5 PR4022 2010/11/10 X01

SCD1U25V2KX-GP
PR4023 5 7 PWR_CHG_IOUT 1 2
PR4035

PQ4006 ACOK# IOUT AD_IA 27

59KR2F-GP

GND

GND
DY
D

2N7002A-7-GP 0R0402-PAD

SC220P50V2JN-3GP
PWR_CHG_REGN PWR_CHG_CSOP_1
1

PC4021
2

8K45R2F-2-GP
DY DYPR4026 BQ24707ARGRR-GP

1 PR4024
21

14
PQ4001 100KR2J-1-GP
G
D

AD_IA_HW2 27

1
2N7002A-7-GP

PC4022
CHG_AGND PG4011
2

1 2
DY
S

2
G PWR_CHG_CMPOUT CHG_AGND

SCD1U25V2KX-GP
GAP-CLOSE-PWR

CHG_AGND DY
S

PC4023
2
X01

1
CHG_AGND 3D3V_AUX_S5

2
CHG_AGND
2010/11/10 X01 CHG_AGND PWR_CHG_REGN
2010/11/10 X01 CHG_AGND
1

ROSA
1

3D3V_AUX_S5 PWR_CHG_REGN PR4062

100KR2J-1-GP PR4027
Adapter Type PR4023 100KR2J-1-GP
DY
1

PR4061 PR4025
2

100KR2J-1-GP
65W 24K DY100KR2J-1-GP
27 PWR_CHG_ACOK
2

90W 33.2K
DY
D

27 AC_IN# PR4036
120KR2F-L-GP
AD+ . PQ4003
A 130W 59K PQ4007 A
2N7002E-1-GP
SCD1U25V3KX-GP
D

2N7002A-7-GP
2

.
EC code only BQ24707
PC4001

. <Core Design>
1

. .
1

PR4012 PR4033
DY DY DY120KR2F-L-GP
1 2 G
Wistron Corporation
S

DY
316KR2F-GP
2

H_PROCHOT# AD_IA_HW AD_IA_HW2

1

PR4037 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

2
49K9R2F-L-GP

Taipei Hsien 221, Taiwan, R.O.C.

S

65W 0 0 AC_IN#
DY Title

CHARGER BQ24707
2

90W 1 0
Size Document Number Rev
1128-SB Custom
130W 0 1 Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 40 of 109
5 4 3 2 1
 A B C D E

SSID = PWR.Plane.Regulator_3p3v5v 3D3V_PWR_2

PWR_5V3D3V_VLK

1
3D3V_S5 3D3V_PWR PC4103 PC4104

SC1KP50V2KX-1GP
PC4102
PG4102 PR4102 SCD1U25V3KX-GP SCD1U25V3KX-GP
GAP-CLOSE-PWR-3-GP DCBATOUT PWR_3D3V_DCBATOUT 100KR2J-1-GP

2
1 2 PG4103
GAP-CLOSE-PWR-3-GP

2
PG4105 1 2
GAP-CLOSE-PWR-3-GP PWR_3D3V5V_ENTRIP
1 2 PG4104
GAP-CLOSE-PWR-3-GP
PG4107 1 2

D
GAP-CLOSE-PWR-3-GP PQ4101 PWR_5V_ENTRIP1

3
1 2 PG4106 2N7002E-1-GP .

2
GAP-CLOSE-PWR-3-GP
PG4108 1 2 . PC4105 DY PR4103 PD4101 PD4102
4 GAP-CLOSE-PWR-3-GP .
. . SC18P50V2JN-1-GP 143KR2F-GP BAT54S-5-GP BAT54S-5-GP 4

4
1 2 PG4109
GAP-CLOSE-PWR-3-GP X02 15V_PWR

1
PG4110 1 2 PQ4102 15V_S5 5V_PWR
PR4104
GAP-CLOSE-PWR-3-GP 36 3V_5V_EN 1 2 ALW_ON_1 DMN66D0LDW-7-GP PG4112
1 2 2011/03/16 X02 GAP-CLOSE-PWR-3-GP

3
0R0402-PAD
PG4113 X02 1 2

1
GAP-CLOSE-PWR-3-GP
PWR_3D3V_ENTRIP2

K
1 2 PR4106

1
200KR2J-L1-GP PC4106 PC4107
PD4103

1
PG4115 SC1U25V3KX-1-GP SCD1U10V2KX-5GP

SC18P50V2JN-1-GP
BZT52C15S-GP

1
GAP-CLOSE-PWR-3-GP PR4107

2
1
169KR2F-1-GP

PC4108
1 2 PWR_3D3V_DCBATOUT DY

A
PC4101

2
PG4117 SCD1U25V3KX-GP

2
GAP-CLOSE-PWR-3-GP
1 2 2010/11/10 X01
PC4109 PC4110 TPS51125 RT8205B
1

1
SCD01U50V2KX-1GP

PG4129 X01 PR4108 DY ASM

SC10U25V5KX-GP

GAP-CLOSE-PWR-3-GP
1 2 D PWR_5V_DCBATOUT
2

PR4108 PWR_5V_DCBATOUT
PWR_3D3V_EN
1 1128-SB
PG4128 DY 2
PC4115
GAP-CLOSE-PWR-3-GP X01 PC4114

SCD01U50V2KX-1GP

SCD1U50V3KX-GP
820KR3J-GP 5V_PWR 5V_S5

1
1 2

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

PC4112
TPS51125 RT8205B PG4119
D
8
7
6
5

1
SC10U25V5KX-GP

PC4116

PC4117

PC4111
PR4110 0R3J 4R7 GAP-CLOSE-PWR-3-GP
DY
D
D
D
D
PU4102 DCBATOUT PWR_5V_DCBATOUT
DY 1 2

5
6
7
8
SIS412DN-T1-GE3-GP TPS51125 RT8205B

2
D
D
D
D
1116:84.00412.037 PR4109 0R3J 4R7 PU4103 PG4118
PG4111
SIS412DN-T1-GE3-GP Design Current =7.1A GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP

16
Design Current =8.32A 11.14A<OCP<13.17A 1 2
S
S
S
G

PU4101 1 2
13.07A<OCP<15.45A
1
2
3
4

S G PG4101

VIN

G
S
S
S
PC4113 PG4114 GAP-CLOSE-PWR-3-GP
SCD1U25V3KX-GP 0826 SCD1U25V3KX-GP 1116:84.00412.037 GAP-CLOSE-PWR-3-GP 1 2

4
3
2
1
PR4110
PR4109 PC4118 G S 1 2
2 1 PWR_3D3V_VBST2_1
1 2PWR_3D3V_VBST2 9 22 PWR_5V_VBST11 2 PWR_5V_VBST1_1 1 2 PG4122
VBST2 VBST1 0R3J-0-U-GP PG4116 GAP-CLOSE-PWR-3-GP
3D3V_PWR 2D2R3J-2-GP 5V_PWR
PWR_3D3V_DRH2 10 21 PWR_5V_DRVH1 GAP-CLOSE-PWR-3-GP 1 2
PL4102 DRVH2 DRVH1 PL4101
3 1128-SB 1 2 3
1 2 PWR_3D3V_LL2 11 20 PWR_5V_LL1 1 2 PG4123
SCD1U10V2KX-5GP

IND-2D2UH-46-GP-U LL2 LL1 IND-2D2UH-46-GP-U GAP-CLOSE-PWR-3-GP

1

PWR_3D3V_DRVL2 PWR_5V_DRVL1
PC4119

D 12 19 1 2
1

1
DRVL2 DRVL1
2010/11/10 X01 D
8
7
6
5

5
6
7
8
ST220U6D3VDM-15GP

GAP-CLOSE-PWR-3-GP
TPS51125ARGER-GP PG4124
DY DY PR4112

SCD1U10V2KX-4GP
D
D
D
D
PT4103

D
D
D
D

PWR_3D3V_VO2 PWR_5V_VO1

PC4120
PR4111 PU4104 7 24 PU4105 PT4101 GAP-CLOSE-PWR-3-GP
2

1
PG4121 2D2R5F-2-GP VO2 VO1 2D2R5F-2-GP PG4130
SI7716ADN-T1-GE3-GP SI7716ADN-T1-GE3-GP 1 2
DY
2
GAP-CLOSE-PWR-3-GP

ST220U6D3VDM-15GP
PWR_3D3V_FB2 5 2 PWR_5V_FB1

2
VFB2 VFB1 PG4125

2
1

1128-SB GAP-CLOSE-PWR-3-GP
2

2
1
G
S
S
S
2PWR_3D3V_EN 13 3V_5V_POK
S
S
S
G

1 23 1 2
PC4121 PR4101 DY
820KR2F-GP EN0 PGOOD
DY S G S DY PC4122
2

1
2
3
4

4
3
2
1
SC330P50V2KX-3GP PWR_3D3V_ENTRIP2 PWR_5V_ENTRIP1 SC560P50V-GP PG4126
G 6 1

2
51125_VREF ENTRIP2 ENTRIP1 GAP-CLOSE-PWR-3-GP
3 15 1 2
VREF GND
1
SCD22U10V2KX-1GP

PC4123

1116:84.07716.037 PWR_5V3V_TONSEL4 25 1116:84.07716.037

TONSEL GND

1
PR4115
2
1

PWR_5V3V_SKIPSEL
14 18 PWR_5V3D3V_VLK 0R2J-2-GP

1
PR4114 SKIPSEL VCLK
DY
PR4113 DY 0R2J-2-GP PR4116
VREG3

VREG5
6K65R2F-GP 33KR2F-GP

1 2
PWR_5V_FB1_R
2

1 2

51125_FB2_R

2
PC4125 PC4124 DY
3D3V_AUX_S5_5_51125 8

17

3D3V_PWR_2
DYSC18P50V2JN-1-GP 5V_AUX_S5 SC18P50V2JN-1-GP

2
3D3V_PWR_2
PG4127
2

1
1 2
1

PR4118 PR4119 PR4120

PR4117 2 GAP-CLOSE-PWR-3-GP 100KR2J-1-GP 21K5R2F-GP
10KR2F-2-GP
51125_VREF DY 1
0R2J-2-GP
Close to VFB Pin (pin2)

2
PR4121
3D3V_PWR_2 1 2 3V_5V_POK 46
2

0R0402-PAD
PR4122
51125_VREF 1 2
1

PC4127
PC4126

0R0402-PAD
Close to VFB Pin (pin5)
SC10U10V5KX-2GP
SC4D7U6D3V5KX-3GP

2 2 PR4123
1 2
3D3V_PWR_2 DY
2

0R2J-2-GP 3D3V_PWR_2 3D3V_AUX_S5

2 PR4124
1
DY 0R2J-2-GP 1
PR4125
2
0R0402-PAD

TPS51125 RT8205B
PR4118 DY ASM
PR4121 ASM DY

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L I/P cap: 10U 25V K0805 X5R/ 78.10622.51L
Inductor: 2.2uH PCMC063T-2R2MN Cyntec 18mohm/20mohm Isat =14Arms 68.2R210.20B Inductor: 2.2uH PCMC063T-2R2MN Cyntec 18mohm/20mohm Isat =14Arms 68.2R210.20B
O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L SKIPSEL VREG3 or VREG5 VREF(2V) GND O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L
O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081 H/S: TPC8061-H / 21mohm/30mOhm@4.5Vgs/ 84.08061.037
H/S: TPC8061-H / 21mohm/30mOhm@4.5Vgs/ 84.08061.037 Operating OOA Auto Skip Auto Skip L/S: TPCA8065-H / 12mohm/15mOhm@4.5Vgs/ 84.08065.037
Mode PWM only
L/S: TPCA8065-H / 12mohm/15mOhm@4.5Vgs/ 84.08065.037

EN0 Open 820kΩ to GND GND

Operating
Mode enable both enable both LDOs, disable all
TPS51125: LDOs, VCLK on VCLK off and circuit
and ready to ready to turn on
TONSEL CH1 CH2 turn on switcher channels
GND 200kHz 265kHz switcher
channels
VREF 245kHz 305kHz
VREG3 300kHz 375kHz

1
VREG5 365kHz 460kHz 1

RT8205B:

TONSEL CH1 CH2

<Core Design>
GND 200kHz 250kHz
VREF 300kHz 375kHz Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
VREG3 365kHz 460kHz Taipei Hsien 221, Taiwan, R.O.C.
VREG5 365kHz 460kHz Title

Size Document Number

TPS51125_5V/3D3V Rev
A2 Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 41 of 109
A B C D E
 5 4 3 2 10825
SSID = PWR.Plane.CORE.REG 1 2
PC4210 SC47P50V2JN-3GP

PC4214 SC180P50V2JN-1GP
1 2

PR4227
PC4218
1 26265_FB_NB_R 1 2

33KR2F-GP SC1KP50V2JN-2GP DCBATOUT

D PC4201
D
5V_S5 1 2
PR4209

1
1 2 SC1KP50V2JN-2GP
TC4207
DY SE100U25VM-10GP
2R3J-GP

2
1
1 PR4228 2 PR4220
PC4209 22KR2F-GP
SC1U10V3KX-4GP 1 2 APU_VDDNB

2
GNDA_VCORE
10R2J-2-GP
2010/11/10 X01
GNDA_VCORE APU_VDDNB_RUN_FB_H 6
DCBATOUT
PR4211
1 2 PHASE_NB 43
1 PR4222 2 8K2R2F-1-GP

6265_OCSET_NB
Pleae help to check 5V_S5 3D3V_S5 2R3J-GP LGATE_NB 43

1
the net whether can 0825
PC4202

6265_COMP_NB
PHASE_NB 43

6265_FSET_NB
change to 3D3V_S5 SCD1U25V3KX-GP

6265_FB_NB
2
1

1 UGATE_NB 43
DCBATOUT

6265_VCC
6265_VIN
PR4229 PR4202 1128-SB
DY 0R0402-PAD DY PR4212 GNDA_VCORE
10KR2F-2-GP 0R2J-2-GP APU_VDDNB_RUN_FB_L 6
PC4204 PC4203 PC4223 PC4206
2

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP
6265_OFS/VFIXEN PR4231

5
6
7
8

1
1 2

SCD1U25V3KX-GP
3D3V_S0 Peak Current=11
1

D
D
D
D
GNDA_VCORE 10R2J-2-GP PU4202

49
48
47
46
45
44
43
42
41
40
39
38
37
DY Design Current =7.7A
C X01 PU4201
C

SIR172DP-T1-GE3-GP

2
1

PR4224
DY 16.5A<OCP<18.7A

GND
VIN
VCC
FB_NB
COMP_NB
FSET_NB
VSEN_NB
RTN_NB
OCSET_NB
PGND_NB
LGATE_NB
PHASE_NB
UGATE_NB
0R2J-2-GP BOOT_NB 43
PR4214 DY
2

G
S
S
S
10KR2J-3-GP
2

4
3
2
1
GNDA_VCORE 1 36
OFS/VFIXEN BOOT_NB BOOT0 PL4201 APU_VDD
36 VRM_VDD_PW RGD 2 PGOOD BOOT0 35
6,17,36,71 H_CPUPW RGD 3 34 UGATE0 UGATE0 1128-SB
PR4203 PWROK UGATE0
6 APU_SVD_R 2 1 0R0402-PAD6265_SVD 4 SVD PHASE0 33 PHASE0 PHASE0 1 2

1
PR4210
2 1 0R0402-PAD6265_SVC 5 32 5V_S5 PR4233
6 APU_SVC_R SVC PGND0

PT4203
SE330U2VDM-L-GP

PT4208
ST330U2VDM-4-GP

PT4204
SE330U2VDM-L-GP

PT4206
SE330U2VDM-L-GP
PR4205
2 1 0R0402-PAD6265_ENABLE 6 31 LGATE0 BOOT0 1 2 BOOT0_R 1 2 COIL-1UH-34-GP-U
36 VCORE_EN ENABLE LGATE0
1 2 6265_RBIAS 7 30 0R3J-0-U-GP PC4220 PR4230 PR4221
RBIAS PVCC DY 2D2R5F-2-GP

5
6
7
8
1 2 PR4216 16K9R2F-GP 6265_OCSET 8 29 6K49R2F-1-GP PG4216

SIR460DP-T1-GE3-GP
OCSET LGATE1

1
D
D
D
D
PR4223 100KR2F-L1-GP 6265_VDIFF0 9 28 PC4207 PU4203

2
6265_FB0 VDIFF0 PGND1 SC2D2U10V3KX-1GP SCD22U10V3KX-2GP GAP-CLOSE-PW R-3-GP
10 27

2
FB0 PHASE1
6265_COMP0 11 26 DY DY

2
COMP0 UGATE1

1
GNDA_VCORE 6265_VW 0 12 25

2
VW0 BOOT1 PC4225
DY SC560P50V-GP PR4213

S
S
S
G
COMP1
VDIFF1
VSEN0

VSEN1

2
RTN0
RTN1

PG4217 1 2
ISN0

ISN1
ISP0

ISP1
VW1

4
3
2
1
FB1

1 2 1K4R2F-1-GP 2010/11/10 X01

1 2
GAP-CLOSE-PW R-3-GP ISL6265CHRTZ-T-GP PC4216 SCD1U25V2KX-GP
13
14
15
16
17
18
19
20
21
22
23
24

GNDA_VCORE
ISP0 PR4218 PR4208 PR4208 close
ISN0 ISN0 1 DY 2 1 DY 2
10R2F-L-GP NTC-10K-9-GP to PL4201
1D8V_S0 ISP0
B B

ISP0
APU_VDD ISP0_R
2

LGATE0 ISN0
PR4201
1

Close to 0R0402-PAD
PR4206
10R2J-2-GP CPU socket
1

Parts
close to
2

6 APU_VDD_RUN_FB_H
6 APU_VDD_RUN_FB_L PWM IC
I/P cap: 10U 25V K0805 X5R/ 78.10622.51L
1

PR4219 Inductor: 1uH PCMC063T-1R0MN Cyntec 9mohm/10mohm Isat =22Arms 68.1R01A.20B

10R2J-2-GP Parallel O/P cap: 330U 2V EEFSX0D331ER 9mOhm 3Arms Panasonic/79.33719.L01
6265_FB0_C PC4222SC180P50V2JN-1GP
O/P cap: 330U 2V EEFSX0D331XE 6mOhm 3,5Arms Panasonic/79.33719.20L
Close to
2

PC4212 1 2 DY H/S: SIR712DP/ POWERPAK/10.3mOhm/12.4mOhm@4.5Vgs/ 84.00172.037

PR4207 PC4224 CPU socket L/S: SiR460DP/ POWERPAK/ 4.9mOhm/ 6.1mohm@4.5Vgs/ 84.00460.037
1 2 1 2 1 2 1 2
249R2F-GP PC4208
SC2200P50V2KX-2GP SC220P50V2JN-3GP
SC1KP50V2JN-2GP

1KR2F-3-GP PR4225 PC4217 PR4226

1 PR4217 2 1 2 1 2 1 2
54K9R2F-L-GP 6K81R2F-1-GP
2PR4204 1
DY
SC180P50V2JN-1GP
A 3D3V_S5 DY
910KR2J-GP
<Core Design>
A
6265_FB0_R 1 2
2PR4215
DY 1
0R2J-2-GP PC4221 SC1KP50V2JN-2GP Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
1 2
DY Title
SC33P50V2JN-3GP
EC4270
VREG : +VCC_CORE&+VDDNB
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 42 of 109
 5 4 3 2 1

SSID = PWR.Plane.VDDNB.REG

D D

DCBATOUT 1128-SB

Peak Current=10

1
PC4304 PC4302 PC4301 PC4303
Design Current =7A

SCD1U25V3KX-GP
DY

5
6
7
8

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP
15A<OCP<17A

2
D
D
D
D
PU4302

SIR172DP-T1-GE3-GP
G
S
S
S
4
3
2
1
PL4301 APU_VDDNB
C C
42 UGATE_NB
42 PHASE_NB 1 2

COIL-1UH-34-GP-U

1
PT4301 PT4302 PT4304

5
6
7
8

1
SIR460DP-T1-GE3-GP
2

D
D
D
D

PU4301

SE330U2VDM-L-GP

SE330U2VDM-L-GP

SE330U2VDM-L-GP
PR4301
PC4305 DY 2D2R5F-2-GP
DY

2
SCD22U10V3KX-2GP

2
PR4302
42 BOOT_NB 1 2 BOOT_NB_R 1128-SB

1
S
S
S
0R3J-0-U-GP

G
PC4306
DY SC560P50V-GP

4
3
2
1

2
42 LGATE_NB

I/P cap: 10U 25V K0805 X5R/ 78.10622.51L

Inductor: 1uH PCMC063T-1R0MN Cyntec 9mohm/10mohm Isat =22Arms 68.1R01A.20B
B B
O/P cap: 330U 2V EEFSX0D331ER 9mOhm 3Arms Panasonic/79.33719.L01
H/S: SIR712DP/ POWERPAK/10.3mOhm/12.4mOhm@4.5Vgs/ 84.00172.037
L/S: SiR460DP/ POWERPAK/ 4.9mOhm/ 6.1mohm@4.5Vgs/ 84.00460.037

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

TPS51218_VDDNB
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 43 of 109

5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_1p5v0p75v

DCBATOUT PWR_DCBATOUT_1D5V
PG4401
1 2

GAP-CLOSE-PWR-3-GP
D PG4402 D
1 2

GAP-CLOSE-PWR-3-GP
PG4403
1 2 1D5V_PWR 1D5V_S3

GAP-CLOSE-PWR-3-GP
PG4404 PG4405
1 2 1 2
0728
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
5V_S5 PG4406 PG4407
1 2 1 2

SC1U10V3KX-3GP
PWR_DCBATOUT_1D5V GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP

PC4402
PG4408 PG4409
3D3V_S5 1 2 1 2

1
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
PC4403 PC4404 PC4405

PC4407
PG4410

SCD1U50V3KX-GP

SC4D7U25V5KX-GP
2
2

5
6
7
8

PC4406
1 2

SC10U25V5KX-GP
SC10U25V5KX-GP

SC10U25V5KX-GP
1

1
Rename RUNPWROK to 1D5V_S3_PWRGD

D
D
D
D
PR4402 PU4402
DY 20KR2F-L-GP DY GAP-CLOSE-PWR-3-GP

SIR172DP-T1-GE3-GP
PG4411

2
PU4401 Design Current =10.32A 1 2

1
20 12 PC4408 16.21A<OCP<19.16A
36 1D5V_S3_PWRGD PGOOD V5IN

G
S
S
S
SCD1U25V3KX-GP 1128-SB GAP-CLOSE-PWR-3-GP
PWR_0D75V_EN 17 PR4401 PG4412

4
3
2
1
VTTEN PWR_1D5V_VBST 1
15 2 1 2 1 2
PWR_1D5V_EN VBST 2D2R3J-2-GP
16
EN/PSV GAP-CLOSE-PWR-3-GP
PWR_1D5V_VREF 6 14 PWR_1D5V_DRVH 1D5V_PWR PG4413
1

VREF DRVH PL4401 1 2

PR4403
11K3R2F-2-GP 13 PWR_1D5V_SW 1 2 GAP-CLOSE-PWR-3-GP
SW PG4414
COIL-1UH-51-GP-U 1128-SB 1 2

SC4D7U6D3V5KX-3GP
2

1
PWR_1D5V_REFIN 8 11 TPS51216_DRVL

SCD1U10V2KX-4GP
5
6
7
8

2
REFIN DRVL

PC4410

PC4411
PU4403 PT4402 PT4401 GAP-CLOSE-PWR-3-GP
SCD1U25V3KX-GP

1
D
D
D
D

PG4415
10 PR4404 PG4416
C PGND DY C

SIR460DP-T1-GE3-GP

SE220U2VDM-8GP

SE220U2VDM-8GP
PWR_1D5V_MODE 19 2D2R5F-2-GP 1 2
SCD01U16V2KX-3GP

GAP-CLOSE-PWR-3-GP
2

MODE
DY
PC4409

54K9R2F-L-GP

200KR2F-L-GP
PR4405

2
1

2011/03/16 X02 GAP-CLOSE-PWR-3-GP

2

PWR_1D5V_TRIP 18 PWR_1D5V_VDDQS
PC4412

PG4417
1

9
1

TRIP VDDQS

S
S
S
TPS51216_PHS_SET

G
PR4406

1 2

PWR_1D5V_VDDQS
2

4
3
2
1

1
PWR_1D5V_VTTREF5
PR4408 VTTIN 0D75V_PWR GAP-CLOSE-PWR-3-GP
VTTREF
66K5R2F-GP 3 DY PC4413 PG4418

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP
1

PC4414 VTT SC330P50V2KX-3GP

2

1 2

SCD1U10V2KX-4GP

2
1

1
SCD22U6D3V2KX-1GP

PC4415

PC4416

PC4417
1
2

21
VTTS DY GAP-CLOSE-PWR-3-GP
2

GND PG4419
4

2
VTTGND
7 1 2
0630 modify GND
TPS51216RUKR-GP GAP-CLOSE-PWR-3-GP
1D5V_PWR

SC1U10V3KX-3GP
DDR_VREF_S3 0630 Modify:

PC4401
I/P cap: 10U 25V K0805 X5R/ 78.10622.51L

1
PR4409 ADD PC4604 1uF0603 on PWR_1D5V_VTTIN.
PWR_1D5V_VTTREF 2 1 Inductor: 1.5uH PCMC104T-1R5MH Cyntec 3.8mohm/4.2mohm Isat =33Arms 68.1R510.20I
O/P cap: 220U 2V EEFCX0D221R 15mOhm 2.7Arms Panasonic/79.22719.20L

2
0R3J-0-U-GP
0702 Modify: H/S: SIR712DP/ POWERPAK/10.3mOhm/12.4mOhm@4.5Vgs/ 84.00172.037
Add PR4611 0ohm 0603 pad L/S: SiR460DP/ POWERPAK/ 4.9mOhm/ 6.1mohm@4.5Vgs/ 84.00460.037
on PWR_1D5V_VTTREF.
0D75V_PWR 0D75V_S0
PG4420
1 2

GAP-CLOSE-PWR-3-GP Intel Sequence, Remove

PG4421
1 2

GAP-CLOSE-PWR-3-GP

B B

State S3 S5 VDDR VTTREF VTT

S0 Hi Hi On On On
Add For Sequence
S3 Lo Hi On On Off(Hi-Z)
S4/S5 Lo Lo Off Off Off 1125-1
PR4410 1 2 2D2R2J-GP PWR_0D75V_EN
18,27,36,46,47 PM_SLP_S3#
MODE
PR4411 1 2 0R2J-2-GP
PR4406 Frequency Discharge Mode 18,27 PM_SLP_S5# DY

1
200k ohm 400kHz PC4418
Tracking Discharge SCD1U10V2KX-4GP

2
100k ohm 300kHz
68k ohm 300kHz
Non-tracking Discharge
47k ohm 400kHz

0816
PR4412 2 1 0R0402-PAD PWR_1D5V_EN
18,27 PM_SLP_S5#
1

Change To SLP_S5 PC4419

DY SCD1U10V2KX-5GP
2

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RT8207_1D5V_S3
Size Document Number Rev
Custom
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 44 of 109

5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

VDDR & VDDP

Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 45 of 109

5 4 3 2 1
 A B C D E

SSID = PWR.Plane.1V1REG
0824
DCBATOUT
1128-SB
3D3V_S5 PC4602 PC4603 PC4604

SC10U25V5KX-GP
SC10U25V5KX-GP

SC10U25V5KX-GP
1

2
SCD1U50V3KX-GP
1
DY

10KR2J-3-GP

PC4605
PR4602 1D1V_PWR 1D1V_S5

1
5
6
7
8
D
D
D
D
PU4602 PG4603
SIS412DN-T1-GE3-GP Design Current =7A 1 2

2
PR4603 2 1 0R0402-PAD
4
27,36 1D1V_S5_PWRGD 11A<OCP<13A GAP-CLOSE-PWR-3-GP 4
2010/11/10 X01 PG4605

G
S
S
S
1 2
PU4601 PC4606

4
3
2
1
PR4604 1 2 PR4601 SCD1U25V3KX-GP GAP-CLOSE-PWR-3-GP
120KR2F-L-GP PWR_1D1V_PWRGD 1 11 2D2R3J-2-GP PG4606
PWR_1D1V_TRIP PGOOD GND PWR_1D1V_BOOT 1 1D1V_PWR
2 10 2PWR_1D1V_BOOT_R2 1 PL4601 1 2
PD4601 PWR_1D1V_EN TRIP VBST PWR_1D1V_UGATE
K A 3 9
SDMK0340L-7-F-GP PWR_1D1V_FB EN DRVH PWR_1D1V_PHASE GAP-CLOSE-PWR-3-GP
4 8 1 2

1
PWR_1D1V_CCM VFB SW IND-2D2UH-46-GP-U PG4607
5
CCM V5IN
7 5V_S5 1128-SB

GAP-CLOSE-PWR-3-GP
PR4605 1 2 6 PWR_1D1V_LGATE 0728 PR4606 2D2R5J-1-GP 1 2
41 3V_5V_POK
DY

1
100KR2J-1-GP DRVL PC4608

1
PG4608

SCD1U10V2KX-4GP
PC4607 GAP-CLOSE-PWR-3-GP

151218_SW_GND_VTT_1D1V
1

1
PC4601

PR4607 TPS51218DSCR-GP-U1 SC1U10V2KX-1GP 2010/11/10 X01 PT4601 PG4609

SC1KP50V2KX-1GP

2
5
6
7
8
470KR2F-GP SE220U2VDM-8GP 1 2

2
D
D
D
D
PU4603
2

2
SI7716ADN-T1-GE3-GP GAP-CLOSE-PWR-3-GP

2
PG4610
1 2

G
S
S
S
GAP-CLOSE-PWR-3-GP

SC330P50V2KX-3GP
PWR_1D1V_PWR PG4611

4
3
2
1
1 2

PC4609 GAP-CLOSE-PWR

1
2010/11/10 X01 DY

1
PR4608

2
DY PC4610
6K49R2F-1-GP
SC18P50V2JN-1-GP

2
2
PWR_1D1V_FB

1
I/P cap: 10U 25V K0805 X5R/ 78.10622.51L
PR4609
3
Inductor: 2.2uH PCMC063T-2R2MN Cyntec 18mohm/20mohm Isat =14Arms 68.2R210.20B 11K5R2F-GP 3
O/P cap: 220U 2V EEFCX0D221ER 15mOhm 3.87Arms PANASONIC/79.22719.20L
H/S: SIS412DN/ 24mohm/30mOhm@4.5Vgs/ 84.00412.037

2
L/S: SIS412DN/ 24mohm/30mOhm@4.5Vgs/ 84.00412.037

Vout=0.704V*(R1+R2)/R2

SSID = PWR.Plane.1VREG

DCBATOUT PWR_DCBATOUT_1V PWR_DCBATOUT_1V

PG4617
1 2
3D3V_S5 PC4613 PC4614 PC4618
GAP-CLOSE-PWR

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP
1

2
SCD1U50V3KX-GP
2 PG4622 2
1

X01
10KR2J-3-GP

PC4616
PR4614
1 2 DY DY DY DY

1
5
6
7
8
DY GAP-CLOSE-PWR

D
D
D
D
PG4620 PU4606 1V_PWR_1 1V_PWR 1V_S0
1 2 SIS412DN-T1-GE3-GP Design Current =4A
2

2 DY 1 PG4619 PG4604
36 1V_S0_PWRGD PR4611 GAP-CLOSE-PWR DY 6.27A<OCP<7.41A 1 2 1 2
0R2J-2-GP G
S
S
S
GAP-OPEN-PWR GAP-CLOSE-PWR-3-GP
PU4605 PC4619 X01 PG4618 PG4628
4
3
2
PR4613 1 2 PR4616 SCD1U25V3KX-GP 1 1 2 1 2
130KR2F-GPDY PWR_1V_PWRGD 1 11 2D2R3J-2-GP
PGOOD GND PL4602 1V_PWR_1 1V_PWR
PWR_1V_TRIP 2 10 PWR_1V_BOOT 1 DY 2PWR_1V_BOOT_R 2 DY 1 GAP-OPEN-PWR GAP-CLOSE-PWR-3-GP
PD4602 PWR_1V_EN TRIP VBST PWR_1V_UGATE PG4615 PG4623
K A 3 9
SDMK0340L-7-F-GP DY PWR_1V_FB 4
EN DRVH
8 PWR_1V_PHASE 1 DY 2 1 2 1 2

1
PWR_1V_CCM VFB DY SW
5
CCM V5IN
7 5V_S5 1126-SB

GAP-CLOSE-PWR-3-GP
PR4618 1 2 6 PWR_1V_LGATE 0728 PR4617 2D2R5J-1-GP GAP-OPEN-PWR GAP-CLOSE-PWR-3-GP
18,27,36,44,47 PM_SLP_S3#
DY
1

100KR2J-1-GPDY DRVL COIL-2D2UH-27-GP

SCD1U10V2KX-4GP
PC4620 PG4613 PG4625
PC4621

1
PG4621
DY PC4612

1
1 2 1 2

SCD1U10V2KX-4GP
1

1
DY DY
PC4615

PR4615 TPS51218DSCR-GP-U1 SC1U10V2KX-1GP DY PT4602 DY

SC1KP50V2KX-1GP

151218_SW_GND_VTT_1V
2

PT4603
5
6
7
8

470KR2F-GP SE220U2VDM-8GPDY GAP-OPEN-PWR GAP-CLOSE-PWR-3-GP

DY SE390U2D5VM-7GP

2
D
D
D
D

2
PU4604 PG4614 PG4626
2

SIS412DN-T1-GE3-GP 1 2 1 2

2
DY GAP-OPEN-PWR GAP-CLOSE-PWR-3-GP
PG4616 PG4627
G
S
S
S

1 2 1 2
SC330P50V2KX-3GP

PWR_1V_PWR
4
3
2
1

GAP-OPEN-PWR GAP-CLOSE-PWR-3-GP
PG4612 PG4624
PC4611 1 2 1 2

1
0823
DY PR4612

1
GAP-OPEN-PWR GAP-CLOSE-PWR
2

5K23R2F-GP DY DY PC4617
SC18P50V2JN-1-GP

2
2
1 PWR_1V_FB 1

I/P cap: 4.7U 25V K0805 X5R/ 78.47522.51L

1
Inductor: 2.2uH PCMC063T-2R2MN Cyntec 18mohm/20mohm Isat =14Arms 68.2R210.20B 0823 <Core Design>
PR4610
O/P cap: 220U 2V EEFCX0D221ER 15mOhm 3.87Arms PANASONIC/79.22719.20L 10K5R2F-GPDY
H/S: SIS412DN/ 24mohm/30mOhm@4.5Vgs/ 84.00412.037
L/S: SIS412DN/ 24mohm/30mOhm@4.5Vgs/ 84.00412.037 Wistron Corporation
2

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

1.1V
Vout=0.704V*(R1+R2)/R2 Size
A2
Document Number
Enrico 14 AMD
Rev
A00
Date: Friday, April 22, 2011 Sheet 46 of 109
A B C D E
 5 4 3 2 1

SSID = PWR.Plane.1V8REG

APW7153B for 1D8V_S0

PR4709
1
3D3V_S5 DY 2 1D8V_PW R 1D8V_S0
10KR2F-2-GP PG4704
3D3V_S5 GAP-CLOSE-PW R-3-GP
D 36 1D8V_S0_PW RGD Design Current =3A 1 2 D

PG4706

1
PR4705 PU4702 GAP-CLOSE-PW R-3-GP

2D2R2F-GP
APW 7153BQBI-TRG-GP 1 2
1

PC4715 PC4711 1D8V_PW R

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
6 PVDD PGND 5 PL4702
PG4705
2

2
7 4 PW R_1D8V_LX 1 2 GAP-CLOSE-PW R-3-GP
VDD LX#4 IND-1D5UH-23-GP 1 2

1
PC4708 8 3
POK LX#3

1
SCD1U10V2KX-5GP
PC4713 PC4714 PC4716
PW R_1D8V_FB 9 2 PR4708

2
FB GND

SC100P50V2JN-3GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
20KR2F-L-GP

2
PW R_1D8V_COMP 10 1 PW R_1D8V_RT

GND
COMP SHDN/RT

2
1

PC4707
SCD1U10V2KX-4GP
PR4706

1
PR4704 74.07153.A73 PW R_1D8V_FB

11

820KR2F-GP
1MR2J-1-GP DY

1
2

2
PR4707
PC4709 PR4710
16KR2F-GP
1 2PW R_1D8V_COMP_R
1 2

2
SC100P50V2JN-3GP 20KR2F-L-GP
PC4712
C C
1DY 2

SC47P50V2JN-3GP
Vo=0.8*(1+(R1/R2))

X01
D

PQ4702
2N7002K-2-GP
84.2N702.J31

I/P cap: 4.7U 25V K0805 X5R/ 78.47522.51L

G

O/P cap: 22U 25V M0805 X5R/ 78.22610.51L

Inductor: 3.3uH PCMC063T-3R3MN Cyntec 28mohm/30mohm Isat =13.5Arms 68.3R310.20A

2 PR47111 PW R_1D8V_RT_R
18,27,36,44,46 PM_SLP_S3#
0R0402-PAD
B B
1

PC4710
SCD1U10V2KX-5GP DY
2

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RT8015B_1D8V_S0
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 47 of 109

5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Reserved
Size Document Number Rev
A3 Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 48 of 109
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO
LVDS CONNECTOR 1 R4907
2
100KR2J-1-GP
RN4901
INVERTER POWER
BLON_OUT_C 1 8 BLON_OUT 27
LCD_TST_C 2 7
DCBATOUT_LCD LCD_TST 27
3 6
LCD_BRIGHTNESS 4 5 DCBATOUT DCBATOUT_LCD
L_BKLT_CTRL 6
SRN100J-4-GP
F4901 POLYSW-1D1A24V-GP-U

1 2
LCD1
D D
31

1
NP1 69.50007.A31 C4905 C4904
X01 1 30 2nd = 69.50007.A41 SCD1U50V3KX-GP SC1KP50V2KX-1GP

2
2 29
BLON_OUT_C 3 28
LCD_BRIGHTNESS 4 27
6 LVDS_DDC_DATA 5 26
6 25
6
6
LVDS_DDC_CLK
LVDSA_CLK 7 24 Camera Power
6 LVDSA_CLK# 8 23
6 LVDSA_DATA2 9 22 USB_CAMERA# R4903 1 2 0R0603-PAD USB_PN7 18
10 21 USB_CAMERA R4904 1 2 0R0603-PAD 3D3V_S0 3D3V_CAMERA_S0
6 LVDSA_DATA2# USB_PP7 18
6 LVDSA_DATA1 11 20 LCD_TST_C 1 TP4903TPAD14-GP A00
12 19 LCDVDD
6 LVDSA_DATA1# 3D3V_CAMERA_S0
6 LVDSA_DATA0 13 18 3D3V_S0
6 LVDSA_DATA0# 14 17 R4906 2 1 0R3J-0-U-GP
15 16 1 TP4904TPAD14-GP
NP2

1
32 C4901 C4902
EC4903 DY C4903

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP SC10U6D3V5MX-3GP
ETY-CONN30E-2-GP-U2

2
USB_CAMERA# 1 AFTP4906
USB_CAMERA 1 AFTP4907
Close to LVDS connector

C LVDSA_CLK C
LCD_BRIGHTNESS
LVDSA_CLK#
LCD_TST_C

1
EC4905 EC4906 EC4901 EC4902
DY DY

SC5D6P50V2CN-1GP

SC5D6P50V2CN-1GP
DY DY

2
SC33P50V2JN-3GP

SC33P50V2JN-3GP
For EMI request

B B

3D3V_S0 LCDVDD

Q4901 A00
1 D D 6
2 D D 5
R4908
3 G S 4 2 1
0R3J-0-U-GP
15V_S5 1 2 AO6402A-GP
R4910 330KR2J-L1-GP 84.06402.B3D
1
FPVCC_CTL1

1 2 2nd = 84.03456.D3D
C4906 SCD1U25V2KX-GP R4913
150R3J-L-GP
2 DY R4905
1
100KR2J-1-GP
Q4902
2

4 3 LCDVDD_1

5 2

6 1

2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
5V_S5 1 2
D4901 R4912 100KR2J-1-GP
A A
6 LVDS_VDD_EN 1 Q4903
3 FPVCC_CTL3
3LCDVCC_EN 1 R1 <Core Design>
2
2 R2
27 LCD_TST_EN
BAT54CPT-GP
PDTC144EU-1-GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
83.R2003.E81 Taipei Hsien 221, Taiwan, R.O.C.
2nd = 83.00054.Q81
Title
3rd = 83.BAT54.081
LCD/Inverter Connector
Size Document Number Rev
Custom
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 49 of 109
5 4 3 2 1
 5 4 3 2 1

5V_CRT_S0
Layout Note:
SSID = VIDEO 5V_CRT_S0
D5002
*Pi-filter & 150 Ohm pull-down 2
resistors should be as close

4
3
CRT_R 3
RN5002 DY
as to CRT CONN. SRN4K7J-8-GP 1
* RGB signal will hit 75 Ohm
BAV99PT-GP-U
first, then pi-filter, finally

1
2
RN5003
D CRT_RED_R D5001 D
1 8
85 VGA_CRT_RED
85 VGA_CRT_GREEN 2 7 CRT_GREEN_R CRT CONN.
DY CRT_DDCDATA_CON 2
85 VGA_CRT_BLUE 3 6 CRT_BLUE_R
CRT_DDCCLK_CON
4 5 CRT_G 3
DY
SRN0J-7-GP

1
1
C5008
DY DY C5009 1
X01
SC22P50V2JN-4GP SC22P50V2JN-4GP
CRT RGB

2
2
L5002 BAV99PT-GP-U
RN 68.00119.231
CRT_RED_R 1 2 CRT_R
6 CRT_RED 1 8 D5003
SBK160808T-300Y-N-GP
6 CRT_GREEN 2 7
2
6 CRT_BLUE 3 6 L5001
4 5 CRT_GREEN_R CRT_G CRT_B
1 2 3
SBK160808T-300Y-N-GP DY
0R8P4R-PAD-1-GP X01 1
RN5004 L5003
CRT_BLUE_R 1 2 CRT_B
SBK160808T-300Y-N-GP BAV99PT-GP-U

SC10P50V2JN-4GP

SC10P50V2JN-4GP

SC10P50V2JN-4GP
5V_CRT_S0_R 5V_CRT_S0 5V_S0
X02

8
7
6
5

1
C5005

C5006

C5007
C5002 C5003 C5004
500mA
RN5001

SC8P250V2CC-GP

SC8P250V2CC-GP

SC8P250V2CC-GP
D5004

2
SRN150F-1-GP F5001
RN5005
CRT_DDCDATA_CON 1 2 2 1
85 VGA_CRT_DDCDATA 1 4

1
2
3
4
85 VGA_CRT_DDCCLK 2 DY 3 CRT_DDCCLK_CON
FUSE-1D1A6V-4GP-U
C 69.50007.691 CH551H-30PT-GP C
SRN0J-6-GP
2nd = 69.50007.771
RN

6 DDCDATA 1 RN5006 4 5V_CRT_S0_R

6 DDCCLK 2 3 CRT1
0R4P2R-PAD
9 VCC_CRT NC#4 4
NC#11 11

CRT_DDCDATA_CON 12 16
CRT_DDCCLK_CON DDCDATA_ID1 CHASSIS#16
15 DDCCLK_ID3 CHASSIS#17 17

CRT_R 1
CRT_G CRT_RED
2 CRT_GREEN GND 5
CRT_B 3 6
CRT_BLUE GND
GND 7
C5011 1 DY2 CRT_VSYNC_CON 14 8
CRT_HSYNC_CON VSYNC GND
13 HSYNC GND 10 1
SC33P50V2JN-3GP

1
D-SUB-15-129-GP AFTP509
DY C5001
SC33P50V2JN-3GP 20.20948.015

2
X01

B B

CRT Hsync & Vsync level shift AFTP501

AFTP502
1 5V_CRT_S0
1 CRT_DDCDATA_CON
AFTP503 1 CRT_DDCCLK_CON
AFTP504 1 CRT_R
AFTP505 1 CRT_G
AFTP506 1 CRT_B
AFTP507 1 CRT_HSYNC_CON
5V_CRT_S0 AFTP508 1 CRT_VSYNC_CON

U5001
For UMA CRT 1 OE# VCC 5

6 CRT_HSYNC R5010 1 2 0R0402-PAD 2 A

3 4 CRT_HSYNC1_1 1 R5001 2 CRT_HSYNC_CON
GND Y CRT_DDCDATA_CON
83,85 VGA_CRT_HSYNC R5009 1 DY 0R2J-2-GP
2 10R2J-2-GP

1
74AHCT1G125GW -1-GP C5012 CRT_HSYNC_CON
For DIS CRT DY
SC100P50V2JN-3GP
R5031 1 2 0R0402-PAD

1
C5013 CRT_VSYNC_CON
2

DY
SYNCOE#

1
C5014 CRT_DDCCLK_CON

SC18P50V2JN-1-GP
5V_CRT_S0
2 DY

1
U5002 C5015

SC18P50V2JN-1-GP

SC100P50V2JN-3GP
2
For UMA CRT 1 5 DY
OE# VCC

2
6 CRT_VSYNC R5008 1 2 0R0402-PAD 2
A A <Core Design> A
3 4 CRT_VSYNC1_1 1 R5004 2 CRT_VSYNC_CON
GND Y 10R2J-2-GP
83,85 VGA_CRT_VSYNC R5007 1
DY
0R2J-2-GP
2
74AHCT1G125GW -1-GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
For DIS CRT
Title

Size Document Number

DCIN Rev
A3 Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 50 of 109
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO
HDMI Level Shifter & CONNECTOR HDMI CONN
HDMI1
Impedance:100 ohm 21 20
D 1 APU_HDMI_DATA2 6 D

2
3 APU_HDMI_DATA2# 6
4 APU_HDMI_DATA1 6
5
APU_HDMI_CLK# 6 APU_HDMI_DATA1# 6
APU_HDMI_CLK 7 APU_HDMI_DATA0 6
8
APU_HDMI_DATA0# 9 APU_HDMI_DATA0# 6
APU_HDMI_DATA0 10 APU_HDMI_CLK 6
11
12 APU_HDMI_CLK# 6
13
14 5V_CRT_S0_R
APU_HDMI_DATA1# 15 DDC_CLK_HDMI
APU_HDMI_DATA1 16 DDC_DATA_HDMI
17
APU_HDMI_DATA2# 18
APU_HDMI_DATA2 19
23 22 X01

1
C5102
SKT-HDMI19P-63-GP-U
499R2F-2-GP

499R2F-2-GP

499R2F-2-GP

499R2F-2-GP

499R2F-2-GP

499R2F-2-GP

499R2F-2-GP

499R2F-2-GP

SCD1U10V2KX-5GP
2
1

HPD_HDMI_CON
22.10296.171

0819
2

2
C C
R5114

R5115

R5116

R5117

R5118

R5119

R5120

R5121
R5131
HDMI_PLL_GND
1 2 DP1_HPD 6
checklist:
D

suggestion to stuff 604-ohm for UMA and PX 1KR2J-1-GP

Q5103

1
2N7002K-2-GP
R5132
84.2N702.J31 DY 2K2R2J-2-GP
2nd = 84.07002.I31

2
G

5V_S0
1

R5113
100KR2J-1-GP
DY
2

B B

5V_S0
3
4

RN5101
SRN2K2J-1-GP
2
1

6 PCH_HDMI_DATA_R 0R0402-PAD1 R5129 2 DDC_DATA_HDMI

6 PCH_HDMI_CLK_R 0R0402-PAD1 R5130 2 DDC_CLK_HDMI

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

HDMI Level Shifter/Connector

Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 51 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

eDP
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 52 of 109

5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 53 of 109
5 4 3 2 1
(Blanking)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 54 of 109
 5 4 3 2 1

SSID = User.Interface

D D

C C

ITP Connector
H_CPURST# use pull-up Resistor close
ITP connector 500 mil ( max ),
others place near CPU side.

B B

CPU ITP Connector

TCK(PIN 5)
TCK(PIN AC5)
FBO(PIN 11)

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

ITP Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 55 of 109
5 4 3 2 1
 5 4 3 2 1

SSID = SATA SATA HDD Connector

X01
3D3V_S0 HDD1
C5601 C5604

1
SC10U6D3V5KX-1GP SCD1U10V2KX-5GP
3D3V_S0 P1 V33 16 16
DY DY P2 17
V33 17

2
P3 V33
D D
NP1 NP1
5V_S0 P7 V5 NP2 NP2
P8 V5
5V_S0 P9 V5

1
C5606 C5605
AFTP5607 1 HDD1_20 P13 S1
SCD1U10V2KX-5GP V12 GND
AFTP5608 1 HDD1_21 P14 S4
SC10U10V5ZY-1GP V12 GND
AFTP5609 HDD1_22

2
1 P15 V12 GND S7
GND P4
GND P5
19 SATA_TXP0 S2 A+ GND P6
19 SATA_TXN0 S3 A- GND P10
GND P12
C5603 1 2 SCD01U16V2KX-3GP SATA_RXP0 S6
19 SATA_RXP0_C C5602 B+
19 SATA_RXN0_C 1 2 SCD01U16V2KX-3GP SATA_RXN0 S5 B- DAS/DSS P11

SKT-SATA7P-15P-80-GP

62.10065.H71

C C

ODD Connector
SATA_RX- and SATA_RX+ Trace
Length match within 20 mil X01
3D3V_S0

ODD1 integrated PU
5V_S0 R5603 2 1 ODD_PW R_5V P2 S1 19 SATA_ODD_PW RGT
+5V GND

1
0R5J-5-GP P3 S4
+5V GND R5611
GND S7
10KR2J-3-GP
18 SATA_ODD_PRSNT#
SATA_ODD_DA#_C
P1 DP GND P5 DY G547F1P81U-GP
P4 MD GND P6 ODD_PW R_5V
5V_S0
0720: Modify Zero ODD Circuit 8

2
GND
19 SATA_TXN1 S3 A- GND 9 4 EN/EN# OC# 5
100 mil
1

19 SATA_TXP1 S2 A+ 3 IN#3 OUT#6 6

SCD01U16V2KX-3GP2 1 C5607 SATA_RX1-_C
R5604 19 SATA_RXN1_C
SCD01U16V2KX-3GP2
S5 B- 2 IN#2 DY OUT#7 7
19 SATA_RXP1_C 1 C5608 SATA_RX1+_C S6 B+ 1 GND OUT#8 8

1
0R2J-2-GP

1
DY TC5604
SKT-SATA7P+6P-26-GP-U U5601 TC5603
2

SC10U10V5ZY-1GP
2
B B
74.00547.C79

SC10U10V5ZY-1GP
2
2ND =
22.10300.201
Current limit
0720: Modify Zero ODD Circuit
Active High
typ =>2A
3D3V_S0 3D3V_S0
1

2
R5606 R5612
10KR2J-3-GP
DY DY 10KR2J-3-GP
0721 Remove ODD_DA PU
R5608
2

SATA_ODD_DA#_C 2 DY 1 SATA_ODD_DA#
ODD_PW RGT#
0R2J-2-GP
G
D

Q5602 Q5601
2N7002K-2-GP 2N7002K-2-GP
When the drive is powered on, the FET to the MD/DA pin drive is OFF. DY DY
When the drive is powered off, the FET to the MD/DA pin is ON 84.2N702.J31
A <Core Design> A
84.2N702.J31
G

D
S

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
DY Taipei Hsien 221, Taiwan, R.O.C.
2 R5607 1 SATA_ODD_DA# 17
0R2J-2-GP
SATA_ODD_PW RGT 2 R5613 1 ODD_DA_Q 18 Title
0R0402-PAD

Size Document Number

HDD/ODD Rev
0712
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 56 of 109
5 4 3 2 1
 5 4 3 2 1

SSID = ESATA

D D

C C

(Blanking)

B B

A A
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

ESATA/USB Charger Rev
A3
Enrico 14 AMD A00
5 4 3 2 Date: Friday, April 22, 2011 Sheet
1 57 of 109
 5 4 3 2 1

SSID = AUDIO

Speaker
Connector

5
D D
SPK1
1 ACES-CON4-4-GP
29 AUD_SPK_L-

29 AUD_SPK_L+ 2
29 AUD_SPK_R- 3
29 AUD_SPK_R+ 4

6
1

1
EC5801
MLVG0402220NV05BP-GP-U EC5802 EC5803 EC5804

MLVG0402220NV05BP-GP-U

MLVG0402220NV05BP-GP-U

MLVG0402220NV05BP-GP-U
DY DY DY DY AFTP5805 1
2

2
20.F0765.004

AFTP5801 1 AUD_SPK_L-
AFTP5802 1 AUD_SPK_L+
AFTP5803 1 AUD_SPK_R-
AFTP5804 1 AUD_SPK_R+

C C

FOR EMI
1DY 2
EC5810 SCD1U10V2KX-5GP
B B
1 2
EC5811 SCD1U10V2KX-5GP

1 2
EC5812 SCD1U10V2KX-5GP

1DY 2
EC5813 SCD1U10V2KX-5GP

1 2
EC5814DY SCD1U10V2KX-5GP

1DY 2
EC5815 SCD1U10V2KX-5GP

AUD_AGND

AFTP5808
MIC2 0804 Change to AGND
3
1
1

29,82 INT_MIC_L_R
A 2 DY <Core Design> A

AFTP5809 1 4

ACES-CON2-19-GP Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
AUD_AGND
Title

Audio Jack
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 58 of 109
5 4 3 2 1
SSID = LOM LAN TransFormer

XF5901

Rx Side
9 8 MDO1-
31 LAN_MDI1N

11 6

10 7 MDO1+
31 LAN_MDI1P
1CT:1CT
Tx Side
15 2 MDO0-
31 LAN_MDI0N

14 3

16 1 MDO0+
31 LAN_MDI0P
1CT:1CT

SC1KP3KV8KX-GP-U

SC1KP3KV8KX-GP-U
X01 X01

2 0R3J-0-U-GP

0R3J-0-U-GP
XFORM-12P-36-GP
C5904
SCD01U16V2KX-3GP

2
1

1
Non-Surge Surge Surge Non-Surge

C5901
2

R5903

C5902

R5904
EU5901

2
X02

1
LAN_MDI0P 1 MDO2+ MDO3+
MDO2- MDO3-
LAN_MDI0N 3

1
Surge

4
3
LAN_MDI1P 4 R5901 R5902
RN5901

75R5F-1-GP

75R5F-1-GP
LAN_MDI1N 6 SRN75J-2-GP-U

2
TVLST2304AD0-GP

1
2
X01

C5911
C5903
ES5901

1
MDO0+ 1 2 MDO0- Surge Non-Surge
Surge

SC1KP2KV6KX-GP
SC1KP3KV8KX-GP-U
2

2
GT1206150ASMD-GP
ES5902

MDO1+ 1 Surge 2 MDO1-

GT1206150ASMD-GP

RJ45
RJ45
9 NP1

MDO0+ 1

MDO0- 2
MDO1+ 3 MDO0+ 1 AFTP5907
MDO2+ 4 MDO0- 1 AFTP5908
MDO2- 5 MDO1+ 1 AFTP5901
MDO1- 6 MDO1- 1 AFTP5904
MDO3+ 7 MDO2+ 1 AFTP5902
MDO3- 8 MDO2- 1 AFTP5903
<Core Design>
MDO3+ 1 AFTP5905
10 NP2 MDO3- AFTP5906
1
RJ45-8P-76-GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
22.10177.J61
LAN
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 59 of 109
 5 4 3 2 1

SSID = Flash.ROM
SPI FLASH ROM (2M byte) for KBC
3D3V_S5 3D3V_AUX_KBC

D
3D3V_S5 3D3V_AUX_KBC D

2
DY R6005 R6007

2
0R2J-2-GP 0R0402-PAD
R6008 R6009
DY 0R2J-2-GP 0R0402-PAD

1
SPI_VCC
Reserved 795 use LPC ROM or 791 LPC ROM used

1
Reserved 795 use LPC ROM or 791 LPC ROM used

1
SPI_POW R C6001 C6002

SC10U6D3V5KX-1GP

SCD1U10V2KX-5GP
DY

2
1

4
3
R6002
RN6002
SRN100KJ-6-GP

100KR2J-1-GP
2

1
2
SPI_HOLD_0#

U6001

27 EC_SPI_CS# 1 8 SPI_VCC
R6003 1 CS# VCC
27 EC_SPI_DI 2 33R2J-2-GP SPI_SO 2 DO/IO1 HOLD#/IO3 7
27 EC_SPI_W P# R6004 2 1 0R2J-2-GP EC_SPI_W P#_R 3 6
DY WP#/IO2 CLK EC_SPI_CLK 27
4 GND DI/IO0 5 EC_SPI_DO 27
C C

1
W 25Q16BVSSIG-GP DY DYEC6001
DY R6001 72.25Q16.001 EC6003

SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP
10KR2J-3-GP

2
2nd: 72.25Q16.001
3rd: 72.25F16.00P
1
4th: 72.02516.A01
Reserved 795 use LPC ROM or 791 LPC ROM used

SSID = RBATT
RTC_AUX_S5 3D3V_AUX_S5

B U6003 B
2
+RTC_VCC
3 X01 RTC1

1 RTC_PW R 1 R6006 2 1 PWR

2

510R2J-1-GP 2
C6005 GND
CH715FPT-GP NP1
SC1U6D3V2KX-GP NP1
NP2
1

NP2
83.R0304.B81
2nd = 83.00040.E81
BAT-AAA-BAT-054-P04-GP-U
Width=20mils
62.70001.061

3D3V_S0

R6032
Q6001 DY 10KR2J-3-GP
G
1

D RTC_SENSE 17
1

R6031 S
10MR2J-L-GP
A <Core Design> A
2N7002K-2-GP
2

84.2N702.J31
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

Flash/RTC Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 60 of 109
5 4 3 2 1
 5 4 3 2 1

SSID = USB

USB20_VCCA USB20_VCCA
5V_S5 U6102
100 mil USB2
1 GND OUT#8 8 5
D 2 IN#2 OUT#7 7 1 D
3 IN#3 OUT#6 6

1
U6102_EN 4 5 C6103 C6104 TC6101 TC6103 USB_PN0_R 2
EN/EN# OC# DY DY

1
C6102 USB_PP0_R 3

ST100U6D3VBML1GP
SCD1U16V2KX-3GP

ST220U6D3VDM-15GP
SC10U10V5ZY-1GP
SC1U10V3ZY-6GP 4

2
G547F2P81U-GP AFTP6102 1 6

2
74.00547.A79 SKT-USB6-16-GP
USB_OC#1 18

LOW ACTIVE TYPE!!

22.10321.S01
R6101 X01
27 USB_PW R_EN# 1 2
0R0402-PAD

X01

USB20_VCCB
5V_S5 U6101 AFTP6101 1 USB20_VCCA
100 mil AFTP6103 1 USB_PN0_R
1 8 AFTP6104 1 USB_PP0_R
GND OUT#8
2 IN#2 OUT#7 7
3 IN#3 OUT#6 6

1
C 4 5 C6107 C6108 TC6102 C
EN/EN# OC# DY
1

C6101 DY

SCD1U16V2KX-3GP

ST220U6D3VDM-15GP
SC10U10V5ZY-1GP
SC1U10V3ZY-6GP

2
G547F2P81U-GP
2

USB_OC#2 18
U6102_EN

LOW ACTIVE TYPE!!

27 USB_PW R_EN# 1 R6104 2

0R0402-PAD

X02

B R6103 B
0R0603-PAD
USB_PP0_R 1 2 USB_PP0 18
X01
1

C6105
SC6D8P50V2DN-GP
2

R6102
0R0603-PAD
USB_PN0_R 1 2 USB_PN0 18
X01
1

C6106
SC6D8P50V2DN-GP
2

A <Core Design> A

U6105

USB_PN0_R 1 ESD I/O1 ESD I/O4 6 USB_PP0_R Wistron Corporation

2 5 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
GND VP 5V_S5
Taipei Hsien 221, Taiwan, R.O.C.
3 DY
ESD I/O2 ESD I/O3 4
Title
IP4220CZ6-GP
USB Power SW
Size Document Number Rev
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 61 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

USB 3.0
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 62 of 109

5 4 3 2 1
 5 4 3 2 1

SSID = User.Interface

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Bluetooth
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 63 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

F/P
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 64 of 109
5 4 3 2 1
 5 4 3 2 1

SSID = Wireless Mini Card Connector(802.11a/b/g/n)

D D
W LAN1
3D3V_S0
53
3D3V_S0 1D5V_S0 NP1
X01 1 2
1D5V_S0
AFTP6505 1 W LAN_ACT 3 4
DY 0R2J-2-GP BT_ACT
1

1
27 BLUETOOTH_EN 1 2 5 6
DY R6535 18 CLK_PCIE_W LAN_REQ# 7 8
C6502 C6503 C6504 C6505 C6506
9 10
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
2

2
17 CLK_PCIE_W LAN# 11 12
17 CLK_PCIE_W LAN 13 14
15 16

27 E51_RXD 17 18
27 E51_TXD 19 20 W IFI_RF_EN 27
21 22 PLT_RST# 17,31,71,83
5V_S5 17 PCIE_RXN2 23 24 3D3V_S0
W LAN_ACT 17 PCIE_RXP2 25 26
27 28 1D5V_S0
1

29 30 PCH_SMBCLK 14,15
C6501 C6508 17 PCIE_TXN2 31 32 PCH_SMBDATA 14,15
DY DY 17 PCIE_TXP2 33 34
SC220P50V2KX-3GP
SCD1U16V2KX-3GP

USB_P1-
2

35 36 0726
37 38 USB_P1+
3D3V_S0 39 40 X01
41 42
2010/07/09 Pop R6510 for Wifi/BT combo module 43 44 LED_W LAN#
C LED_W LAN# 68 C
27 BLUETOOTH_EN 1 2 45 46 LED_W PAN#
R6510 0R3J-0-U-GP LED_W PAN# 68
47 48 1D5V_S0
49 50
5V_S5 1 2 +5V_MINI_DEBUG 51 52 3D3V_S0
R6503 DY 0R3J-0-U-GP NP2
54

SKT-MINI52P-41-GP

X02

X01
R6406
1 2 USB_P1+
18 USB_PP1
B 0R0402-PAD B
X01
1

C6509
SC6D8P50V2DN-GP
2

X01
R6405
1 2 USB_P1-
18 USB_PN1
0R0402-PAD
X01
1

C6510
SC6D8P50V2DN-GP
2

05/19 Add Common Mode Choke

2010/07/16 Change CMC L6401 to smaller 69.10118.001 (the same same as other CMCs on MB) and rename L6401 to TR6501.
Change R6406,R6405 to 0R 0402 size <Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

MINICARD(WLAN)/ITP CONN
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 65 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

WWAN
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 66 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 67 of 109
5 4 3 2 1
 5 4 3 2 1

X01 R6834
1 2
0R0402-PAD

FRONT POWER LED PLED1

5V_S5 SSID = User.Interface
Q6801 R6806
C LED_PW R 1 2 FPOW ER_LED_A 2 1
R1 K A
B 330R2J-3-GP
DY E

3
R2
LED-W -27-GP
PDTC124EU-1-GP
83.01221.R70
27 PW RLED#
D 19 SATA_LED# 5V_S0 D

Q6805
HDLED1
R2
E

3
B R6812
R1
C SATA_LED_R 1 2 HDD_LED_A 1A K2
330R2J-3-GP
LED-W -27-GP EC6801 SC220P50V2KX-3GP
PDTA143ET-GP LED_PW R 1 2
SATA HDD LED(White) 83.01221.R70 DY
84.00143.M11
EC6810 SC220P50V2KX-3GP
SATA_LED_R DY
1 2

EC6807 SC220P50V2KX-3GP
DY
W HITE_LED_BAT# 1 2

EC6809 SC220P50V2KX-3GP
X01 AMBER_LED_BAT# DY
1 2

R6835
Battery LED2(WHITE_LED) 1 2
0R0402-PAD
Q6807 R6801
C W HITE_LED_BAT# 1 2 BAT_W HITE# WHITE
R1 LED-OW -3-GP
B DY 330R2J-3-GP
C E 5V_S5 C
R2 3
PDTC124EU-1-GP
1
27 BATT_W HITE_LED# 84.00124.H1K
27 CHG_AMBER_LED# 2

R6836
1 2 CHLED1
0R0402-PAD

Q6808 83.00326.G70
C AMBER_LED_BAT# 2 R6803 1 BAT_AMBER#
B R1
DY
AMBER
E 499R2F-2-GP
R2
PDTC124EU-1-GP

84.00124.H1K
Battery LED1(AMBER_LED)

Wireless LED 5V_S0

B D6831 B
65 LED_W LAN# 2 Q6831
R2
E
W LAN_LED#_R R6833 LED-W -27-GP
3 B R1
C W LAN_LED_R 1 2 W LAN_LED_B 1 2
A K
65 LED_W PAN# 1 330R2J-3-GP
PDTA144VT-GP W LED1
3
1

BAW 56-2-GP 84.00144.P11

EC6832

DY 83.01221.R70
SC220P50V2KX-3GP

27 W LAN_LED# 1
R6839
DY 0R2J-2-GP
2

Power button
PW RBT1
5
1A 1B

2A 2B
A 3A 3B <Core Design> A
1 2 KBC_PW RBTN#_C 4A 4B
27 KBC_PW RBTN# R6802 6
100R2J-2-GP
ACES-CONN8G-GP Wistron Corporation
AFTP6801 1 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
1 AFTP6802 Taipei Hsien 221, Taiwan, R.O.C.

Title

20.K0464.004 LED Bard/Power Button

Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 68 of 109
5 4 3 2 1
 5 4 3 2 1

X01
SSID = KBC

D
KB1
31
1
AFTP6901 TouchPad Connector D

1 KB_DET# 27
2 KROW 7 1
3 KROW 6 1 AFTP6902
4 KROW 4 1 AFTP6903
5 KROW 2 1 AFTP6904 5V_S0
6 KROW 5 1 AFTP6905 5V_S0
7 KROW 1 1 AFTP6906
8 KROW 3 1 AFTP6907
9 KROW 0 1 AFTP6908
10 KCOL5 1 AFTP6909

2
1

1
11 KCOL4 1 AFTP6910 C6901
12 KCOL7 1 AFTP6911 KROW [0..7] 27 RN6901 SCD1U10V2KX-5GP
13 KCOL6 1 AFTP6912 SRN10KJ-5-GP

2
14 KCOL8 1 AFTP6913
15 KCOL3 1 AFTP6914 KCOL[0..16] 27 TPAD1
16 KCOL1 1 AFTP6915

3
4
17 KCOL2 1 AFTP6916 6
18 KCOL0 1 AFTP6917 4A 4B
19 KCOL12 1 AFTP6918 3A 3B
KCOL16 AFTP6919 27 TPCLK
20 1 27 TPDATA 2A 2B
21 KCOL15 1 AFTP6920
22 KCOL13 1 AFTP6921 AFTP6927 1 1A 1B

1
23 KCOL14 1 AFTP6922 5
24 KCOL9 1 AFTP6923 C6902 DY DY C6903
25 KCOL11 1 AFTP6924 SC33P50V2JN-3GP SC33P50V2JN-3GP ACES-CONN8G-GP

2
26 KCOL10 1 AFTP6925
C 27 CAP_LED_R AFTP6926 CAP_LED_R C
28
29
30
32 1 AFTP6957 20.K0464.004
JAE-CON30-7-GP 1 AFTP6972
AFTP6929 1 5V_S0
20.K0565.030 AFTP6930 1 TPCLK
AFTP6931 1 TPDATA

20101116 X02 Modify:

Change R6906 to 1K from 390ohm for
fine tune LED illumination.
20101118 X02:
Dell recommand: change all white LEDs resistor to 620 ohm.
20101202 X02:
Dell recommand: change all white LEDs resistor to 604 ohm.

B 5V_S5 B
Q6902 CAP_LED_R
R2
R6905 E
1 2 B R6906
27 CAP_LED# R1
CAP_LED_Q CAP_LED_R
C 1 2
15KR2J-1-GP 604R2F-2-GP
PDTA143ET-GP
84.00143.M11
2nd = 84.02143.011
3rd CAP_LED_1
= 84.00143.N11
1 2
R6907 DY100R2J-2-GP
CAP_LED:(X01 Low actived)
Connect to KB driving internal LED directly.(MAX 25mA)

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Key Board/Touch Pad

Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 69 of 109
5 4 3 2 1
 5 4 3 2 1

SSID = Hall.Sensor
D D

3D3V_S5

1
-1_0623 3D3V_S5
HALL1 DY R6901
100KR2J-1-GP
NP2
C 5 6 C

2
4 7
3 DY 8 LID_CLOSE# 27,82
2 9

1
1 10
C6904
NP1
DY SCD047U16V2KX-1-GP

2
ACES-CONN10C-2-GP
20.F1513.010

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Hall Effect Sensor

Size Document Number Rev
A4
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 70 of 109
5 4 3 2 1
 5 4 3 2 1

SSID = Debug
RN7102
1 8 LPC_AD3_R_DB1
17,27 LPC_AD3 LPC_AD2_R_DB1
17,27 LPC_AD2 2 7
3 6 LPC_AD1_R_DB1 X01
D 17,27 LPC_AD1 DY LPC_AD0_R_DB1 3D3V_S0 D
17,27 LPC_AD0 4 5

SRN0J-7-GP DB1
1
LPC_AD0_R_DB1 2
LPC_AD1_R_DB1 3
LPC_AD2_R_DB1 4
LPC_AD3_R_DB1 5
1 DY 2 LPC_FRAME#_R 6
17,27 LPC_FRAME# R7107 DY
17,31,65,83 PLT_RST# 7
0R2J-2-GP 8
17,21 CLK_PCI_LPC R7102 1 2 0R2J-2-GP 9
DY 10
X02 11
12
Layout close to SB
MLX-CON10-7-GP

20.D0183.110
C C
PCB Footprint = PAD-10P-177042
DY HDT+

1D8V_S0 HDT+ Connectors

1 TP7101 TPAD14 TPAD14 TP7108 1 APU_TCK 6
1 TP7102 TPAD14 TPAD14 TP7109 1 APU_TMS 6
TPAD14 TP7110 1 APU_TDI 6
TPAD14 TP7111 1 APU_TDO 6
6 APU_TRST# 0R2J-2-GP R7101 1 DY 2APU_TRST#_R
1 TP7103 TPAD14 TPAD14 TP7112 1 H_CPUPWRGD 6,17,36,42
DBRDY3 1 TP7104 TPAD14 TPAD14 TP7113 1 APU_RST_L_BUF 6
B DBRDY2 1 TP7105 TPAD14 TPAD14 TP7114 1 B
APU_DBRDY 6
DBRDY1 1 TP7106 TPAD14 TPAD14 TP7115 1 APU_DBREQ# 6
TPAD14 TP7116 1APU_TEST19_PLLTEST0_R1 DY 2 R7105 0R2J-2-GP
APU_TEST19_PLLTEST0 6
1 TP7107 TPAD14 TPAD14 TP7117 1APU_TEST18_PLLTEST1_R1 2 R7106 0R2J-2-GP
APU_TEST18_PLLTEST1 6
DY
CRB:placed 0-ohm
RN7101 checklist:if both SCAN and HDT+ header are implement
8 1 DBRDY3 placed 15-ohm
7 2 DBRDY2
6 DY 3 DBRDY1
5 4

SRN10KJ-6-GP

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Dubug connector
Size Document Number Rev
A4
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 71 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RESERVED
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 72 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 73 of 109
5 4 3 2 1
 5 4 3 2 1

SSID = SDIO SD/XD/MS Card Reader

D D
3D3V_CARD_S0
CARD1

11 SD_VDD/MMC_VDD MS_DATA0 12 XD_D1/SD_D5/MS_D0 32

MS_DATA1 13 XD_D4/SD_D3/MS_D1 32
4 10 XD_D0/SD_CLK/MS_D2_R
3D3V_CARD_S0 MS_VCC MS_DATA2
MS_DATA3 7 XD_ALE/SD_D7/MS_D3 32

32 XD_W E#/SD_CD# 20 SD_CD MS_INS 8 XD_RE#/MS_INS# 32

For EMI

SC2D2U6D3V3KX-GP
32 XD_D4/SD_D3/MS_D1 3 SD_CD/DAT3/MMC_RSV MS_BS 15 XD_D6/MS_BS 32
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
5 XD_RDY/SD_W P/MS_CLK 32
C7404

C7405
R7407 33R2J-2-GP XD_D0/SD_CLK/MS_D2_R MS_SCLK
1

1 32 XD_D0/SD_CLK/MS_D2 2 1 14
C7401

C7402

C7403

SD_CLK/MMC_CLK
32 XD_D2/SD_CMD 6 SD_CMD/MMC_CMD
DY DY DY GND 23
2

32 XD_CLE/SD_D0/MS_D7 18 SD_DAT0/MMC_DAT GND 24

32 XD_CE#/SD_D1 19 SD_DAT1
32 XD_D5/SD_D2/MS_D5 1 SD_DAT2 SD_GND 21

32 XD_RDY/SD_W P/MS_CLK 22 SD_WP/SW MS_VSS 2

MS_VSS 16

NP1 NP1 SD_VSS/MMC_VSS1 9

NP2 NP2 SD_VSS/MMC_VSS2 17

CARD-PUSH-22P-GP

C
20.I0110.021 C

0810 Vendor Recommand

XD_ALE/SD_D7/MS_D3
XD_D1/SD_D5/MS_D0
XD_CLE/SD_D0/MS_D7
XD_CE#/SD_D1
XD_D5/SD_D2/MS_D5
XD_D4/SD_D3/MS_D1
XD_D2/SD_CMD
XD_D0/SD_CLK/MS_D2_R
XD_W E#/SD_CD#
XD_RDY/SD_W P/MS_CLK

SC6D8P50V2DN-GP

SC6D8P50V2DN-GP

SC6D8P50V2DN-GP

SC6D8P50V2DN-GP

SC6D8P50V2DN-GP

SC6D8P50V2DN-GP

SC6D8P50V2DN-GP

SC6D8P50V2DN-GP

SC6D8P50V2DN-GP
SC4D7P50V2CN-1GP

EC7408
1

1
EC7401

EC7402

EC7403

EC7404

EC7405

EC7406

EC7407

EC7409

EC7410
2

2
B B

For EMI

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CARD Reader Connector

Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 74 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Express Card
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 75 of 109

5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 76 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 77 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 78 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 79 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 80 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

UNUSED PARTS/EMI Capacitors

Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 81 of 109

5 4 3 2 1
 5 4 3 2 1

X01
X02
SSID = USB USB20_VCCB
USB_PN2_R R8203 1 2 0R0603-PAD USB_PN2 18

D IOBD1 D
USB_PP2_R R8204 1 2 0R0603-PAD USB_PP2 18 17

2
3
4
5
6
USB_PN2_R 7
USB_PP2_R 8
9
X02 USB_PN6_R 10
USB_PP6_R 11
12
USB_PN6_R R8201 1 0R0603-PAD 13
2 USB_PN6 18 14
15
USB_PP6_R R8202 1 0R0603-PAD 16
2 USB_PP6 18
18

PTW O-CON16-1-GP

20.K0429.016

C C

IOBD2
17

29,58 INT_MIC_L_R 1

SSID = AUDIO 29 AUD_HP1_JACK_L2

2
3
29 AUD_HP1_JACK_R2 4
5
29 MIC_IN_L 6
29 MIC_IN_R 7
8
29 EXT_MIC_JD# 9
29 AUD_HP1_JD# 10
11
B
27,70 LID_CLOSE# 12 B
13
3D3V_S5 14
15
16

18

AUD_AGND PTW O-CON16-1-GP

20.K0429.016

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

IO Board Connector Rev
A3 Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 82 of 109

5 4 3 2 1
 5 4 3 2 1

CONFIGURATION STRAPS
SSID = VIDEO VGA1A 1 OF 7 RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 3K RESISTOR
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
X = DESIGN DEPENDANT
THEY MUST NOT CONFLICT DURING RESET NA = NOT APPLICABLE

PLATFORM
4 PEG_TXP0 PEG_TXP0 AF30 AH30 PEG_C_RXP0
C8306 DIS_PX
1 2 SCD1U10V2KX-5GP STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS RECOMMEND
PEG_TXN0 PCIE_RX0P PCIE_TX0P
AG31 PEG_C_RXN0
C8305 SCD1U10V2KX-5GP
PEG_RXP0 4 SETTING
4 PEG_TXN0 AE31 PCIE_RX0N PCIE_TX0N DIS_PX
1 2 PEG_RXN0 4
Transmitter Power Savings Enable
TX_PWRS_ENB GPIO0 0: 50% Tx output swing 1: Full Tx output swing X 1
4 PEG_TXP1 PEG_TXP1 AE29 AG29 PEG_C_RXP1
C8303 DIS_PX
1 2 SCD1U10V2KX-5GP
PCIE_RX1P PCIE_TX1P PEG_RXP1 4
D 4 PEG_TXN1 PEG_TXN1 AD28 AF28 PEG_C_RXN1
C8304 DIS_PX
1 2 SCD1U10V2KX-5GP PCIE TRANSMITTER DE-EMPHASIS ENABLED D
PCIE_RX1N PCIE_TX1N PEG_RXN1 4
TX_DEEMPH_EN GPIO1 0:Tx de-emphasis disabled 1:Tx de-emphasis enabled X 1
4 PEG_TXP2 PEG_TXP2 AD30 AF27 PEG_C_RXP2
C8310 2 SCD1U10V2KX-5GP
DIS_PX
1 0:Advertises the PCIe device as 2.5GT/s capable at power on.
PCIE_RX2P PCIE_TX2P PEG_RXP2 4
PEG_TXN2 AC31 AF26 PEG_C_RXN2
C8309 2 SCD1U10V2KX-5GP
DIS_PX
1 BIF_GEN2_EN_A GPIO2 0 0
4 PEG_TXN2 PCIE_RX2N PCIE_TX2N PEG_RXN2 4 1:Advertises the PCIe device as 5.0GT/s capable at power on.
optional input allow the system to request a fast
4 PEG_TXP3 PEG_TXP3 AC29 AD27 PEG_C_RXP3
C8308 2 SCD1U10V2KX-5GP
DIS_PX
1 GPIO5_AC_BATT GPIO5 ? 0
PCIE_RX3P PCIE_TX3P PEG_RXP3 4 power reduction by setting GPIO5 to low.
4 PEG_TXN3 PEG_TXN3 AB28 AD26 PEG_C_RXN3
C8307 2 SCD1U10V2KX-5GP
DIS_PX
1
PCIE_RX3N PCIE_TX3N PEG_RXN3 4

GPIO8_ROMSO GPIO8 RESERVED 0 0

AB30 PCIE_RX4P PCIE_TX4P AC25

PCI EXPRESS INTERFACE

AA31 PCIE_RX4N PCIE_TX4N AB25 0:VGA Controller capacity enabled
VGA_DIS GPIO9 1:The device won't be recognized as the system's VGA controller 0 0
AA29 Y23 BIOS_ROM_EN=1, Config[2:0] defines the ROM type 0 0 1
PCIE_RX5P PCIE_TX5P BIOS_ROM_EN=0, Config[2:0] defines the primary memory aperture size X X X
Y28 PCIE_RX5N PCIE_TX5N Y24 ROMIDCFG[2:0] GPIO[13:11] (256MB)
Y30 PCIE_RX6P PCIE_TX6P AB27 GPIO21_BB_EN GPIO21 RESERVED 0 0
W31 PCIE_RX6N PCIE_TX6N AB26
0:Disable external BIOS ROM device
BIOS_ROM_EN GPIO_22_ROMCSB X 0
1:Enable external BIOS ROM device
W29 PCIE_RX7P PCIE_TX7P Y27
V28 PCIE_RX7N PCIE_TX7N Y26 VIP Device Strap Enable indicates to the software driver that it sense
VIP_DEVICE_STRAP_EN V2SYNC X 0
whether or not a VIP device is connected on the VIP Host interface.
V30 PCIE_RX8P PCIE_TX8P W24
C
U31 PCIE_RX8N PCIE_TX8N W23 RSVD H2SYNC RESERVED 0 0 C

U29 PCIE_RX9P PCIE_TX9P V27 RSVD GENERICC RESERVED 0 0

T28 PCIE_RX9N PCIE_TX9N U26

AUD[1] HSYNC X 1
T30 PCIE_RX10P PCIE_TX10P U24 AUD[1:0]:11-Audio for both DisplayPort and HDMI
R31 PCIE_RX10N PCIE_TX10N U23
AUD[0] VSYNC X 1
R29 PCIE_RX11P PCIE_TX11P T26
P28 PCIE_RX11N PCIE_TX11N T27

2010/06/11
P30 PCIE_RX12P PCIE_TX12P T24
N31 PCIE_RX12N PCIE_TX12N T23
3D3V_VGA_S0
3D3V_VGA_S0
N29 P27
M28
PCIE_RX13P
PCIE_RX13N
PCIE_TX13P
PCIE_TX13N P26 2010/06/11 PIN STRAPS R8325
1 2 10KR2J-3-GP
DIS_PX Need to check 85 JTAG_TMS_VGA DY
M30 P24 R8328
PCIE_RX14P PCIE_TX14P R8301 3KR2J-2-GP
L31 P23 1 DIS_PX
2 2 1 10KR2J-3-GP
PCIE_RX14N PCIE_TX14N 85 TX_PW RS_ENB DY
85 TX_DEEMPH_EN R8302 1 DIS_PX
2 3KR2J-2-GP
2010/07/13 Stuff for 5.0GT/S 84 TESTEN
L29 M27 R8327
PCIE_RX15P PCIE_TX15P R8303
K30 PCIE_RX15N PCIE_TX15N N26 85 BIF_GEN2_EN_A 2 10KR2J-3-GP
1 DIS_PX 1DIS_PX 2 5K11R2F-L1-GP
B R8304 B
2010/06/10 1 2 10KR2J-3-GP
85 GPIO8_ROMSO DY R8326 1 2 10KR2J-3-GP
Move CAPs close to CPU CLOCK R8305 1 2 10KR2J-3-GP
85 JTAG_TRST#_VGA DY
AK30
85 VGA_DIS DY R8329 1 2 10KR2J-3-GP
17 CLK_PCIE_VGA PCIE_REFCLKP 85 JTAG_TCK_VGA
17 CLK_PCIE_VGA# AK32 PCIE_REFCLKN DY
85 CONFIG0 R8306 1 DIS_PX
2 10KR2J-3-GP
1V_VGA_S0
CALIBRATION R8307 1 2 10KR2J-3-GP
Y22 PCIE_CALRP 1 DIS_PX
2
85 CONFIG1 DY
PCIE_CALRP R8321 1K27R2F-L-GP R8308 1 2 10KR2J-3-GP
JTAG SIGNAL OPTION
1DIS_PX 2 PW RGOOD N10 AA22 PCIE_CALRN 1 DIS_PX
2
85 CONFIG2 DY Normal Debug pilot run
R8314 10KR2F-2-GP PWRGOOD PCIE_CALRN R8315 2KR2F-3-GP R8309 1 DY 2 10KR2J-3-GP Signal
50,85 VGA_CRT_VSYNC mode mode mode
R8316
ATI_RST# 1 2 VGA_RST# AL27 R8310 1 DY 2 10KR2J-3-GP
PERST# 50,85 VGA_CRT_HSYNC
0R0402-PADDIS_PX TESTEN "1"(PU) "1"(PU) "0"(PD)
1

C8312 ROBSON-GP-U Colay with Seymour-XT-S3

DY SC47P50V2JN-3GP 71.ROBSO.M01 (71.SEYMR.M01) JTAG_TRST# "0"(PD) "1"(PU) NC
2

DY JTAG_TCK CLK "1"(PU) NC

85 BIOS_ROM_EN R8313 1 2 10KR2J-3-GP
X01 R8330
0R2J-2-GP
R8323
85 GPIO5_AC_BATT R8318 1
DY 2 10KR2J-3-GP JTAG_TMS "1"(PU) "1"(PU) NC
2 DY 1 PLT_RST# 2 DY 1 ATI_RST#
17,86 1D5V_VGA_PW OK
85 GPIO21_BB_EN R8317 1
DY 2 10KR2J-3-GP
3D3V_VGA_S0
0R2J-2-GP
A R8324 U8301 <Core Design> A
93 1D8V_S0_VGA_PG 1 2 1 B
0R0402-PAD DIS_PX 5 3D3V_VGA_S0
VCC
1

C8311 PE_GPIO0
ADIS_PX
U8302
DY SCD1U10V2KX-4GP
2
Y 4 U8302_Y 1 B
Wistron Corporation
3 5 dGPU mode H 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2

GND VCC Taipei Hsien 221, Taiwan, R.O.C.

74LVC1G08GW -1-GP
17 PE_GPIO0 2 DIS_PX
A ATI_RST#
Y 4 ATI_RST# 85 IGPU L
73.01G08.L04 3 Title
GND

17,31,65,71 PLT_RST# R8322

2 DY 1 0R2J-2-GP
2ND = 73.7SZ08.DAH 74LVC1G08GW -1-GP IGPU with BACO H GPU_PEG/STRAPPING(1/5)
73.01G08.L04 Size Document Number Rev
0820 6,17 APU_RST# R8331 1 DIS_PX2 0R0402-PAD
2ND = 73.7SZ08.DAH A3 Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 83 of 109
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO
VGA1C 3 OF 7
88 MDA[0..31]

MDA0 K27 K17 MAA0 88,89

MDA1 DQA_0 MAA_0
J29 DQA_1 MAA_1 J20 MAA1 88,89
MDA2 H30 H23 MAA2 88,89
MDA3 DQA_2 MAA_2
H32 DQA_3 MAA_3 G23 MAA3 88,89
MDA4 G29 G24 MAA4 88,89
MDA5 DQA_4 MAA_4
F28 H24 MAA5 88,89

MEMORY INTERFACE
MDA6 DQA_5 MAA_5
D F32 DQA_6 MAA_6 J19 MAA6 88,89 D
MDA7 F30 K19 MAA7 88,89
MDA8 DQA_7 MAA_7
C30 DQA_8 MAA_8 J14 MAA8 88,89
MDA9 F27 K14 MAA9 88,89
MDA10 DQA_9 MAA_9
A28 DQA_10 MAA_10 J11 MAA10 88,89
MDA11 C28 J13 MAA11 88,89
MDA12 DQA_11 MAA_11
E27 DQA_12 MAA_12 H11 MAA12 88,89
MDA13 G26 G20 MAA13 88,89
MDA14 DQA_13 MAA_13
D26 DQA_14 MAA_14/BA0 J16 A_BA0 88,89
PLACE MVREF DIVIDERS AND CAPS CLOSE TO ASIC MDA15 F25 L15 A_BA1 88,89
MDA16 DQA_15 MAA_15/BA1
A25 DQA_16 MAA_BA2 G11 A_BA2 88,89
MDA17 C25
MDA18 DQA_17
E25 DQA_18 DQMA_0 E32 DQMA0 88
MDA19 D24 E30 DQMA1 88
1D5V_VGA_S0 1D5V_VGA_S0 MDA20 DQA_19 DQMA_1
E23 DQA_20 DQMA_2 A21 DQMA2 88
MDA21 F23 C21 DQMA3 88
MDA22 DQA_21 DQMA_3
D22 DQA_22 DQMA_4 E13 DQMA4 89
1

1
Ra R8410 Ra R8411 MDA23 F21 D12 DQMA5 89
40D2R2F-GP 40D2R2F-GP MDA24 DQA_23 DQMA_5
E21 DQA_24 DQMA_6 E3 DQMA6 89
DIS_PX DIS_PX MDA25 D20 F4 DQMA7 89
MDA26 DQA_25 DQMA_7
F19 DQA_26
MDA27 A19 H28 QSAP_0 88
2

2
MVREFDA MVREFSA MDA28 DQA_27 RDQSA_0
D18 DQA_28 RDQSA_1 C27 QSAP_1 88
MDA29 F17 A23 QSAP_2 88
DQA_29 RDQSA_2
1

1
Rb R8414 C8402 Rb R8415 C8403 MDA30 A17 E19 QSAP_3 88
100R2F-L1-GP-U SCD1U10V2KX-5GP 100R2F-L1-GP-U SCD1U10V2KX-5GP MDA31 DQA_30 RDQSA_3
89 MDA[32..63] C17 DQA_31 RDQSA_4 E15 QSAP_4 89
DIS_PX DIS_PX DIS_PX DIS_PX MDA32 E17 D10 QSAP_5 89
2

2
MDA33 DQA_32 RDQSA_5
D16 DQA_33 RDQSA_6 D6 QSAP_6 89
MDA34 F15 G5 QSAP_7 89
2

C MDA35 DQA_34 RDQSA_7 C

A15 DQA_35
MDA36 D14 H27 QSAN_0 88
MDA37 DQA_36 WDQSA_0
F13 A27
DDR3/GDDR3 Memory Stuff Option (ROBSON-S3/SEYMOUR-XT-S3) MDA38 A13
DQA_37
DQA_38
WDQSA_1
WDQSA_2 C23
QSAN_1
QSAN_2
88
88
MDA39 C13 C19 QSAN_3 88
MDA40 DQA_39 WDQSA_3
E11 DQA_40 WDQSA_4 C15 QSAN_4 89
DDR5 DDR3 MDA41 A11 E9 QSAN_5 89
MDA42 DQA_41 WDQSA_5
C11 DQA_42 WDQSA_6 C5 QSAN_6 89
MDA43 F11 H4 QSAN_7 89
MDA44 DQA_43 DIS_PX WDQSA_7
MVDDQ 1.5V 1.5V/1.8V A9 DQA_44
MDA45 C9 L18
MDA46 DQA_45 ODTA0 ODTA0 88
F9 DQA_46 ODTA1 K16 ODTA1 89
Ra 40.2R 40.2R MDA47 D8
MDA48 DQA_47
E7 DQA_48 CLKA0 H26 CLKA0 88
MDA49 A7 H25
MDA50 DQA_49 CLKA0# CLKA0# 88
Rb 100R 100R C7 DQA_50
MDA51 F7 G9
MDA52 DQA_51 CLKA1 CLKA1 89
A5 DQA_52 CLKA1# H9 CLKA1# 89
MDA53 E5
MDA54 DQA_53
C3 DQA_54 RASA0# G22 RASA0# 88
MDA55 E1 G17
MDA56 DQA_55 RASA1# RASA1# 89
G7 DQA_56
MDA57 G6 G19
MDA58 DQA_57 CASA0# CASA0# 88
G1 DQA_58 CASA1# G16 CASA1# 89
DPC_CALR (Park/Robson-S3): MDA59 G3
1D5V_VGA_S0 MDA60 DQA_59
J6 H22
Analog calibration. MDA61 J1
DQA_60 CSA0#_0
J22
CSA0#_0 88
Connect DPxx_CALR to GND through a 150-Ω (1%) resistor. MDA62 DQA_61 CSA0#_1
J3 DQA_62
MDA63 J5 G13
B 150R2F-1-GP DQA_63 CSA1#_0 CSA1#_0 89 B
CSA1#_1 K13
R8403 1 DIS_PX
2 243R2F-2-GP MEM_CALRN0 R8407 1 DIS_PX
2 MVREFDA K26
MEM_CALRP0 MVREFSA MVREFDA
1 2 J26 MVREFSA CKEA0 K20
R8408 DIS_PX 243R2F-2-GP J17
CKEA0 88
MEM_CALRN0 CKEA1 CKEA1 89
J25 MEM_CALRN0
TESTEN K7 G25
83 TESTEN TESTEN WEA0# W EA0# 88
WEA1# H10 W EA1# 89
R_MEM_2 R_MEM_1 MEM_CALRP1/DPC_CALR J8 MEM_CALRP1/DPC_CALR R8420
MEM_CALRP0 K25 AB16 PX_EN_R 1 2 PX_EN 86
R8405 R8402 MEM_CALRP0 PX_EN 0R0402-PADDIS_PX
1 DIS_PX
2 DRAM_RST_1 1 DIS_PX
2 DRAM_RST L10
88,89 MEM_RST DRAM_RST

2
51R2J-2-GP 10R2F-L-GP TPAD14 TP8401 1CLKTESTA K8 G14 R8421
CLKTESTA RSVD#G14 DIS_PX10KR2J-3-GP
** This basic topology should be used for DRAM_RST for TPAD14 TP8402 1CLKTESTB L7 CLKTESTB
2

DDR3/GDDR3/GDDR5.These Capacitors and Resistor values C8401

are an example only. The Series R and || Cap values SC120P50V2JN-1GP
DIS_PX R8409

1
5K1R2F-2-GP ROBSON-GP-U
will depend on the DRAM load and will have to be DIS_PX
1

calculated for different Memory ,DRAM Load and board C_MEM R_MEM_3 71.ROBSO.M01 Colay with Seymour-XT-S3
(71.SEYMR.M01)
2

to pass Reset Signal Spec.

C8407 2010/07/06
SCD1U10V2KX-5GP
1 2 CLKTESTA Schematics check list:
Designator For SEYMOUR For Robson Place all these components very close to GPU DY A pull-down resistor is required.
(Within 25mm) and keep all component close C8406
A to each Other (within 5mm) except R_MEM_2 SCD1U10V2KX-5GP <Core Design> A
R_MEM_1 10R 10R 1 2 CLKTESTB
DY
1

R_MEM_2 50R 50R R8419 DY DY Wistron Corporation

51R2J-2-GP R8418 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
51R2J-2-GP Taipei Hsien 221, Taiwan, R.O.C.
R_MEM_3 5K 5K
2

Title

C_MEM 120pF 120pF GPU Memory(2/5)

For normal GPU operation, these signals can be left Size Document Number Rev
A3 Enrico 14 AMD A00
floating (do not populate the capacitors and resistors).
Date: Friday, April 22, 2011 Sheet 84 of 109
5 4 3 2 1
 5 4 3 2 1

Memory ID Table
SSID = VIDEO VGA1B 2 OF 7 LVDS Interface
DVPDATA[0:3] Description
0000 DDR3 SAMSUNG-K4W1G1646G-BC11(900MHz)64M*16
VGA1F 6 OF 7
M93-S3/M92-S2 TXCAP_DPA3P
AF2
0001 DDR3 Hynix-H5TQ1G63DFR-11C (900MHz) 64M*16 AE9
DVCNTL_0/DVPDATA_18 TXCAM_DPA3N
AF4
L9
DVCNTL_1/NC#L9
N9 AG3
0010 DDR3 SAMSUNG K4W2G1646C-HC11 (900MHz) 128M*16 AE8
DVCNTL_2/TESTEN#2
DPA TX0P_DPA2P
AG5 LVDS CONTROL AB11
DVDATA_12/DVPDATA_16 TX0M_DPA2N VARY_BL
AD9 AB12
DVDATA_11/DVPDATA_20 DIGON
0011 DDR3 Hynix-H5TQ2G63BFR-11C (900MHz) 128M*16 AC10
DVDATA_10/DVPDATA_22 TX1P_DPA1P
AH3
AD7 AH1
DVPDATA[0:3] Default: Internal Pull down 1D8V_VGA_S0 DVDATA_9/DVPDATA_12 TX1M_DPA1N
AC8
DVDATA_8/DVPDATA_14
AC7 AK3
DVDATA_7/DVPCNTL_0 TX2P_DPA0P
0804 Modify for DV14 Config AB9
DVDATA_6/DVPDATA_8 TX2M_DPA0N
AK1
TXCLK_UP_DPF3P
AH20
AB8 AJ19
DVDATA_5/DVPDATA_6 TXCLK_UN_DPF3N
D AB7 AK5 D
MEM_ID3 DVDATA_4DVPDATA_4 TXCBP_DPB3P
For Seymour, R8527 1 DY 2 10KR2J-3-GP AB4
DVDATA_3/DVPDATA_19 TXCBM_DPB3N
AM3
TXOUT_U0P_DPF2P
AL21
2010/06/11 R8522 1 2 10KR2J-3-GP MEM_ID2
DPC_PVDD is DPC_VDD18 R8519 1
DY MEM_ID1
AB2
DVDATA_2/DVPDATA_21 TXOUT_U0N_DPF2N
AK20
1G 2 10KR2J-3-GP Y8 AK6
DPC_PVSS and all DPC_VSSR are DP_VSSR R8518 1 MEM_ID0 DVDATA_1/DVPDATA_2 TX3P_DPB2P
2 10KR2J-3-GP Y7 AM5 AH22
Hynix DVDATA_0/DVPDATA_0
DPB TX3M_DPB2N TXOUT_U1P_DPF1P
AJ21
TXOUT_U1N_DPF1N
X02 TX4P_DPB1P
AJ7
DVO TX4M_DPB1N
AH6
TXOUT_U2P_DPF0P
AL23

2010/07/15 Modify:
MEM_ID Control AK8
TXOUT_U2N_DPF0N
AK22
THERMTRIP_R

Q8501 change to dual 2n7002. 1D8V_VGA_S0 TX5P_DPB0P

AL7 AK24
Add R8512,R8521,C8529 for Q8501 pin2 TX5M_DPB0N TXOUT_U3P
AJ23
turn on timming control. THERMTRIP_VGA TXOUT_U3N
2010/06/11 M93-S3/M92-S2

1
W6
R8526 DPC_PVDD/DVPDATA_11 LVTMDP
V6 M92-S2/M93-S3
10KR2J-3-GPDY 1V_VGA_S0 DPC_PVSS/GND
V4
DVPDATA_3/TXCCP_DPC3P
AC6 U5 AL15
DPC_VDD18#1/DVPDAT10 DVPCNTL_2/TXCCM_DPC3N TXCLK_LP_DPE3P
AC5 AK14
2
6

DPC_VDD18#2/DVPDAT23 TXCLK_LN_DPE3N
W3
Q8501 L8507 DVPDATA_7/TX0P_DPC2P
DY (1.0V@110mA DPC_VDD10) AA5
DPC_VDD10#1/DVPDAT15 DVPDATA_1/TX0M_DPC2N
V2
TXOUT_L0P_DPE2P
AH16
2N7002KDW-GP 1 2 DPC_VDD10 AA6 AJ15
BLM15BD121SS1D-GP DPC_VDD10#2/DVPDAT17 TXOUT_L0N_DPE2N
Y4
84.2N702.A3F DVPCNTL_MV1/TX1P_DPC1P

C8526

C8527

C8528
DIS_PX W5 AL17

SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP

SCD1U10V2KX-5GP
1

2nd = 84.DM601.03F DVPDATA_9/TX1M_DPC1N TXOUT_L1P_DPE1P

AK16

1
TXOUT_L1N_DPE1N
U1 AA3
DIS_PX DIS_PX DIS_PX W1
DPC_VSSR#1/DVPCLK DVPDATA_13/TX2P_DPC0P
Y2 AH18
DPC_VSSR#2/DVPDAT5 DVPCNTL_1/TX2M_DPC0N TXOUT_L2P_DPE0P
Q5801_2

U3 AJ17

2
DPC_VSSR#3/GND TXOUT_L2N_DPE0N
27,28,36 PURE_HW_SHUTDOWN# Y6 AA12
R8525 DPC_VSSR#4/GND NC#AA12
AA1 AL19
DPC_VSSR#5/DVPCNTL_MV0 TXOUT_L3P
83 ATI_RST# 2 DY 1
0R2J-2-GP TXOUT_L3N
AK18
1

C8529 DPC DIS_PX

2 R8512 1 SCD1U10V2KX-4GP
27 PCIE_RST# DY DY 2010/07/07 Remove TP8517,TP8518,TP8506,TP8519,TP8512
2

0R2J-2-GP ROBSON-GP-U
R1
R3
SCL
I2C 0820
SDA 71.ROBSO.M01
3D3V_VGA_S0 AM26
GENERAL PURPOSE I/O R VGA_CRT_RED 50
AK26
R#
83 TX_PWRS_ENB U6
GPIO_0 1D8V_VGA_S0
C
83 TX_DEEMPH_EN U10 AL25 VGA_CRT_GREEN 50 X01 C
1

GPIO_1 G
83 BIF_GEN2_EN_A T10 AJ25
R8503 GPIO_VGA_03_DATA U8 GPIO_2 G# AVDD_A2VDDQ
DIS_PX 10KR2J-3-GP GPIO_VGA_04_CLK GPIO_3_SMBDATA
0723 Add SMBUS U7
GPIO_4_SMBCLK B
AH24 VGA_CRT_BLUE 50
83 GPIO5_AC_BATT T9
GPIO_5_AC_BATT B#
AG25 R8507 (1.8V@65mA AVDD)
TPAD14 TP8505 1 GPIO6_VGA T8 DAC1 1 2
2

DIS_PX
1 R8524 2 VGA_BLEN T7
GPIO_6
AH26 0R0402-PADDIS_PX
GPIO_7_BLON HSYNC VGA_CRT_HSYNC 50,83
GPIO17_VGA 10KR2J-3-GP P10 AJ27
83 GPIO8_ROMSO VGA_CRT_VSYNC 50,83

1
GPIO_8_ROMSO VSYNC C8501 C8503 C8504
P4

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
83 VGA_DIS GPIO_9_ROMSI
P2
GPIO_10_ROMSCK GPU_RSET
DIS_PX DY DY DY
83 CONFIG0 N6 AD22 1 2

2
GPIO_11 RSET R8514 499R2F-2-GP
83 CONFIG1 N5
GPIO_12 AVDD_A2VDDQ
83 CONFIG2 N3 AG24 R8517
GPIO_13 AVDD AVDD_A2VDDQ
Y9 AE22 AVSSQ 1 2
GPIO_6,GPIO_15_PWRCNTL_0,GPIO_16_SSIN,GPIO_20_PWRCNTL_1: GPIO_14_HPD2 AVSSQ 0R0402-PAD AVSSQ
92 PWRCNTL_0 N1
Voltage control signals for the core (VDDC and VDDCI). TPAD14-GP TP8502 GPIO16_SSIN GPIO_15_PWRCNTL_0 DIS_PX
1 M4 AE23
At Reset, these signals will be inputs with weak internal pull-down resistors. GPIO17_VGA GPIO_16_SSIN VDD1DI
R6 AD23
VBIOS can define all voltage control signals to be either 3.3-V or open drain outputs (all signals TPAD14-GP TP8506 GPIO18_VGA GPIO_17_THERMAL_INT VSS1DI AVSSQ AVSSQ
1 W10
must be the same type). The output state (high/low) of these signals is programmable for each PowerPlay state. THERMTRIP_VGA GPIO_18_HPD3
M2
GPIO_19_CTF M92-S2/M93-S3
P8 AM12 AVDD_A2VDDQ
92 PWRCNTL_1 GPIO_20_PWRCNTL_1 R2/NC#AM12
83 GPIO21_BB_EN P7 AK12
GPIO_21_BB_EN R2#/NC#AK12
83 BIOS_ROM_EN N8
GPIO_22_ROMCSB (1.8V@100mA VDD1DI)
18 PEG_CLKREQ# N7 AL11
GPIO_23_CLKREQB G2/NC#AL11
AJ11
G2#/NC#AJ11

1
AK10 C8502 C8506 C8507

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
83 JTAG_TRST#_VGA L6
B2/NC#AK10
AL9 DY DY DY
R8520 1 PWRCNTL_0 JTAG_TRST# B2#/NC#AL9
DY 23KR2J-2-GP TPAD14 TP8510 1 L5

2
JTAG_TDI
83 JTAG_TCK_VGA L3
R8521 1 PWRCNTL_1 JTAG_TCK
DY 23KR2J-2-GP 83 JTAG_TMS_VGA L1 AH12
JTAG_TDO_VGA JTAG_TMS C/NC#AH12
TPAD14 TP8503 1 K4
JTAG_TDO
DAC2 Y/NC#AM10
AM10
2010/07/07 TPAD14 TP8511 1 RSVD AF24 AJ9
RSVD#AF24 COMP/NC#AJ9
Change to RSVD based TPAD14 TP8504 1 GEN_A AB13
on DS v3.05 1D8V_VGA_S0TPAD14 TP8508 GEN_B GENERICA
1 W8 AL13
GENERICB H2SYNC
W9 AJ13
GENERICC V2SYNC
W7
1

TPAD14
R8515 TP8509 GENERICE_HPD4 AD10 GENERICD AVDD_A2VDDQ
PLACE VREFG DIVIDER AND CAP 1
GENERICE_HPD4 50 mA ROB
499R2F-2-GP AD19 VDD2DI_GPU R8504 2 1 0R2J-2-GP
CLOSE TO ASIC VDD2DI/NC#AD19 AC19_GND1ROB
AVDD_A2VDDQ
DIS_PX AC14
HPD1 VSS2DI/NC#AC19
AC19 2 (1.8V@100mA VDD2DI)
B 1D8V_VGA_S0 DPLL_PVDD R8523 0R2J-2-GP B
130 mA ROB
2

(1.8V@75mA DPLL_PVDD) GPU_VREFG AE20 A2VDD_GPU R8508 2 1 0R2J-2-GP A2VDD

1
L8501 A2VDD/NC#AE20 C8508 C8509
1.5 mA ROB
1

1 DIS_PX 2 R8516 C8514 AE17 A2VDDQ_GPU R8505 2 1 0R2J-2-GP DY DY

AVDD_A2VDDQ
1

BLM18PG471SN1D-GP 249R2F-GP SCD1U10V2KX-5GP A2VDDQ/NC#AE17 SCD1U10V2KX-5GP SC1U6D3V2KX-GP

AC16

2
1

C8515 C8516 VREFG

DIS_PX DIS_PX AE19
SC1U6D3V2KX-GP

SCD1U10V2KX-5GP
1

C8505 A2VSSQ
DY DIS_PX DIS_PX DIS_PX
2

SC4D7U6D3V3KX-GP R8501
2

R2SET
AG13 1 ROB 2
2

R2SET/NC#AG13
715R2F-GP
M92-S2/M93-S3 M92-S2/M93-S3 0820
AE6 VGA_CRT_DDCCLK 50
PLL/CLOCK DDC1CLK
AE5 VGA_CRT_DDCDATA 50
DDC1DATA AVDD_A2VDDQ
AF14
DPLL_PVDD
AE14 AD2
1V_VGA_S0 DPLL_VDDC DPLL_PVSS AUX1P
AUX1N
AD4 (1.8V@2mA A2VDDQ)
(1.0V@125mA DPLL_VDDC) DDC/AUX
DIS_PX
1 2 AD14 AC11
L8506 BLM18PG471SN1D-GP DPLL_VDDC DDC2CLK
AC13

SC1U6D3V2KX-GP
1

1
DDC2DATA C8510 C8511
1

C8518 C8519 XTALIN AM28 AD13 0723 Add SMBUS DY DY

C8517 DY XTALOUT XTALIN AUX2P SCD1U10V2KX-5GP
DIS_PX DIS_PX AK28 AD11
SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

2
SC4D7U6D3V3KX-GP XTALOUT AUX2N
2

DDCCLK_AUX5P
AE16 AUXP PD 100K
AD16
R8510 1 20R2J-2-GP NC#AC22/XO_IN AC22
DDCDATA_AUX5N AUXN PU 100K
DY NC#AC22/XO_IN
R8511 1 DY 20R2J-2-GP NC#AB22/XO_IN2AB22 AC1 Draw on EDP circuit page
NC#AB22/XO_IN2 DDC6CLK
AC3
DDC6DATA
28 P2800_VGA_DXP
AD20 3D3V_VGA_S0
1

NC#AD20/DDCCLK_AUX3P 3D3V_VGA_S0 A2VDD

DIS_PX THERMAL NC#AC20/DDCDATA_AUX3N
AC20
C8523
SC2200P50V2KX-2GP T4 (3.3V@130mA A2VDD)
2

DPLUS R8509
28 P2800_VGA_DXN T2 1 2
DMINUS 0R0402-PADDIS_PX
2010/07/06 1D8V_VGA_S0 TSVDD
4
3

1
Schematics check list: L8504 DIS_PX TPAD14 TP8512 1 FAN_PWM_C R5 C8512 C8513

SC1U6D3V2KX-GP
TS_FDO RN8501 SCD1U10V2KX-5GP
A 1-M ohm resistor must be connected 1 2 (1.8V@20mA TSVDD) AD17
TSVDD DY DY
BLM15BD121SS1D-GP AC17 SRN4K7J-8-GP DIS_PX

2
between XTALIN and XTALOUT when a crystal is used. C8521 C8522 TSVSS
1

A ROBSON-GP-U A
2010/07/06 DIS_PXSC1U6D3V2KX-GP
DIS_PX
C8520 DY SCD1U10V2KX-5GP
71.ROBSO.M01 Q8503
1
2

SC4D7U6D3V3KX-GP
2

R8502
GPIO_VGA_04_CLK 1 6 SML1_CLK 6,27
1DIS_PX 2 Colay with Seymour-XT-S3
2 DIS_PX
5
Clock Input Configuraiton -GDDR3/DDR3 (71.SEYMR.M01) <Core Design>
1MR2F-GP
a) 27MHz crystal connected to XTALIN or XTALOUT or 3 4
X01 X8501
b) 27MHz (1.8V) oscillator connected to XTALIN or 2N7002KDW-GP Wistron Corporation
C8524 1 2XTALIN 1 4
c) 27MHz (3.3V) oscillator connected to XO_IN (Park, Madison, and Broadway only) 84.2N702.A3F 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2nd = 84.DM601.03F Taipei Hsien 221, Taiwan, R.O.C.
SC12P50V2JN-3GP
DIS_PX DIS_PX SML1_DATA 6,27 Title
DIS_PX GPIO_VGA_03_DATA
2 3 XTALOUT 1 2 GPU_DP/LVDS/CRT/GPIO(3/5)
80.30034.641 C8525 SC12P50V2JN-3GP Size Document Number Rev
2nd 80.30034.651 A2
A00
3rd 80.30034.681 XTAL-27MHZ-85-GP X01 Enrico 14 AMD
Date: Friday, April 22, 2011 Sheet 85 of 109
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO
1D5V_VGA_S0

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP SCD1U10V2KX-5GP

C8610

C8611

C8612
C8609
1

1
VGA1D 4 OF 7 1D8V_VGA_S0
DIS_PX DIS_PX DIS_PX DIS_PX PCIE_PVDD
MEM I/O

2
PCIE L8707
(1.8V@504mA PCIE_VDDR)
H13 AB23 1 DIS_PX 2

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP
VDDR1 PCIE_VDDR

C8613

C8615

C8616

C8637
H16 AC23

1
VDDR1 PCIE_VDDR
H19 AD24
VDDR1 PCIE_VDDR HCB2012KF-221T30-GP
J10
VDDR1 PCIE_VDDR
AE24 DIS_PX DIS_PX DIS_PX DIS_PX

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
J23 AE25

2
VDDR1 PCIE_VDDR

C8624

C8625

C8626

C8627
D J24 AE26 D

1
VDDR1 PCIE_VDDR
J9 AF25
VDDR1 PCIE_VDDR 1V_VGA_S0
DIS_PX DIS_PX DIS_PX DIS_PX K10
VDDR1 PCIE_VDDR
AG26
K23

2
VDDR1
K24
VDDR1 (1.0V@1920mA PCIE_VDDC)
K9 L23

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
VDDR1 PCIE_VDDC

C8628

C8629

C8630

C8631

C8632
L11 L24

1
VDDR1 PCIE_VDDC
L12 L25
VDDR1 PCIE_VDDC

SC10U6D3V5KX-1GP
L13 L26 DIS_PX DIS_PX DIS_PX DIS_PX DIS_PX

C8697
VDDR1 PCIE_VDDC

SC10U6D3V5KX-1GP
1

1
L20 M22

C8698

2
VDDR1 PCIE_VDDC
L21 N22
DIS_PX DIS_PX L22
VDDR1 PCIE_VDDC
N23
VDDR1 PCIE_VDDC

2
N24
PCIE_VDDC
R22
PCIE_VDDC
T22
1D8V_VGA_S0 VDDC_CT LEVEL PCIE_VDDC
U22
TRANSLATION PCIE_VDDC
20100920 X01: V22
PCIE_VDDC VGA_CORE
Reserve R8605 0402 0R for VDDC_CT. AA20
VDD_CT
AA21
VDD_CT
(1.8V@110mA VDD_CT) AB20 AA15

SC4D7U6D3V3KX-GP
R8605 VDD_CT CORE VDDC
1 2 AB21 N15
VDD_CT VDDC

C8699

C8652

C8653
0R0402-PADDIS_PX N17

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP SCD1U10V2KX-5GP
1

1
VDDC
M93-S3/M92-S2 R13

POWER
VDDC
DIS_PX DIS_PX DIS_PX VDDC
R16
AA17 R18

2
VDDR3 VDDC
AA18
VDDR3 I/O VDDC
Y21
AB17 T12
VDDR3 VDDC
AB18 T15

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
VDDR3 VDDC

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
C8646

C8649

C8665

C8669

C8647

C8670

C8645

C8648

C8672

C8675

C8671
3D3V_VGA_S0 T17

SC4D7U6D3V3KX-GP
VDDC
V12 T20

1
VDDR4/VDDR5 VDDC

C8601

C8666

C8667
Y12 U13

SC1U6D3V2KX-GP
DIS_PX DIS_PX DIS_PX

1
VDDR4 VDDC
U12
VDDR4/VDDR5 VDDC
U16 DIS_PX DIS_PX DIS_PX DIS_PX DIS_PX DIS_PX DIS_PX DIS_PX
DIS_PX DIS_PX DIS_PX U18

2
VDDC
2 AA11 V21

2
NC#AA11/VDDR4 VDDC
Y11 V15
DVCLK/VDDR4 VDDC
V17
VDDC

SC1U6D3V2KX-GP

C8677
V11 V20

C8676
NC#V11/VDDR5 VDDC

SC1U6D3V2KX-GP
C8679

C8680
U11 Y13

1
NC#U11 VDDC BIF_VDDC
Y16
SCD1U10V2KX-5GP VDDC
VDDC
Y18 DIS_PX DIS_PX DIS_PX DIS_PX
C8673

C8674
R21

SC1U6D3V2KX-GP

2
VDDC/BIF_VDDC
C U21 C
1

1
MEM CLK VDDC/BIF_VDDC
MPV18 DIS_PX DIS_PX L17 55mA in BACO mode
L8604 VDDRHA
(Park: 1.8V@75mA MPV18)

SC10U6D3V5KX-1GP
SC4D7U6D3V3KX-GP

SC4D7U6D3V5KX-3GP
2

C8654
1 DIS_PX 2 L16 ISOLATED

C8651
1

1
VSSRHA CORE I/O
C8604

C8603

C8690
SC1U6D3V2KX-GP

SCD1U10V2KX-5GP
1

BLM15BD121SS1D-GP MPV18 M13 DY DIS_PX

PLL VDDCI
68.00084.F81 DIS_PX DIS_PX DIS_PX M15

2
VDDCI
2ND = 68.00217.701 AM30 M16
2

MPV18 PCIE_PVDD VDDCI

M17
VDDCI
M18
L8 DIS_PX VDDCI
M20
1V_VGA_S0 SPV18 MPV18 VDDCI
M21
VDDCI
N20
VDDCI
(120mA SPV10) H7
SPV18
L8606
1 DIS_PX 2 SPV10 H8
BLM15BD121SS1D-GP SPV10 VGA_CORE
SC4D7U6D3V3KX-GP
C8634

C8635

C8636
68.00084.F81 J7 (GDDR3/DDR3 1.12V@4A VDDCI)
SC1U6D3V2KX-GP

SCD1U10V2KX-5GP
1

2ND = 68.00217.701
SPVSS A00

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
C8657

C8655

C8656

C8659

C8660
DIS_PX DIS_PX DIS_PX 2010/07/13 Modify:
BIF_VDDC Add C8601 for BIF_VDDC
2

1
BACK BIAS
SPV18 M11 DIS_PX DIS_PX DIS_PX DIS_PX DIS_PX
L8605 BBP#1
(1.8V@75mA SPV18) M12

2
BBP#2 DIS_PX
1 DIS_PX 2
SC4D7U6D3V3KX-GP
C8605

C8692

C8694

VGA_CORE

1
SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

C8617
1

BLM15BD121SS1D-GP

SC10U6D3V5KX-1GP
ROBSON-GP-U
68.00084.F81 DIS_PX DIS_PX DIS_PX
M11_M12

2
2ND = 68.00217.701 1ROB 2
71.ROBSO.M01

SC10U6D3V5KX-1GP
2

C8695
1
R8602 0R2J-2-GP
Colay with Seymour-XT-S3 DY
(71.SEYMR.M01)

2
2010/06/17_1 AO4468 MAX 3.1A
B B
Rds(on) = 1ow Rds(on) = 101~155mOhm 2010/07/08
VGS=0.7~1.5V VGS=+/-12V
3D3V_S5 3D3V_VGA_S0
BIF_VDDC U8601 U8603 VGA_CORE BIF_VDDC U8606 U8604 1V_VGA_S0
AO3400A-GP AO3400A-GP AO3418-GP AO3418-GP 1D5V_VGA_PWOK

10KR2J-3-GP

10KR2J-3-GP
R8607

R8606
BIF_VDDC_CORE BIF_VDDC_1V
S
DIS_PX
D D DIS_PX
S S DIS_PX D D DIS_PX S

1
3D3V_VGA_S0 5V_S0
3D3V_VGA_S0 5V_S0 84.03400.B37 84.03400.B37 84.03418.031 84.03418.031
G

DIS_PX DIS_PX
0629 Modify

2
Q8603
1

R8604 R8609 Q8603_G G X01

1

R8610 1KR2J-1-GP
R8603 1KR2J-1-GP
1KR2J-1-GP DY D 1D5V_VGA_PWOK 17,83
DY 1KR2J-1-GP DIS_PX DIS_PX DIS_PX
S
2

PX_EN# Q8604

C
2

R8608
MMBT3904-4-GP
PX_EN## 2N7002K-2-GP 84.2N702.J31
1D5V_VGA_S0 1 2 Q8604_B B DIS_PX
DIS_PX 0629 Modify 2nd = 84.07002.I31

E
2K2R2J-2-GP

SCD1U10V2KX-5GP
1
R8601 C8693 84.T3904.C11
1D5V_VGA_PWOK 1 DY 2 1D5V_VGA_PWOK_R DY 2ND = 84.03904.P11
0R2J-2-GP 3rd = 84.03904.L06

U8605 3D3V_VGA_S0
Q8602 Non-BACO= HIGH 2
1D5V_VGA_PWOK 1
B BACO = LOW
5 4 3
VCC
ADIS_PX
92 8209A_EN/DEM_VGA 2
4 1D5V_VGA_PWOK_R 5 DIS_PX2 PX_EN#
Y
3
GND PX_EN 8209A_EN/DEM_VGA1D5V_VGA_PWOK_R PX_EN# PX_EN##
PX_EN## 6 1
Q8601 74LVC1G08GW-1-GP
A 84 PX_EN G 73.01G08.L04 2N7002KDW-GP Non-BACO 0 1 1 0 1 A

DIS_PX
D 2ND = 73.7SZ08.DAH 84.2N702.A3F
BACO 1 0 0 1 0
S 2nd = 84.DM601.03F
2N7002K-2-GP PX_EN# = High, BIF_VDDC = 1V_VGA_S0 <Core Design>
84.2N702.J31 PX_EN## = High, BIF_VDDC = VGA_CORE
2nd = 84.07002.I31 Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
GPU_POWER(4/5)
Size Document Number Rev
A2
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 86 of 109
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO

1D8V_VGA_S0
1D8V_VGA_S0 DPEF_VDD18 DPAB_VDD18
VGA1G 7 OF 7 (1.8V@300mA DPAB_VDD18)
R8705 1 2 0R0603-PAD

SC4D7U6D3V3KX-GP
DP E/F POWER DP A/B POWER

C8713
R8707 1 2 0R0603-PAD

SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
DIS_PX

1
C8717

C8714

C8712
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
D D
DIS_PX DY DY DY

1
C8718

C8719
AG15 AE11

SC1U6D3V2KX-GP
DPE_VDD18 DPA_VDD18
DY DY DY AG16 AF11

2
DPE_VDD18 DPA_VDD18

2
DPEF_VDD10 DPAB_VDD10

1V_VGA_S0 AG20 AF6 1V_VGA_S0

DPE_VDD10 DPA_VDD10
AG21 DPE_VDD10 DPA_VDD10 AF7
(1.0V@220mA DPAB_VDD10)
VGA1E 5 OF 7 R8708 1 2 0R0603-PAD R8706 1 2 0R0603-PAD

SC4D7U6D3V3KX-GP
C8721
AG14 AE1

SCD1U10V2KX-5GP
DIS_PX DPE_VSSR DPA_VSSR DIS_PX

1
C8720

C8725

C8702

C8703

C8705
AH14 AE3

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP

SC10U6D3V5KX-1GP
DY DY DY DPE_VSSR DPA_VSSR DY
AM14 DPE_VSSR DPA_VSSR AG1 DY DY
AA27 A3 AM16 AG6

2
PCIE_VSS GND DPE_VSSR DPA_VSSR
AB24 PCIE_VSS GND A30 AM18 DPE_VSSR DPA_VSSR AH5
AB32 PCIE_VSS GND/EVDDQ AA13
AC24 AA16 DPEF_VDD18 DPAB_VDD18
PCIE_VSS GND
AC26 PCIE_VSS GND AB10
AC27 PCIE_VSS GND/EVDDQ AB15 AF16 DPF_VDD18 DPB_VDD18 AE13
AD25 PCIE_VSS GND AB6 AG17 DPF_VDD18 DPB_VDD18 AF13
AD32 PCIE_VSS GND AC9
AE27 AD6 DPEF_VDD10 DPAB_VDD10
PCIE_VSS GND
AF32 PCIE_VSS GND AD8
AG27 PCIE_VSS GND AE7 AF22 DPF_VDD10 DPB_VDD10 AF8
AH32 PCIE_VSS GND AG12 AG22 DPF_VDD10 DPB_VDD10 AF9
K28 PCIE_VSS GND AH10
K32 PCIE_VSS GND AH28
L27 PCIE_VSS GND B10 AF23 DPF_VSSR DPB_VSSR AF10
M32 PCIE_VSS GND B12 2010/07/09 N11 and N12: in Seymour is NC AG23 DPF_VSSR DPB_VSSR AG9
C N25 B14 AM20 AH8 C
PCIE_VSS GND DPF_VSSR DPB_VSSR
N27 PCIE_VSS GND B16 AM22 DPF_VSSR DPB_VSSR AM6
P25 PCIE_VSS GND B18 AM24 DPF_VSSR DIS_PX DPB_VSSR AM8
P32 PCIE_VSS GND B20
R27 B22 N11_GND 1ROB 2
PCIE_VSS GND R8703
T25 PCIE_VSS GND B24
T32 B26 R8702 0R2J-2-GP DIS_PXDPCD_CALR 150R2F-1-GP
PCIE_VSS GND N12_GND
U25 PCIE_VSS GND B6 1ROB 2 1 2 AF17 DPEF_CALR DPAB_CALR AE10 DPAB_CALR 1DIS_PX 2
U27 B8 R8701 150R2F-1-GP
PCIE_VSS GND R8704 0R2J-2-GP DPEF_VDD18 DPAB_VDD18
V32 PCIE_VSS GND C1
W25 PCIE_VSS GND C32
W26 E28 AG18 DP PLL POWER AG8
PCIE_VSS GND DPE_PVDD DPA_PVDD
W27 PCIE_VSS GND F10 AF19 DPE_PVSS DPA_PVSS AG7
Y25 F12 DPEF_VDD18 DPAB_VDD18
PCIE_VSS GND
Y32 PCIE_VSS GND F14
GND F16
GND F18 AG19 DPF_PVDD DPB_PVDD AG10
GND F2 AF20 DPF_PVSS DPB_PVSS AG11
GND F20
M6 GND GND F22
N11_GND N11 F24
N12_GND GND GND ROBSON-GP-U
N12 F26
N13
GND
GND
GND
GND F6 71.ROBSO.M01
N16 F8
N18
N21
GND
GND GND GND
GND G10
G27
Colay with Seymour-XT-S3
P6
GND
GND
GND
GND G31 (71.SEYMR.M01)
P9 GND GND G8
R12 GND GND H14
B B
R15 GND GND H17
R17 GND GND H2
R20 GND GND H20
T13 GND GND H6
T16 GND GND J27
T18 GND GND J31
T21 GND GND K11
T6 GND GND K2
U15 GND GND K22
U17 GND GND K6
U20 GND GND T11 1D8V_VGA_S0
U9 GND DIS_PX GND R11
V13 GND
V16 GND
V18 GND (1.8V@150mA DPB_VDD18)
Y10 GND
Y15 GND
1

1
Y17 A32 VSS_MECH1 1 TP8701TPAD14 C8709 C8710 C8711

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP

GND VSS_MECH
Y20 GND VSS_MECH AM1 VSS_MECH2 1 TP8702TPAD14 DY DY DY
AM32 VSS_MECH3 1 TP8703TPAD14
2

2
VSS_MECH

ROBSON-GP-U

A
71.ROBSO.M01 <Core Design>
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU_DPPWR/GND(5/5)
Size Document Number Rev
A3 Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 87 of 109

5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO
1D5V_VGA_S0 1D5V_VGA_S0
VRAM1 VRAM2
MDA[0..31] 84 MDA[0..31] 84
K8 E3 MDA3 K8 E3 MDA27
VDD DQL0 MDA7 VDD DQL0 MDA29
K2 VDD DQL1 F7 K2 VDD DQL1 F7
N1 F2 MDA1 N1 F2 MDA31
VDD DQL2 MDA4 VDD DQL2 MDA25
R9 VDD DQL3 F8 R9 VDD DQL3 F8
B2 H3 MDA2 B2 H3 MDA28
VDD DQL4 MDA6 VDD DQL4 MDA24
D D9 VDD DQL5 H8 D9 VDD DQL5 H8 D
G7 G2 MDA0 G7 G2 MDA30
VDD DQL6 MDA5 VDD DQL6 MDA26
R1 VDD DQL7 H7 R1 VDD DQL7 H7
N9 VDD N9 VDD
D7 MDA21 D7 MDA12
DQU0 MDA19 DQU0 MDA10
A8 VDDQ DQU1 C3 A8 VDDQ DQU1 C3
A1 C8 MDA23 A1 C8 MDA13
VDDQ DQU2 MDA18 VDDQ DQU2 MDA11
C1 VDDQ DQU3 C2 C1 VDDQ DQU3 C2
C9 A7 MDA20 C9 A7 MDA8
VDDQ DQU4 MDA17 VDDQ DQU4 MDA15
D2 VDDQ DQU5 A2 D2 VDDQ DQU5 A2
E9 B8 MDA22 E9 B8 MDA9
VDDQ DQU6 MDA16 VDDQ DQU6 MDA14
F1 VDDQ DQU7 A3 F1 VDDQ DQU7 A3
H9 VDDQ H9 VDDQ
H2 VDDQ DQSU C7 QSAP_2 84 H2 VDDQ DQSU C7 QSAP_1 84
DQSU# B7 QSAN_2 84 DQSU# B7 QSAN_1 84
VRAM1_VREF H1 VRAM1_VREF H1
VRAM2_VREF VREFDQ VRAM2_VREF VREFDQ
M8 VREFCA DQSL F3 QSAP_0 84 M8 VREFCA DQSL F3 QSAP_3 84
1 2 VRAM_ZQ1 L8 G3 QSAN_0 84 1 2 VRAM_ZQ2 L8 G3 QSAN_3 84
R8801 243R2F-2-GP ZQ DQSL# R8802 243R2F-2-GP ZQ DQSL#
DIS_PX DIS_PX
ODT K1 ODTA0 84 ODT K1 ODTA0 84
84,89 MAA0 N3 A0 84,89 MAA0 N3 A0
84,89 MAA1 P7 A1 84,89 MAA1 P7 A1
84,89 MAA2 P3 A2 CS# L2 CSA0#_0 84 84,89 MAA2 P3 A2 CS# L2 CSA0#_0 84
84,89 MAA3 N2 A3 RESET# T2 MEM_RST 84,89 84,89 MAA3 N2 A3 RESET# T2 MEM_RST 84,89
84,89 MAA4 P8 A4 84,89 MAA4 P8 A4
84,89 MAA5 P2 A5 84,89 MAA5 P2 A5
84,89 MAA6 R8 A6 NC#T7 T7 84,89 MAA6 R8 A6 NC#T7 T7
84,89 MAA7 R2 A7 NC#L9 L9 84,89 MAA7 R2 A7 NC#L9 L9
84,89 MAA8 T8 A8 NC#L1 L1 84,89 MAA8 T8 A8 NC#L1 L1
C R3 J9 R3 J9 C
84,89 MAA9 A9 NC#J9 84,89 MAA9 A9 NC#J9
84,89 MAA10 L7 A10/AP NC#J1 J1 84,89 MAA10 L7 A10/AP NC#J1 J1
84,89 MAA11 R7 A11 84,89 MAA11 R7 A11
84,89 MAA12 N7 A12/BC# 84,89 MAA12 N7 A12/BC#
84,89 MAA13 T3 A13 VSS J8 84,89 MAA13 T3 A13 VSS J8
M7 NC#M7 VSS M1 M7 NC#M7 VSS M1
VSS M9 VSS M9
VSS J2 VSS J2
84,89 A_BA0 M2 BA0 VSS P9 84,89 A_BA0 M2 BA0 VSS P9
84,89 A_BA1 N8 BA1 VSS G8 84,89 A_BA1 N8 BA1 VSS G8
84,89 A_BA2 M3 BA2 VSS B3 84,89 A_BA2 M3 BA2 VSS B3
VSS T1 VSS T1
VSS A9 VSS A9
84 CLKA0 J7 CK VSS T9 84 CLKA0 J7 CK VSS T9
84 CLKA0# K7 CK# VSS E1 84 CLKA0# K7 CK# VSS E1
VSS P1 VSS P1
84 CKEA0 K9 CKE 84 CKEA0 K9 CKE
1

R8804 R8803 G1 G1
56R2F-1-GP 56R2F-1-GP VSSQ VSSQ
VSSQ F9 VSSQ F9
DIS_PX DIS_PX 84 DQMA2 D3 DMU VSSQ E8 84 DQMA1 D3 DMU VSSQ E8
84 DQMA0 E7 DML VSSQ E2 84 DQMA3 E7 DML VSSQ E2
D8 D8
2

VSSQ VSSQ
VSSQ D1 VSSQ D1
GPU_CLKA0_T 84 W EA0# L3 B9 84 W EA0# L3 B9
WE# VSSQ WE# VSSQ
84 CASA0# K3 CAS# VSSQ B1 84 CASA0# K3 CAS# VSSQ B1
J3 G9 J3 G9
84 RASA0# RAS# VSSQ 84 RASA0# RAS# DIS_PX VSSQ
1

C8802 DIS_PX
SCD01U16V2KX-3GP DIS_PX
K4W 1G1646E-HC12-GP K4W 1G1646E-HC12-GP
2

B B

1D5V_VGA_S0
1D5V_VGA_S0

1
1

R8805
DIS_PXR8808
2K1R2F-GP
DIS_PX
2K1R2F-GP

2
2

VRAM2_VREF
VRAM1_VREF

1
C8805
1

C8803 R8807 SCD1U10V2KX-5GP C8807

2K1R2F-GP
DIS_PXR8806 DIS_PX SCD1U10V2KX-5GPDIS_PX
C8806 DIS_PX DIS_PX DIS_PXSC1000P50V3JN-GP-U

2
2K1R2F-GP SC1000P50V3JN-GP-U
2

2
2

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

GPU-VRAM1,2 (1/4) Rev
A3 Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 88 of 109
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO 1D5V_VGA_S0

VRAM3
1D5V_VGA_S0
VRAM4
MDA[32..63] 84 MDA[32..63] 84
K8 E3 MDA35 K8 E3 MDA61
VDD DQL0 VDD DQL0
C8902

C8906

C8909

C8908

C8911

C8912

C8919

C8914
SC1U6D3V2KX-GP K2 F7 MDA39 K2 F7 MDA59

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
C8910

C8913

C8917

C8923

C8915
VDD DQL1 VDD DQL1

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
C8920
N1 F2 MDA33 N1 F2 MDA62
1 VDD DQL2 VDD DQL2

1
R9 F8 MDA36 R9 F8 MDA57
DIS_PX DIS_PX VDD DQL3 MDA34 DIS_PX DIS_PX VDD DQL3 MDA63
DIS_PXDIS_PXDIS_PX DIS_PX
DIS_PX DIS_PX B2 VDD DQL4 H3
MDA37
DIS_PX DIS_PX DIS_PXDIS_PX B2 VDD DQL4 H3
MDA56
D9 H8 D9 H8
2

2
VDD DQL5 MDA32 VDD DQL5 MDA60
G7 VDD DQL6 G2 G7 VDD DQL6 G2
R1 H7 MDA38 R1 H7 MDA58
VDD DQL7 VDD DQL7
N9 VDD N9 VDD
D D7 MDA45 D7 MDA52 D
DQU0 MDA40 DQU0 MDA53
A8 VDDQ DQU1 C3 A8 VDDQ DQU1 C3

C8905

C8907

C8916

C8918
A1 C8 MDA47 A1 C8 MDA49

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
VDDQ DQU2 MDA41 VDDQ DQU2 MDA54
C1 VDDQ DQU3 C2 C1 VDDQ DQU3 C2

1
C9 A7 MDA44 C9 A7 MDA48
VDDQ DQU4 MDA43 VDDQ DQU4 MDA55
DIS_PX DIS_PX D2 VDDQ DQU5 A2
MDA46
DIS_PX DIS_PX D2 VDDQ DQU5 A2
MDA50
E9 B8 E9 B8

2
VDDQ DQU6 MDA42 VDDQ DQU6 MDA51
F1 VDDQ DQU7 A3 F1 VDDQ DQU7 A3
H9 VDDQ H9 VDDQ
H2 VDDQ DQSU C7 QSAP_5 84 H2 VDDQ DQSU C7 QSAP_6 84
DQSU# B7 QSAN_5 84 DQSU# B7 QSAN_6 84
VRAM3_VREF H1 VRAM3_VREF H1
VRAM4_VREF VREFDQ VRAM4_VREF VREFDQ
M8 VREFCA DQSL F3 QSAP_4 84 M8 VREFCA DQSL F3 QSAP_7 84
1 2 VRAM_ZQ3 L8 G3 QSAN_4 84 1 2 VRAM_ZQ4 L8 G3 QSAN_7 84
R8903 243R2F-2-GP ZQ DQSL# R8904 243R2F-2-GP ZQ DQSL#
DIS_PX DIS_PX
ODT K1 ODTA1 84 ODT K1 ODTA1 84
84,88 MAA0 N3 A0 84,88 MAA0 N3 A0
84,88 MAA1 P7 A1 84,88 MAA1 P7 A1
84,88 MAA2 P3 A2 CS# L2 CSA1#_0 84 84,88 MAA2 P3 A2 CS# L2 CSA1#_0 84
84,88 MAA3 N2 A3 RESET# T2 MEM_RST 84,88 84,88 MAA3 N2 A3 RESET# T2 MEM_RST 84,88
84,88 MAA4 P8 A4 84,88 MAA4 P8 A4
84,88 MAA5 P2 A5 84,88 MAA5 P2 A5
84,88 MAA6 R8 A6 NC#T7 T7 84,88 MAA6 R8 A6 NC#T7 T7
84,88 MAA7 R2 A7 NC#L9 L9 84,88 MAA7 R2 A7 NC#L9 L9
84,88 MAA8 T8 A8 NC#L1 L1 84,88 MAA8 T8 A8 NC#L1 L1
84,88 MAA9 R3 A9 NC#J9 J9 84,88 MAA9 R3 A9 NC#J9 J9
84,88 MAA10 L7 A10/AP NC#J1 J1 84,88 MAA10 L7 A10/AP NC#J1 J1
84,88 MAA11 R7 A11 84,88 MAA11 R7 A11
84,88 MAA12 N7 A12/BC# 84,88 MAA12 N7 A12/BC#
C T3 J8 T3 J8 C
84,88 MAA13 A13 VSS 84,88 MAA13 A13 VSS
M7 NC#M7 VSS M1 M7 NC#M7 VSS M1
VSS M9 VSS M9
VSS J2 VSS J2
84,88 A_BA0 M2 BA0 VSS P9 84,88 A_BA0 M2 BA0 VSS P9
84,88 A_BA1 N8 BA1 VSS G8 84,88 A_BA1 N8 BA1 VSS G8
84,88 A_BA2 M3 BA2 VSS B3 84,88 A_BA2 M3 BA2 VSS B3
VSS T1 VSS T1
VSS A9 VSS A9
84 CLKA1 J7 CK VSS T9 84 CLKA1 J7 CK VSS T9
84 CLKA1# K7 CK# VSS E1 84 CLKA1# K7 CK# VSS E1
VSS P1 VSS P1
84 CKEA1 K9 CKE 84 CKEA1 K9 CKE
1

R8907 R8908 G1 G1
56R2F-1-GP 56R2F-1-GP VSSQ VSSQ
VSSQ F9 VSSQ F9
DIS_PX DIS_PX 84 DQMA5 D3 DMU VSSQ E8 84 DQMA6 D3 DMU VSSQ E8
84 DQMA4 E7 DML VSSQ E2 84 DQMA7 E7 DML VSSQ E2
D8 D8
2

VSSQ VSSQ
VSSQ D1 VSSQ D1
GPU_CLKA1_T 84 W EA1# L3 B9 84 W EA1# L3 B9
WE# VSSQ WE# VSSQ
84 CASA1# K3 CAS# VSSQ B1 84 CASA1# K3 CAS# VSSQ B1
84 RASA1# J3 RAS# VSSQ G9 84 RASA1# J3 RAS# VSSQ G9
1

C8903 DIS_PX
SCD01U16V2KX-3GP DIS_PX DIS_PX
K4W 1G1646E-HC12-GP K4W 1G1646E-HC12-GP
2

B B

1D5V_VGA_S0
1D5V_VGA_S0

1
1

R8905
R8901 2K1R2F-GP
2K1R2F-GP
DIS_PX
DIS_PX

2
2

VRAM4_VREF
VRAM3_VREF

1
R8906 C8904
1

R8902 C8901 2K1R2F-GP SCD1U10V2KX-5GP C8925

2K1R2F-GP SCD1U10V2KX-5GP C8924 DIS_PX DIS_PX DIS_PXSC1000P50V3JN-GP-U

2
SC1000P50V3JN-GP-U
DIS_PX DIS_PX DIS_PX
2

2
2

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

GPU-VRAM3,4 (2/4) Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 89 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM5,6 (3/4)
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 90 of 109
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM7,8 (4/4)
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 91 of 109
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_VGACORE

D D

VGA_CORE VGA_CORE_PWR VGA_CORE

PG9202 PG9203
1 2 1 2
DCBATOUT PWR_DCBATOUT_VGA_CORE GAP-CLOSE-PWR GAP-CLOSE-PWR
PG9205 PG9206
PG9204 1 2 1 2
1 2
GAP-CLOSE-PWR GAP-CLOSE-PWR
GAP-CLOSE-PWR PG9208 PG9209
PG9207 1 2 1 2
1 2
GAP-CLOSE-PWR GAP-CLOSE-PWR
GAP-CLOSE-PWR PG9211 PG9214
PG9210 1 2 1 2
1 2
GAP-CLOSE-PWR GAP-CLOSE-PWR
GAP-CLOSE-PWR PG9201 PG9217
PG9213 1 2 1 2
1 2
GAP-CLOSE-PWR GAP-CLOSE-PWR
GAP-CLOSE-PWR PG9216 PG9220
PG9215 1 2 1 2
1 2 PWR_DCBATOUT_VGA_CORE
1128-SB GAP-CLOSE-PWR GAP-CLOSE-PWR
GAP-CLOSE-PWR PG9219 PG9212
PG9218 1 2 1 2
1 2 5V_S5

SCD1U25V2KX-GP
PC9205
PC9202 PC9203 PC9204 GAP-CLOSE-PWR GAP-CLOSE-PWR
DY

2
GAP-CLOSE-PWR

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP
F
r
e
q
=
3
6
0
K
H
z
DIS_PX DIS_PX DIS_PX

1
1128-SB
1

5
6
7
8
PC9206 DIS_PX

D
D
D
D
PU9202
SC1U10V2KX-1GP Design Current =12.9A

SIR172DP-T1-GE3-GP
2

C C
PR9202 DIS_PX 19.03A<OCP<22.5A
PWR_VGA_CORE_TON 1 DIS_PX2

G
S
S
S
200KR2F-L-2-GP

4
3
2
1
PU9201 PR9203
2D2R3-1-U-GP PC9201 1128-SB
PR9204 16 13 PWR_VGA_CORE_BOOT
2 1PWR_VGA_CORE_BOOT_C
1 2 VGA_CORE_PWR
2 DIS_PX1 9
TON BOOT DIS_PX DIS_PX PL9201
VDDP PWR_VGA_CORE_UGATE SCD1U25V3KX-GP
10R2F-L-GP 12
PWR_VGA_CORE_VDD 2 UGATE PWR_VGA_CORE_PHASE
VDD PHASE
11 1 DIS_PX2

GAP-CLOSE-PWR-3-GP
8 PWR_VGA_CORE_LGATE 0825
LGATE

1
COIL-D82UH-2-GP

PG9221
PWR_VGA_CORE_PGOOD 4 7 0824 PC9207 PT9201 PT9202 PT9203

1
PWR_VGA_CORE_CS PGOOD G0 PWR_VGA_CORE_FB PWRCNTL_0 85
10 3

SCD1U10V2KX-4GP
5
6
7
8
CS FB
14 PWRCNTL_1 85 DIS_PX DIS_PX DIS_PX DY
1

1
D
D
D
D
G1

SE330U2VDM-L-GP

SE330U2VDM-L-GP

SE330U2VDM-L-GP
5 PWR_VGA_CORE_D1 PU9203

2
PR9205
1

D1
DIS_PX
8209A_EN/DEM_VGA
11K3R2F-2-GP 15
EM/DEM D0
6 PWR_VGA_CORE_D0
DYPR9206

SIR460DP-T1-GE3-GP
PC9208 PWR_VGA_CORE_VOUT 1128-SB
SC1U10V2KX-1GP PWR_VGA_CORE_VOUT
DIS_PX 2D2R5F-2-GP
DIS_PX 17 1
2

GND VOUT
2

2
DIS_PX

S
S
S
G

1
0316-SC RT8208BGQW-GP

4
3
2
1

1
PR9201 DIS_PX
DY PC9213
SC560P50V-GP
10R2J-2-GP

2
I/P cap: 10U 25V K0805 X5R/ 78.10622.51L
Inductor: 0.82uH PCMC063T-R82MN Cyntec 6.7mohm/8.0mohm Isat =24Arms 68.R8210.10V
O/P cap: 220U 2V EEFCX0D221R 15mOhm 2.7Arms Panasonic/79.22719.20L
H/S: SIR712DP/ POWERPAK/10.3mOhm/12.4mOhm@4.5Vgs/ 84.00172.037
L/S: SiR460DP/ POWERPAK/ 4.9mOhm/ 6.1mohm@4.5Vgs/ 84.00460.037

2
PC9209 PC9210
PR9218

1
10KR2F-2-GP
DY DY

SC10P50V2JN-4GP

SC10P50V2JN-4GP
3D3V_VGA_S0
DIS_PX

2
1
1

PR9208 10KR2F-2-GP
1 2 PR9209
3D3V_VGA_S0 10KR2J-3-GP PWR_VGA_CORE_FB
DIS_PX DIS_PX
B B
2

PD9201 PWR_VGA_CORE_PGOOD 2 PR9212 1

DGPU_PWROK 93

1
8209A_EN/DEM_VGA 0R0402-PAD PR9210 PR9213
17,93 PE_GPIO1 2 DY 1
8209A_EN/DEM_VGA 86 PR9211
DIS_PX

150KR2F-L-GP

49K9R2F-L-GP
1

DIS_PX

75KR2F-GP
CH551H-30PT-GP PC9211 DIS_PX
DY SCD1U10V2KX-4GP PC9212
SC100P50V2JN-3GP
DIS_PX
2

2
1GND_SENSE_1
0723 Delete sense function
PWR_VGA_CORE_D1

PWR_VGA_CORE_D0

PR9216
DIS_PX 10R2J-2-GP
0825

2
Robson-XT Seymour-XT
X01
PWR_VGA_CORE_D1 PWR_VGA_CORE_D0 VGA_CORE_PWR PWR_VGA_CORE_D1 PWR_VGA_CORE_D0 VGA_CORE_PWR

L L 1.12V L L 1.05V
L H N/A L H 1V
H L 0.95V H L N/A
A A
H H 0.9V H H 0.9V

Vout=0.75V*(R1+R2)/R2 Vout=0.75V*(R1+R2)/R2
<Core Design>
For ROBSON For Seymour
PR9210=44.2K(64.44225.6DL) PR9210=150K(64.15035.6DL) Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
PR9211=150K(64.15035.6DL) PR9211=75K(64.75025.6DL) Taipei Hsien 221, Taiwan, R.O.C.

Title

RT8208B_+VGA_CORE
Size Document Number Rev
A2
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 92 of 109
5 4

www.bblianmeng.com 3 2 1
 5 4 3 2 1

AO4468 MAX 11.6A

+3VS to 3.3V_DELAY Transfer Rds(on) = 11~14mOhm
3D3V_S5 3D3V_VGA_S0

VGS=+/-20V 1D8V_VGA_S0_PG

10KR2J-3-GP

10KR2J-3-GP
1D8V_VGA_S0 1D8V_S0

PR9338

PR9339
1D8V_VGA_S0
PU9306

1
8 D S 1
7 D S 2
1 DY PR9301
2 6 D DIS_PXS 3 DIS_PX DIS_PX

1
0R2J-2-GP 5 D G 4 PC9331 0629 Modify

1
DMP2130L-7-GP 3D3V_VGA_S0 PC9330DIS_PX DIS_PX

2
PQ9302 SC10U6D3V3MX-GP AO4468-GP SC10U6D3V3MX-GP PQ9309

2
3D3V_S0 S 84.04468.037 PQ9310_C G

2
DIS_PX D 2nd = 84.08882.037

D
84.02130.031 DIS_PX D 1D8V_S0_VGA_PG 83

G
2ND = 84.03413.A31 3D3V_VGA discharge PQ9310
D PR9303 MMBT3904-4-GP S D

G
100KR2J-1-GP 3D3V_AUX_S5 0629 Modify
DIS_PX

C
DIS_PX 2N7002K-2-GP
0504 chaomin 1 2 1D8V_VGA_EN# 1D8V_ENABLE_RC
1D8V_VGA_S0 1 PR9340 2 PQ9310_B BDIS_PX
2

3.3V_ALW_1 PR9334 100KR2J-1-GP

PR9333 DIS_PX 84.2N702.J31
D G S 2nd = 84.07002.I31

E
2K2R2J-2-GP

SCD1U10V2KX-5GP
2nd = 84.DM601.03F 2 1

1
84.2N702.A3F DIS_PX PC9302 84.T3904.C11

4
PR9305 DY 2ND = 84.03904.P11

1
2N7002KDW-GP PQ9306 15V_S5 20KR2F-L-GP
DIS_PX 470R2J-2-GP 3rd = 84.03904.L06

2
PQ9303 2N7002KDW-GP DIS_PX DIS_PX PC9329
DIS_PX SCD01U50V2KX-1GP
84.2N702.A3F

2
1

2
PR9320
2nd = 84.DM601.03F
9025_PWRGD_VGA_1V 1 2 PWR_1D8V_VGA_EN S G D PR9335
DIS_PX 100KR2J-1-GP
3.3V_RUN_VGA_1 0R0402-PAD
PC9323
DIS_PX

SCD1U10V2KX-5GP

1
DY

2
1D8V_ENABLE
17,92 PE_GPIO1

PD9304
17,92 PE_GPIO1 2 DY 1
CH551H-30PT-GP
Different To Intel, AMD Is High Active

PE_GPIO1
PE_GPIO0
C dGPU mode H H C

IGPU L L

IGPU with BACO H H

0628 Modify:
change low Rds(on) MOSFET Change PU9305 part number to 84.04468.037 same as U3601&U3602.

1D5V_VGA_S0 1D5V_S3
DIS_PX
1D5V_VGA_S0

5V_S5 PU9303
AO4468 MAX 11.6A
8 D S 1
Park_Madison Does Not Support BACO, So follow Old Sequence Rds(on) = 11~14mOhm 7 D S 2 0629 Modify:
0603 VGS=+/-20V 6 D S 3 Add PC9332 10uF 0603.
1

1
Seymour_Whistler_Robson Support BACO, So Change Sequence 5 D G 4 PC9314

1D5V_ENABLE_RC
PR9309 PC9301
3D3V_VGA_S0 should ramp-up before VGA_Core 1D5V_S3 DIS_PX SC10U6D3V3MX-GP
0R0402-PAD DIS_PX AO4468-GP

2
B 84.04468.037 B
DIS_PX

SC10U6D3V3MX-GP
2
VGA_Coreshould ramp-up before 1V_VGA_S0 2nd = 84.08882.037
2

1V_VGA_S0 should ramp up before 1D8V_VGA_S0

1

PC9308
1

SC10U6D3V5MX-3GP PC9309
so 1V_VGA_S0 EN have to fine tune RC delay
SC1U6D3V2KX-GP

DIS_PX
2

PR9315
PWR_1V_VGA_VDD

after VGA_Core DIS_PX Iomax>1.2A Park_Madison Does Not Support BACO, So follow Old Sequence
RT9025 for 1V_VGA_S0
2

Seymour_Whistler_Robson Support BACO, So Change Sequence 1 2

DIS_PX PG9303 Discharge Circuit

1
20KR2F-L-GP
1 2 0802 Rename to 1D5V_VGA_EN DIS_PX
1 PR9310 2 1V_VGA_PWR 1V_VGA_S0 3D3V_AUX_S5 PC9315 1D5V_VGA_S0
3D3V_VGA_S0
0R0402-PAD GAP-CLOSE-PWR SCD01U50V2KX-1GP
DIS_PX
Vo(cal.)=1V

2
PG9304 1 2 1D5V_VGA_EN#
0629 Modify: PWR_1V_VGA_EN PU9302 1 2 PR9316 100KR2J-1-GP

1
Reserved PD9302 connect DGPU_PWR_EN to D G S 0721
PWR_1V_EN for power down sequence.
DIS_PX
5 GAP-CLOSE-PWR PR9317
1

PC9310 4
NC#5
6 X01 PC9311 PC9312 PC9313 470R2J-2-GP
1

4
VDD VOUT
SCD1U10V2KX-5GP

3D3V_VGA_S0 PR9311 0629 Modify:

VINDIS_PX ADJ
PD9301 3 7
DIS_PX DY DY DIS_PX
SC100P50V2JN-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

10KR2F-2-GP DIS_PX Reserved PD9301 connect DGPU_PWR_EN to PQ9304 15V_S5

2 DY 1
DY 2 8 0825
2

DIS_1D5V_VGA_S02
EN GND PWR_1D5V_EN for power down sequence.
1 9 2N7002KDW-GP 0802 Rename to 1D5V_VGA_EN
2

17,92 PE_GPIO1
1

CH551H-30PT-GP PGOOD GND

84.2N702.A3F
2

PR9312

2
2K2R2J-2-GP RT9025-25ZSP-GP PWR_1V_ADJ PD9303 2nd = 84.DM601.03F 2N7002K-2-GP
DIS_PX 17,92 PE_GPIO1 2 DY 1 DIS_PX S G D PR9319
DIS_PX
1

100KR2J-1-GP G 1D5V_VGA_EN#
2

PR9314 CH551H-30PT-GP
PR9313
9025_PWRGD_VGA_1V 1 2 PWR_1V_VGA_PWRGD DIS_PX 39KR2F-GP D

1
PR9318
1 2 1D5V_VGA_EN
0R0402-PAD 92 DGPU_PWROK
DIS_PX S
2

0R0402-PAD
DIS_PX 1D5V_ENABLE
DIS_PX 0802 Rename to 1D5V_VGA_EN PQ9301
0628 Modify: 84.2N702.J31
Simplify 1D5V_ENABLE control circuit.
Rmoved PQ9305,PR9327,PR9328 PQ9306.
2nd = 84.07002.I31

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
DISCRETE VGA POWER
Size Document Number Rev
A2 Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 93 of 109

5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO

D D

C C

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

LVDS_Switch
Size Document Number Rev
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 94 of 109

5 4 3 2 1
 5 4 3 2 1

D D

(Blanking)

<Core Des ign>

Wistron Corporation
21F, 88, Sec.1, Hs in Tai Wu Rd., Hs ichih,
Taipei Hs ien 221, Taiwan, R.O.C.

Title

Size Docum ent Num ber

Reserved Rev
A0
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 95 of 109

C C

B B

A A

5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Touch Panel
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 96 of 109
5 4 3 2 1
 A

0824 EMI Request

CPU BRACKET
EC9704

DCBATOUT
HT85BE85R29-U-5-GP
H1
SCD1U25V2KX-GP

DY
2 1

HOLE256R142-GP
H8
1
1 EC9705

DCBATOUT
EC9724
SCD1U25V2KX-GP
SCD1U25V2KX-GP

EC9723 SCD1U25V2KX-GP

EC9722 SCD1U25V2KX-GP

VGA_CORE
2 1

DY
2 1

DY
1 DY 2

1 DY 2
EC9706
SCD1U25V2KX-GP
2 1

DY

3D3V_S0
EC9707

HOLE256R142-GP HOLE256R126-1-GP
H9
SCD1U25V2KX-GP
5

5
1 2 1 EC9701
SCD1U25V2KX-GP

HOLE256R115-GP
H2

5V_S5
EC9708
1 SCD1U25V2KX-GP

DY DY

DY
2 1 2 1
EC9709

X01 EMI 12/13

SCD1U25V2KX-GP EC9725

X02
2 1 SCD1U25V2KX-GP
2 1

DY
EC9710
X02

H10
1 SCD1U25V2KX-GP
2 1
EC9711
SPRING-62-GP
SPR3

1 SCD1U25V2KX-GP

DY
2 1

X01 EMI 12/13

EC9732

HT85BE85R29-U-5-GP
H6
SCD1U25V2KX-GP
1 2 1 EC9712 EC9702
SCD1U25V2KX-GP SCD1U25V2KX-GP

3D3V_S0

5V_S0
EC9734
SCD1U25V2KX-GP 1 2 2 1

DY

DY
2 1 EC9713
SCD1U25V2KX-GP
EC9738
2 1

DY
SCD1U25V2KX-GP
SPRING-58-GP
SPR4

1 2 1 EC9714

Stand Off
SCD1U25V2KX-GP EC9703
EC9735
SCD1U25V2KX-GP
HT85BE85R29-U-5-GPHT85BE85R29-U-5-GP
H4

ODD_PW R_5V
SCD1U25V2KX-GP 2 EC9720
1

DY DY
2 1
1 2 1

STF237R117H83-1-GP
H11

DY
1 SCD1U25V2KX-GP
EC9737
SCD1U25V2KX-GP 2 1

DY
2 1
EC9733
SCD1U25V2KX-GP
2 1

A00
EC9736
4

4
H5

SCD1U25V2KX-GP EC9721
SPRING-58-GP
SPR1

STF217R113H162-GP
H12

1D5V_VGA_S0
1 2 1 SCD1U25V2KX-GP EC9718
1
1 2 1

DY

1D5V_S3
EC9739 SC47P50V2JN-3GP
SCD1U25V2KX-GP 2 1
2 1 EC9726
EC9719
EC9748 SCD1U25V2KX-GP

DY
2 1 SC47P50V2JN-3GP
SCD1U25V2KX-GP
2 1 2 1
EC9749
EC9715
SCD1U25V2KX-GP

X01 EMI 12/13

2 1 SCD1U25V2KX-GP

DY
2 1
SPRING-58-GP
SPR2

1 EC9740 EC9716
HT85B95X975R29-S-GP
H7

SCD1U25V2KX-GP SC47P50V2JN-3GP

DY
2 1
1 2 1
EC9743
SCD1U25V2KX-GP EC9717
SCD1U25V2KX-GP
2 1 2 1

DY
EC9746
SCD1U25V2KX-GP
2 1
EC9742
SCD1U25V2KX-GP
2 1
HT85BE85R29-U-5-GP
H3

1 EC9745
SCD1U25V2KX-GP
DY
2 1
EC9741
SCD1U25V2KX-GP
2 1

X01 EMI 12/13

EC9744
SCD1U25V2KX-GP
2 1
DY DY
3

3
EC9747
SCD1U25V2KX-GP
2 1
X01 EMI 12/16

EC9779 EC9771
3D3V_S5

1D5V_S3
EC9758
1D5V_S3

PW R_3D3V_DCBATOUT

DCBATOUT

SC47P50V2JN-3GP SCD1U25V2KX-GP
DY

2 1 SCD1U25V2KX-GP
DY

EC9756 SCD1U25V2KX-GP

EC9757 SCD1U25V2KX-GP
+DC_IN

2 1 1 2
EC9754 SCD1U25V2KX-GP

EC9755

EC9773 2 1
DY

EC9781

1 DY 2

1 DY 2
SCD1U25V2KX-GP
1 DY 2

1
SCD1U25V2KX-GP
EC9768

SC47P50V2JN-3GP
2 1
DY

2 1

3D3V_S5
SCD1U25V2KX-GP

3D3V_S5
2

EC9784 EC9777
SC47P50V2JN-3GP SCD1U25V2KX-GP
2 1
DY DY DY DY

2 1
EC9774
EC9782
SCD1U25V2KX-GP
SCD1U25V2KX-GP 2 1
2 1
DY

EC9783
EC9776
SC47P50V2JN-3GP SCD1U25V2KX-GP
2 1 EC9759
2 1
5V_S5

EC9780 EC9772 SCD1U25V2KX-GP

DY

SC47P50V2JN-3GP SCD1U25V2KX-GP 2 1
2 1 EC9761
2 1
2

2
EC9775 SCD1U25V2KX-GP
SCD1U25V2KX-GP 2 1 EC9729
DY

1D1V_S0

2 1
DY DY DY

SCD1U25V2KX-GP
DY

EC9778 EC9765 2 1
DCBATOUT

SCD1U25V2KX-GP SCD1U25V2KX-GP EC9730

2 1 2 1
DY DY DY DY

SCD1U25V2KX-GP
EC9752 SCD1U25V2KX-GP

EC9753

EC9750 SCD1U25V2KX-GP

EC9751 SCD1U25V2KX-GP

EC9767 EC9762 2 1
DY

SCD1U25V2KX-GP SCD1U25V2KX-GP
1 DY 2

1 DY 2

1 DY 2

2 1 2 1 EC9731
EC9769 SCD1U25V2KX-GP
EC9764 2 1
SCD1U25V2KX-GP

DY DY DY
2

SCD1U25V2KX-GP SCD1U25V2KX-GP
5V_S5

2 1 EC9727
2 1
DY
Date:

Size

Title

<Core Design>

EC9760 SCD1U25V2KX-GP
A3

EC9770 SCD1U25V2KX-GP 2 1
SCD1U25V2KX-GP 2 1
EC9728
Friday, April 22, 2011

2 1
DY

EC9763 SCD1U25V2KX-GP
Document Number

SCD1U25V2KX-GP 2 1
2 1
DY DY

EC9766
SCD1U25V2KX-GP
2 1
Enrico 14 AMD
UNUSED PARTS/CAP

Taipei Hsien 221, Taiwan, R.O.C.

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Wistron Corporation
Sheet
1

1
97
of
109

Rev
A00

D
 5 4 3 2 1

Thermal Block Diagram Audio Block Diagram

D D

SPKR_PORT_D_L-

SPKR_PORT_D_R+ SPEAKER

Codec
92HD87B1
PAGE28 DXP P2800_DXP
HP1_PORT_B_L HP
HP1_PORT_B_R
SC2200P50V2KX-2GP
MMBT3904-3-GP
OUT
DXN P2800_DXN
C
UMA Place near CPU
C

Thermal PWM CORE

P2800
MMBT3904-3-GP
HP0_PORT_A_L MIC
PAGE27 GPIO5 SYS_THRM TDR T8 HP0_PORT_A_R

KBC GPIO92 CPU_THRM TDL

2N7002 PURE_HW_SHUTDOWN# VREFOUT_A_OR_F IN
OTZ THERM_SYS_SHDN# D EN 3V/5V
NPCE795P S
G
IMVP_PWRGD PGOD
VR
Put under CPU(T8 HW shutdown)

VGA_THRM TDR
GPIO4
PAGE28
GPIO94 GPIO56
P2800_VGA_DXP
DXP THRMDA DMIC_CLK/GPIO1
B B
FAN_TACH1

SC2200P50V2KX-2GP SC2200P50V2KX-2GP DMIC0/GPIO2

VGA DXN
P2800_VGA_DXN
THRMDC
VGA
Thermal
FAN1_DAC

Place near GPU(DISCRETE only).

TACH
P2800
FAN MMBT3904-3-GP
PORTC_L
5V VIN
PORTC_R
Analog
OTZ
PH VREFOUT_C MIC
VSET VOUT
VIN

FAN CONTROL
A
P2793 <Core Design> A

PAGE28 Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
THERMAL/AUDIO BLOCK DIAGRAM
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 98 of 109
5 4 3 2 1
 5 4 3 2 1

POWER SEQUENCE
DCBATOUT

3D3V_AUX_S5

D RTC_AUX_S5 D

KBC_ROM_STRAPS

S5_ENABLE

5V_S5 T2
Min Max Description
3D3V_S5
T1 - - +3.3V_S5 to +1.1V_S5
T1
1D1V_S5
T2 10 ms - +3.3V_S5 to resume reset (RSMRST#).
RSMRST#(KBC_RSMRST#)
T7 98 ms 150 ms FCH PWRGOOD assertion to LDT_PG assertion delay.
S5_ROM_STRAPS
T8C 1.0 ms 2.3 ms PCIRST# to LDT_RST#.
T13
PWR_BTN#(PM_PWRBTN#)
T9A 101 ms 113 ms FCH PWR_GOOD to A_RST#.
PM_SLP_S3#/PM_SLP_S5#
T13 8 ns - PwrButton to SLP_S3# / SLP_S5# de-assertion
C C
1D5V_S3

1D5V_S0

0D75V_S0

5V_S0

3D3V_S0

1D8V_S0

1D1V_S0

1V_S0

VCORE_EN

B
APU_VDD B

APU_VDDNB

FCH_PWRGD T7

H_CPUPWRGD

S0_ROM_STRAPS
T9A
A_RST# T8C

APU_RST#

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
POWER SEQUENCE
Size Document Number Rev
A3 A00
Enrico 14 AMD
Date: Friday, April 22, 2011 Sheet 99 of 109
5 4 3 2 1
 A B C D E

Power Shape

Power Delivery Block Diagram Regulator LDO Switch

AD+
4 AO4407A DCBATOUT 4
Adapter 40

ISL6265C TPS51218 TPS51218 TPS51216

42,43 46 46 44
BT+
Battery
Charger APU_VDD APU_VDD_NB 1D1V_S5 1V_S0
BQ24707

40 AO4468
36

1D5V_S3 DDR_VREF_S3 0D75V_S0

1D1V_S0
3 3

AD+ AD+ 38,40

DCBATOUT DCBATOUT 40,41,42,43,44,46,49,92,97

15V_S5 15V_S5 36,41,49,93

A04468
TPS51125A 36
BT+ BT+ 39,40
41 5V_S5 5V_S5 36,38,41,42,44,46,49,61,65,68,69,92,93,97

5V_S0 5V_S0 6,28,29,36,50,51,56,68,69,86,97

5V_PWR 5V_AUX_S5 3D3V_PWR_2

3D3V_S5 1D5V_S0 RTC_AUX_S5 RTC_AUX_S5 17,27,60

3D3V_AUX_S5 3D3V_AUX_S5 27,28,36,40,41,60,93

3D3V_AUX_KBC 3D3V_AUX_KBC 27,28,39,60

15V_S5 3D3V_AUX_S5 3D3V_S5 3D3V_S5 6,18,19,20,21,31,36,38,41,42,44,46,47,60,70,82,86,93,97

3D3V_S0 3D3V_S0 6,7,14,15,17,18,20,21,27,28,29,31,32,36,42,49,56,60,65,71,93,97

3D3V_PWR
3D3V_CARD_S0 3D3V_CARD_S0 32,74
2 2
1D8V_S0 1D8V_S0 6,7,17,20,42,47,71,93
PA102FMG AO4468
5V_S5 31 36
1D5V_S3 1D5V_S3 5,7,14,15,36,44,93,97

1D5V_S0 1D5V_S0 36,65

1D1V_S5 1D1V_S5 20,36,46

3D3V_LAN_S5 3D3V_S0 1D1V_S0 1D1V_S0 20,36,97

RT8015B 1D1V_SATA_S0 1D1V_SATA_S0 19,20

48 1D1V_PCIE_S0 1D1V_PCIE_S0 17,20

VDDIO_AZ VDDIO_AZ 20,21

UP7534BRA8 UP7534BRA8 AO4468 1D8V_S0

1V_S0 1V_S0 4,7,46
61 61 36 RTL8105E-VB AO6402A DDR_VREF_S3 DDR_VREF_S3 5,14,15,44
31 49 0D75V_S0 0D75V_S0 14,15,44

APU_VDDNB APU_VDDNB 7,42,43

USB20_VCCA USB20_VCCA 5V_S0
APU_VDD APU_VDD 7,42
1D05V_LOM LCDVDD
1 <Core Design> 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Power Block Diagram
Size Document Number Rev
A3
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 100 of 109
A B C D E
 5 4 3 2 1

2.2K
3D3V_S0
0 OHM
SMB_DATA PCH_SMBDATA
AE22 200 DIMMA(DM1)
SMB_CLK PCH_SMBCLK
AD22 202
14
DY DY SMB Addr=[XX]
D
10K D

FCH F5 SCLK1
3D3V_S5 200
SDATA1 DIMMB(DM2)
F4 202
15
SMB Addr=[XX]

10K
32
D25 SCLK2 WLAN
30
SDATA2 65
F23
SMB Addr=[XX]

2.2K
3D3V_S5
0 OHM
B26 SCLK3 APU_SIC
SDATA3 DY APU_SID
E26

1K
3D3V_S0
APU_SIC
C
P3 C
APU_SID
P4

2.2K
5V_HDMI_S0
0 OHM
APU B2
PCH_HDMI_CLK_R DDC_CLK_HDMI
15
PCH_HDMI_DATA_R DDC_DATA_HDMI HDMI
C2 16
51
2.2K
3D3V_S0 SMB Addr=[XX]
33 OHM
A3 LVDS_DDC_CLK
13 LCD Panel
LVDS_DDC_DATA
B3 11 (LVDS Type)
49
4.7K
5V_CRT_S0 SMB Addr=[XX]
0 OHM
DDCCLK CRT_DDCCLK_CON CRT
F2 15
DDCDATA CRT_DDCDATA_CON
B
D4 12 B
50
DY DY SMB Addr=[XX]

0 OHM
SML1_CLK APU_SIC
67
SML1_DATA APU_SID
68

4.7K
3D3V_AUX_KBC
EC 100 ohm
BAT_SCL PBAT_SMBCLK1 Battery
70 3
BAT_SDA PBAT_SMBDAT1
69 4 connector 39
100 ohm
DY DY SMB Addr=[XX]

A NPCE795PA0DX A

short pad <Core Design>

PWR_CHG_BAT_SCL Charger
9
PWR_CHG_BAT_SDA BQ24707RGRRG4 Wistron Corporation
8
40 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
SMB Addr=[XX]
Title
SMBUS BLOCK DIAGRAM
Size Document Number Rev
A2
Enrico 14 AMD A00
Date: Friday, April 22, 2011 Sheet 101 of 109
5 4 3 2 1
 5 4 3 2 1

Change notes -

DATE VERSON DATE Page Modify List OWNER

X01 9/23 50 Delete F5001, Share Fuse with HDMI EE

D D
71 DUMMY Debug Port DB1,RN7102, R7107 EE

Change R2724 value to 20K, X01 Version EE

27

ME
39,56 Change BATT1,ODD1,HDD1 Connector

27 Add C2722 0.1uF between Q2703 G&S pin for fixed leakage voltage to 3D3V_AUX_KBC under DC mode. EE

27 Add Q2706 2N7002 to avoid leakage loop from 3D3V_S5 to 3D3V_AUX_KBC issue when 10mW latched fail EE
timing. Un-stuff C2713 to follow the standard schematics.

28 Change U2801, U2803 to 74.02800.A71 EE

C C

X01 9/29 61 Change U6102 to 74.07534.079 EE

50 Change L5001,L5002,L5003 bead to 0402 size:68.00217.991 EE

38,59,69,
82 Change DCIN1,RJ45,TPAD1,IOBD1 Connector ME

82 Change IOBD1 Pin define EE

X01 10/13 6 Dummy APU_SIC, APU_SID level shifter, pop R644,R645 EE

B B

6 EE
Add level shifter for H_Thermtrip#

36 DUMMY Q3601,R3622 for reserved EE

28 Change R2816,R2822 to 107KR,R2817 ,R2821to 226KR for new version P2800 chip EE

39 Delete R3901 for double pull high EE

49 Delete R4902 for double resister EE

27 Change PURE_HW_SHUTDOWN#(R2705) power rail to 3D3V_AUX_KBC EE

X01 10/20 92 Change PR9213 to 75K, PR9211 to 150K for VGA_CORE (Robson-LP)Output Power
A <Core Design> A

27,36 Add GPIO97 for IMVP_PWRGD control ,Change D3605.2 to 1V_S0_PWRGD,Delete D3606, EE
Change D3603.1 to VRM_VDD_PWRGD for sequence Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
86 Modify 1D5V_VGA_PWRGD to 1D5V_VGA_PWOK EE
Title

31 Dummy R3101,R3102,Q3101,R3108 for leakage EE Change notes

Size Document Number Rev
A3
Change R3607 to 10K,C3605 to 15n,PR4711 to 0ohm, PC4710 DY, C3610 DY, R3633 to 33K, C3615 to 33n,R3604 to33K EE Enrico 14 AMD A00
36,47
for sequence Date: Friday, April 22, 2011 Sheet 102 of 109
5 4 3 2 1
 5 4 3 2 1
Change notes -

DATE VERSON DATE Page Modify List OWNER

X01 10/20 20 Change R2004 to 0603 size for current tolerance EE

D 93 Change PR9311 to 10K for 1V_VGA Voltage Power D

61,65 Add C6105,C6106,C6509,C6510 to 6.8p for solve SIV USB fail EE

27 Change RN2705 8P4R to 4P2R and R2715, RN2705 DY EE

40 Add PR4061 PR4062 100KR, empty other parts for fine tune sequence for leakage EE

10/27 85,17 Modify C8524,C8525=12p, C1715,C1717=18p for crystal frequence match EE

68 Add LED for WLAN EE

C C
14 Change RN1401 to 22 ohm and pop C1423,C1424 for solved SMBus SIV Fail EE

11/10 38 Change DCIN CONN pin define EE

31 Solved leakage issue follow DV15 EE

68 Modify Wireless LED schematic EE

85 Change L8502,L8503,L8507,L8505,L8513 to short pad for power EE

B EE B
17,31 Modify C1720=15p, C3102=15p for crystal frequence match

28 Add G709 for thermal solution EE

68 Delete RN6802,RN6801 EE

83~89 Change GPU from Robson LP to Seymour XT EE

11/17 46 DY 1V to merge 1D1V EE

27 Add two model ID for config EE

58 Delete MIC2 and move mic1 to IO Board EE

92 Update Seymour and Robson power plan setting(PR9219,PR9210,PR9214,PR9211) EE

A <Core Design>
A
87 Pop R8421 for check list request EE
Wistron Corporation
EE 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
68 Modify power LED schematic and charger LEDs Taipei Hsien 221, Taiwan, R.O.C.

Power Title
Merge with power schematic Change notes

27 Add LID_CLOSE# pull high EE Size Document Number Rev

A3 Enrico 14 AMD A00

Date: Friday, April 22, 2011 Sheet 103 of 109

 5 4 3 2 1

Change notes -

DATE VERSON DATE Page Modify List OWNER

50,51 Modift CRT,HDMI share fuse schematic EE

D
X01 11/24 31 Change L3101 to slime type and add R3101 GIGA mark for 10/100 internal PU EE D

27 Change R2726, R2710 to F tolerance for accurate level to KBC EE

27,65,68 Change WLAN LED design to meet on/off behavior SPEC EE

27 Change RTC_POWER from RTC_AUX_S5 to 3D3V_AUX_S5 for saving RCT power and no influence on PSL EE

6 Pull up LTDP0_HPD to 5V from AMD SCL 1.04 EE

6 Change RN634 to 2K2R follow AMD SCL 1.03 EE

C C

6 Add level shifter for LVDS SMBus follow AMD SCL 1.04 EE

59 Rename part reference for Lan ESD EMI

31 Set R3101 BOM option for 8105E DY EE

31 Add RTC sense schematic EE

12/2 27 Reserved R2778 for EC power switch logic circuit. EE

B B

27 Set R2769 empty, Duplicated function in page 40. EE

28 Reserve R2861 for hysteresis EE

36 Reserve C3633 for power up sequence tunning EE

49 Modify TP4906,TP4907 to AFTP EE

17,31 Change 25MHZ, 32.768K to small size by source recommand Sourcer

2 Modify Block Diagram EE

36 Change U3606 P/N EE

<Core Design>
A
59 Modify Transformer schenatic from GIGA to 10/100 for latest config EE A

6 Remove level shifter for LVDS SMBus(AMD confirm) EE Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

40 Reserve snuber 2.2ohm+560p for EMI solution EMI Title

Change notes
50 Change L5001,L5002 and L5003 from 220hm to 30ohm for EMI Solution EMI
Size Document Number Rev
A3 Enrico 14 AMD A00
50 Change 2N7002E to 2N7002K for EOL Sourcer
Date: Friday, April 22, 2011 Sheet 104 of 109

5 4 3 2 1
 5 4 3 2 1

Change notes -

DATE VERSON DATE Page Modify List OWNER

27 Modify R2776 to 64.9K EE

D
59 Modify R5903,R5904 to 0603 size EE D

27 Change R2739 to 1% tolerance EE

6 Change RN634 form 2.2KR to 1KR by AMD suggestion EE

65,68 Change WLAN LED indicator for reserve EC and module circuit EE

60 Change Q6001.G from +RTC_VCC to RTC_PWR EE

15 Reserve R1531 and R1532 69.8R for memory glitch issue EE

C C

36,46 Stuff 0R and change to open-gap for merge power rail EE

47 Change PQ4701 to ESD 2KV for Vendor EOL EE

38,39 PD3801 change to P6SMBJ58A,PD3902 change to SMF18AT1G Power

40 Add PQ4007 PR4012 and PR4037 to improve AC_IN# delay issue Power

All Change reference from PTCxx to PTxx for meet SMT Process Power
B B

41,42,44, Change PC4111,PC4116,PC4117,PC4204,PC4223,PC4203,PC4301,PC4302,PC4304,PC4403,PC4404,PC4405,PC4602,PC4603, Power

46,92 PC4604,PC4613,PC4614,PC4618,PC9202,PC9203,PC9204 to 10u 0805 size

92 PR9205 change to 13 Kohm for OCP setting Power

6 Remove SIC,SID level shifter EE

12/7 36 Reserve 1V_S0_PWRGD link for 1V_S0 power rail EE

38 Power
Change PD3801: 83.P6SMB.DAG(YS) change to 83.P6SBM.DAG(CHENMKO).

86 Change U8601.U8603,U8604,U8606 pin G to 5v_S0 EE

28 Remove R2822,R2821,C2819 and NC U2803 OTZ pin EE

<Core Design>
A A
36 Dummy C3609 EE

49 Change R4903,R4904 to 0603 size EE

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
17 Add RTC detect pin on REQ1#_GPIO40 EE Title
Change notes
61,65 Move C6105,C6106,C6509,C6510 to Connector side EE
Size Document Number Rev
A3 Enrico 14 AMD A00
61 Pop TC6102 and DY on IO Board side EE Date: Friday, April 22, 2011 Sheet 105 of 109
5 4 3 2 1
 5 4 3 2 1

Change notes -

DATE VERSON DATE Page Modify List OWNER

71 Pop DB1,RN7102,R7107 for debug EE

D
74 DY EC7401,EC7403 for reserve EE D

36,46 Add PC4621 and PT4603 1V_PWR and change 1V_S0 to 1V_PWR EE

14,59 Rename C59011 to C5901 and Change TC4101 to 79.22719.20L EE

46 Dummy 1V power generator foe back up solution EE

40 Add PR4063,PC4025 for EMI Snaber solution EMC

12/7_1 17 Reserve damping resistor R1766 for crystal drive level adjustment EE
C C

65 Reserve BT_ACT for future module extension EE

69 Change KB connector EE

12/8 69 Add Caps led schematic and change AD_IA_HW2 to GPIO50, PCIE_RST# to GPIO36, CAP_LED change to GPIO30 EE

12/10 27 Add R2780 and DY R2732,Q2702 for EC "PROCHOT_EC" pin from PP to OD type EE

12/13 68,82 Change IOBD2 and PWBTN1 pin define EE

B B

38,40,41 PC3806 PC4006 PC4008 PC4110 and PC4114 change to 10uF 25V 0805 size (78.10622.51L) Power

28 Change U2801,U2803 to B version(74.02800.B71) EE

97 Add EMI Solution EMI

12/14 40 Change PC4004 and PC4024 from 1uF to 0.1uF (78.10424.2BL) Power

28 DY R2816,R2817,C2831 for set ADJ floating EE

61 DY TC6102 for reserve on IO board EE

12/15 82 Change IOBD2 pin define and connector EE, ME

<Core Design>
A A
20 Chnage R2004 to 0402 size EE

17 Change R1766 location and change to 1KR for Put Rd at chip output side and suppress amplitude. EE
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

12/17 6,65 Swap RN605,TR6501 for Layout EE Title

Change notes

97 Add EMI Solution EMI Size Document Number Rev

A3 Enrico 14 AMD A00
36 Change C3615 tolerance from 16V to 25V for component derating high voltage tolerance EE Date: Friday, April 22, 2011 Sheet 106 of 109
5 4 3 2 1
 5 4 3 2 1

Change notes -

DATE VERSON DATE Page Modify List OWNER

36 Delete R2779 for LID_Close# double pull high EE

D
12/21 59 Change C5904 to 0.01u from vendor recommand EE D

50 Modify CRT Hsync & Vsync level shift follow DV15 EE

46 Modify 1V_S0 Schematic EE

12/21_1 42 DY PR4214,PR4402 for pull up on R3624 EE

12/22 61 DY C6104,C6108 EE

12/22_1 56 Change HDD1 CONN to 62.10065.H71 ME

C C

61 DY TC6101, Stuff TC6103 EE

12/23 20 Change to 10u 0805 size EE

12/23_1 Implement OPI Solution EE

12/27 Crooect VGA setting, PR9210:150K, PR9211:75K EE

X02 03/03 41 Change PR4104 to 0 ohm,PR4106 to 200K EE

B B

83 DY R8309,R8310 to solve device error EE

31 Move C3125 to Q3101.S ,R3134 to 100k to solve unnecessary pulse EE

Change C3102,C3103 to 18P from vendor recommand EE

17 Change RN1701 to 22 ohm for solve SIV solution EE

50 Change RN5001 to 150 ohm for solve SIV solution EE

Stuff C5002,C5003,C5004 EE

97 Add SPR3,SPR4 ME
<Core Design>
A A
59 Add RN5901 for nonuse Giga lan EE

50,59,97 Change CRT ,TPAD1,RJ45 CONN, H10 Hole and add SPR3,SPR4 ME
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

03/07 83~87 Change VGA P/N to 71.ROBSO.M01 EE

Title
Change notes

85 DY R8525,R8526 and Q8501 for nonuse EE

Size Document Number Rev
A3 Enrico 14 AMD A00
28 DY R2813,R2805,R2832,C2808,U2805,R2812,R2811, Stuff R2823 for P2800 EE Date: Friday, April 22, 2011 Sheet 107 of 109

5 4 3 2 1
 5 4 3 2 1

Change notes -

VERSON DATE Page Modify List OWNER

28,85 DY U2803,R2815,R2812,R2814,C2813,C2814. stuff RN8501,Q8503 for GPU temperature by SMBus EE

D D
03/09 27 DY D2701,D2704 and D2705, Add R2781,R2782 and R2783 for connect directly EE

97 Change SPR3 to 34.39S07.003 EE

38,39 Rename AFPP3811,3812,3813,3814,3901,3902,3903,3904 to AFTP EE

03/10 38,60 Delete AFTP6001,AFTP6002,AFTP3811 EE

17 Change C1719,C1720 to 18p for vendor recommand EE

40 Delete PR4063 and PC4025 for EMI Solution EE

C C

03/10_1 71 Add R7102 to reserved EE

27 Change R2724 to 33k for SC PCB version EE

31 Add RN3101,Q3104 and R3108 to solve Lan leakage issue EE

03/11 41,42,47 Change power gap P/N EE

Change 0 ohm to short pad EE

B B

61,65,82 Delete TR6101,TR6501,TR8202,TR8201 CMC EE

03/16 41 Change PR4103 from 150Kohm to 143Kohm for 5V OCP setting Power

44 Change PR4408 from 75Kohm to 66.5Kohm for 1.5V OCP setting Power

92 Change PR9205 from 13Kohm to 11 Kohm for VGA OCP setting Power

47 Change PC4709 from 1.5KpF to 100pF for comp Power

46 Dummy PC4602 and POP PC4604. Power

03/17 28 DY C2818,D2802,C2816 and Stuff C2815 EE

A <Core Design> A
03/22 40 DY PQ4007,PR4037,PR4012 for new version IC EE

A00 04/07 49 Add 0 ohm at Q4901.4 for reserved to avoid module leakage EE Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

71 Change DB1 foorprint to PAD-10P-177042 for factory request EE

Title
Change notes

18 Change R1818 to 0 ohm for reserved non-zero power ODD EE

Size Document Number Rev
A3 Enrico 14 AMD A00
04/11 18 Change R2724 to 47K for X-build version EE
Date: Friday, April 22, 2011 Sheet 108 of 109
5 4 3 2 1
 5 4 3 2 1

Change notes -

VERSON DATE Page Modify List OWNER

4/12 40 DY PR4029,PR4028,PQ4004 and PQ4006 for nouse because just use 65W adapter EE

D
40 Change C8617 to 10u for CRB to avoid voltage drop EE D

20 DY C2005,C2007, and add R2030 for nonuse EE

97 Change H12,H13 to 34.4HL17.001 for ME asked ME

4/12_1 97 Delete H13 for ME asked ME

18 Change EC1801 to 22p for EMI solution EMC

68 Change R6806,R6812,R6801,R6833 to 330 ohm for brightness EE

4/13
C C

4/15 56 DY R5612, Pop Q5602 for modify Zero power ODD EE

51 Chnage RN5004 to ZZ.0R08P.ZHH to modify layout symbol is short pad EE

4/17 28 Change R2817 to 0 ohm for setting T8 temperature from 85 to 90 degree to pass reliability test EE

4/21 56 DY U5601,TC5604,R5606,Q5601,R1818,R5612, Stuff R5604,R5603 for remove Zero power ODD EE

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Change notes

Size Document Number Rev

A3 Enrico 14 AMD A00

Date: Friday, April 22, 2011 Sheet 109 of 109

5 4 3 2 1