// DSCH 2.

7a
// 2/11/2019 16:19:06
// C:\Users\Matias\Documents\CURSOS DEL 8VO CICLO\MICRO-NANO
SISTEMAS\LABORATORIO\INFORME PREVIO 3\bloque del restador.sch

module bloque del restador( A0,A1,A2,B1,B0,Q3,R0,R1);

input A0,A1,A2,B1,B0;
output Q3,R0,R1;
or #(16) or2(Q3,w1,w2);
or #(19) or3(w2,w4,w5,A2);
or #(19) or3(w1,w7,w8,w9);
and #(16) and2(w5,w10,w11);
and #(16) and2(w4,A1,w11);
and #(16) and2(w9,A1,w10);
and #(16) and2(w8,w10,A0);
and #(16) and2(w7,A1,A0);
not #(38) inv(w11,B0);
not #(52) inv(w10,B1);
not #(31) inv(w16,A1);
not #(24) inv(w17,A0);
and #(16) and2(w18,w17,A1);
xor #(16) xor2(w19,A0,B0);
not #(10) inv(w20,A2);
and #(16) and2(w21,w11,A0);
and #(16) and3(w22,A0,B1,w16);
and #(16) and2(w23,B0,w10);
and #(16) and2(w24,w18,w23);
or #(19) or3(w25,w21,w22,w24);
and #(16) and2(w26,w25,w20);
and #(16) and2(w27,w19,A2);
or #(16) or2(R0,w27,w26);
and #(16) and3(w29,B1,w11,w16);
and #(16) and3(w30,B1,w16,A0);
and #(16) and2(w31,B0,w10);
and #(16) and2(w32,w17,w16);
and #(16) and3(w33,w10,A1,A0);
and #(16) and3(w34,w10,A1,w11);
and #(16) and2(w35,B0,B1);
and #(16) and2(w36,w17,A1);
and #(16) and2(w37,w32,w31);
or #(19) or3(w38,w29,w30,w37);
and #(16) and2(w39,w36,w35);
or #(19) or3(w40,w33,w34,w39);
and #(16) and2(w41,w38,A2);
or #(16) or2(R1,w41,w40);
endmodule

// Simulation parameters in Verilog Format

always
#1000 A0=~A0;
#2000 A1=~A1;
#4000 A2=~A2;
#8000 B1=~B1;
#16000 B0=~B0;

// Simulation parameters
// A0 CLK 10 10
// A1 CLK 20 20
// A2 CLK 40 40
// B1 CLK 80 80
// B0 CLK 160 160