Contador.

vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

ENTITY contador IS
PORT(reloj, borrar, cargar, habilcnt, descendente : IN STD_LOGIC;
dato_ent : IN STD_LOGIC_VECTOR(3 downto 0);
Q : OUT STD_LOGIC_VECTOR (3 downto 0);
ct_term : OUT STD_LOGIC);
END contador;

ARCHITECTURE sol OF contador IS

SIGNAL conteo: STD_LOGIC_VECTOR(3 downto 0); -- define un bus de 4
bits
BEGIN

PROCESS(reloj,borrar,descendente)
BEGIN
if borrar='1' then conteo<="0000"; -- borrar asíncrona
elsif (reloj'event and reloj='1') then -- flanco
ascendente?
if cargar='1' then conteo<=dato_ent; --carga en
paralelo
elsif habilcnt='1' then -- habilitado?
if descendente='0' then conteo<=conteo+1; -
-incremento
else conteo<=conteo-1; --decremento
end if;
end if;
end if;
if (((conteo="0000" and descendente='1')) OR
((conteo="1111" and descendente='0'))) AND habilcnt='1'
then ct_term<='1';
else ct_term<='0';
end if;
q<=conteo; --transfiere el contenido del registro a las
salidas
END PROCESS;
END sol;

Registro_universal.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity registro_universal is
Port ( D: in STD_LOGIC_VECTOR(3 downto 0);
 S : in STD_LOGIC_VECTOR(1 downto 0);
CLK, R, L, RESET: in STD_LOGIC;
Q: out STD_LOGIC_VECTOR(3 downto 0));
end registro_universal;

Architecture sol of registro_universal is

SIGNAL Q1: STD_LOGIC_VECTOR(3 downto 0);
Begin
Q <= Q1;

process (CLK, RESET)

begin
if reset ='0' then Q1 <= "0000";
elsif (clk'event and clk='1') then
case S is
when "00"=> Q1<=Q1;
when "01"=> Q1<=R & Q1 (3 downto 1);
when "10"=> Q1<=Q1 (2 downto 0) & L;
when "11"=> Q1<=D (3 downto 0);
when others => Q1<=Q1;
end case;
end if;
end process;
end sol;