EXAMPLES OF COMBINATIONAL LOGIC CIRCUITS

Design Example: Two-bit Comparator

A B C D LT EQ GT
0 0 0 0 0 1 0
0 1 1 0 0
1 0 1 0 0
N1 A LT AB<CD 1 1 1 0 0
B 0 1 0 0 0 0 1
EQ AB=CD
C 0 1 0 1 0
N2 GT AB>CD 1 0 1 0 0
D
1 1 1 0 0
1 0 0 0 0 0 1
0 1 0 0 1
1 0 0 1 0
1 1 1 0 0
block diagram 1 1 0 0 0 0 1
and 0 1 0 0 1
truth table 1 0 0 0 1
1 1 0 1 0

we'll need a 4-variable Karnaugh map

for each of the 3 output functions

Nota: Material adpatado del curso: “Components and Design Techniques for
Digital Systems”, U. de Berkeley. Libro texto: Contemporaly logic design 1
Design Example: Two-bit Comparator
(cont’d)
A A A
0 0 0 0 1 0 0 0 0 1 1 1

1 0 0 0 0 1 0 0 0 0 1 1
D D D
1 1 0 1 0 0 1 0 0 0 0 0
C C C
1 1 0 0 0 0 0 1 0 0 1 0
B B B

K-map for LT K-map for EQ K-map for GT

LT = A' B' D + A' C + B' C D

EQ = A'B'C'D' + A'BC'D + ABCD + AB'CD’ = (A xnor C) • (B xnor D)
GT = B C' D' + A C' + A B D'

LT and GT are similar (flip A/C and B/D)

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Design Example: Two-bit Comparator
(cont’d)
A B C D

two alternative
implementations of EQ
with and without XOR

EQ

XNOR is implemented with

at least 3 simple gates
EQ

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ARITMÉTICA ENTERA

Números enteros:
❚  Formato sin Signo (UNSIGNED)
❚  Formatos con Signo (SIGNED)
❙  Signo-Magnitud
❙  Complemento a 2 (El más usado)
SUMA SIN SIGNO
Suma binaria

0+0=0 Suma 0 con acarreo 0

0+1=1 Suma 1 con acarreo 0
1+0=1 Suma 1 con acarreo 0
1+1=0 Suma 0 con acarreo 1
1 + 1 +1 =1 Suma 1 con acarreo 1

Ejemplo 11 acarreo
1101 13
+0110 + 6
10011 19
RESTA SIN SIGNO

Resta binaria

0-0=0
1-1=0
1-0=1
10 - 1 = 1 (0 - 1 con acarreo negativo de 1)

10 10 1 10 10 acarreo
Ejemplo 1 1 0 1 0 0 1 0 210
- 0 1 1 0 1 1 0 1 - 109
0 1 1 0 0 1 0 1 101
MULTIPLICACIÓN SIN
SIGNO

Multiplicación binaria
0x0=0
1x0=0 Se efectúan los productos parciales,
0x1=0 desplazando cada producto parcial
1x1=1 una Posición a la izquierda

Ejemplo 1 1 1
x 1 1 _ 7
1 1 1 x 3
_1 1 1____ 21
1 0 1 0 1
DIVISIÓN SIN SIGNO

División binaria

Se realiza de igual forma que la decimal

Ejemplo 101110 11
011
01111
0101
011
0101
011
010 0
011
001
Full adder
ai bi ci si Couti
Full adder
0 0 0 0 0
0 0 1 1 0 Ci
Si
ai FA
couti
0 1 0 1 0 bi

0 1 1 0 1
1 0 0 1 0
1 0 1 0 1 Mostrar usando K-maps:
1 1 0 0 1
Si= (ai xor (bi xor ci))
1 1 1 1 1
Couti= bi .ci + ai .ci + ai.bi
 Two bits adder (TBA)
A1 A0 B1 B0 Co S1 S0
0 0 0 0 0 0 0
A1 0 1 0 0 1
S0 1 0 0 1 0
A0 1 1 0 1 1
TBA S1
B1 0 1 0 0 0 0 1
Co 0 1 0 1 0
B0 1 0 0 1 1
1 1 1 0 0
1 0 0 0 0 1 0
0 1 0 1 1
With two FA TBA 1 0 1 0 0
1 1 1 0 1
´0 ´ ci FA 1 1 0 0 0 1 1
S0 0 1 1 0 0
A0 ai Si 1 0 1 0 1
B0 bi coi 1 1 1 1 0

ci FA Four bit adder ?

A1 Si S1
ai
B1 bi coi Co
Design Example: 2x2-bit Multiplier

A2 A1 B2 B1 P8 P4 P2 P1
0 0 0 0 0 0 0 0
0 1 0 0 0 0
1 0 0 0 0 0
1 1 0 0 0 0
A1 P1 0 1 0 0 0 0 0 0
A2 P2 0 1 0 0 0 1
1 0 0 0 1 0
B1 P4 1 1 0 0 1 1
B2 P8 1 0 0 0 0 0 0 0
0 1 0 0 1 0
1 0 0 1 0 0
1 1 0 1 1 0
1 1 0 0 0 0 0 0
block diagram 0 1 0 0 1 1
and 1 0 0 1 1 0
truth table 1 1 1 0 0 1

4-variable K-map
for each of the 4
output functions

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Design Example: 2x2-bit Multiplier
(cont’d)
A2 A2
K-map for P8 K-map for P4
0 0 0 0 0 0 0 0
P4 = A2B2B1'
0 0 0 0 0 0 0 0
B1 + A2A1'B2 B1
0 0 1 0 0 0 0 1
B2 P8 = A2A1B2B1 B2
0 0 0 0 0 0 1 1
A1 A1

A2 A2
0 0 0 0
K-map for P2 K-map for P1 0 0 0 0
P1 = A1B1
0 0 1 1 0 1 1 0
B1 B1
0 1 0 1 0 1 1 0
B2 P2 = A2'A1B2 B2
0 1 1 0 + A1B2B1' 0 0 0 0
A1 + A2B2'B1 A1
+ A2A1'B1
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Design Example: BCD Increment by 1

I8 I4 I2 I1 O8 O4 O2 O1
0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 0
0 0 1 0 0 0 1 1
0 0 1 1 0 1 0 0
0 1 0 0 0 1 0 1
I1 O1 0 1 0 1 0 1 1 0
I2 O2 0 1 1 0 0 1 1 1
0 1 1 1 1 0 0 0
I4 O4 1 0 0 0 1 0 0 1
I8 O8 1 0 0 1 0 0 0 0
1 0 1 0 X X X X
1 0 1 1 X X X X
1 1 0 0 X X X X
1 1 0 1 X X X X
block diagram 1 1 1 0 X X X X
1 1 1 1 X X X X
and
truth table
4-variable K-map for each of
the 4 output functions

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 Design Example: BCD Increment by 1
(cont’d)
I8 I8
O8 O4
0 0 X 1 0 1 X 0

0 0 X 0 0 1 X 0
I1 I1
0 1 X X O8 = I4 I2 I1 + I8 I1' 1 0 X X
I2 O4 = I4 I2' + I4 I1' + I4’ I2 I1 I2
0 0 X X 0 1 X X
I4 O2 = I8’ I2’ I1 + I2 I1' I4
O1 = I1'
I8 I8
O2 O1
0 0 X 0 1 1 X 1

1 1 X 0 0 0 X 0
I1 I1
0 0 X X 0 0 X X
I2 I2
1 1 X X 1 1 X X
I4 I4

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Definition of Terms for Two-level
Simplification
❚  Implicant
❙  Single element of ON-set or DC-set or any group of these elements that
can be combined to form a subcube

❚  Prime implicant
❙  Implicant that can't be combined with another to form a larger subcube

❚  Essential prime implicant

❙  Prime implicant is essential if it alone covers an element of ON-set
❙  Will participate in ALL possible covers of the ON-set
❙  DC-set used to form prime implicants but not to make implicant essential

❚  Objective:
❙  Grow implicant into prime implicants (minimize literals per term)
❙  Cover the ON-set with as few prime implicants as possible
(minimize number of product terms)

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Examples to Illustrate Terms
A
0 X 1 0 6 prime implicants:
A'B'D, BC', AC, A'C'D, AB, B'CD
1 1 1 0
D
essential
1 0 1 1
C
0 0 1 1 minimum cover: AC + BC' + A'B'D
B

A
5 prime implicants: 0 0 1 0
BD, ABC', ACD, A'BC, A'C'D
1 1 1 0
D
essential 0 1 1 1
C
0 1 0 0
minimum cover: 4 essential implicants
B

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Process for Deriving a Minimized
Expression From a K-Map
❚  STEP 1
❙  Choose an element from the on-set. Find all of “maximal” groups of 1s and
Xs adjacent to that element. Check for adjacency in the horizontal and
vertical directions. (Remember that the K-map wraps from top row to
bottom and left-most column to right-most)
The prime implicants (adjacency groups) thus formed always contain a
number of elements that is a power of 2 (a sub-cube of the cube of the K-
map).
Repeat step 1 for each element of the on-set to find all prime implicants.

❚  STEP 2
❙  Visit an element of the on-set. If it is covered by a single prime implicant,
it is essential and will contibute a term to the final sum-of-products
expression. The others 1s covered by the essential implicant do not need
to be visited again as they definitely will be covered
Repeat Step2 until all essential prime implicants have been found.

❚  STEP 3
❙  If there remain 1s uncovered by essential prime implicants, select a
minimum number of prime implicants that cover them. Try several
alternative covers to find the one with the fewest possible implicants.
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 Example
F(A,B,C,D) = Σ m(4,5,6,8,9,10,13) + d(0,7,15)

Starting configuration: (a) First 1

A A
AB AB
00 01 11 10 CD 00 01 11 10
CD
00 X 1 0 1 00 X 1 0 1

01 0 1 1 1 01 0 1 1 1
D D
11 0 X X 0 11 0 X X 0
C C
10 0 1 0 1 10 0 1 0 1
B B

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 Example

F(A,B,C,D) = Σ m(4,5,6,8,9,10,13) + d(0,7,15)

(b) Second 1 (c) next (d) next

A A A
AB AB AB
00 01 11 10 CD 00 01 11 10 00 01 11 10
CD CD
00 X 1 0 1 00 X 1 0 1 00 X 1 0 1

01 0 1 1 1 01 0 1 1 1 01 0 1 1 1
D D D
11 11 0 X X 0 11 0 X X 0
0 X X 0
C C C
10 0 1 0 1 10 0 1 0 1 10 0 1 0 1
B B B

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 Example

F(A,B,C,D) = Σ m(4,5,6,8,9,10,13) + d(0,7,15)

(e) next (e) next

A A
AB AB
CD 00 01 11 10 00 01 11 10
CD
00 X 1 0 1 00 X 1 0 1

01 0 1 1 1 01 0 1 1 1
D D
11 0 X X 0 11 0 X X 0
C C
10 0 1 0 1 10 0 1 0 1
B B

F(A,B,C,D)= A´B + AB´D´ + AC´D

essentials
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Ex: F=a’b’d’ + abd’ +a’b

a’b’ ab’ab a’b

ON = (0,2,4,5,6,7,12,14)
c’d’ 1 0 1 1 DC=15
cd’ 1 0 1 1 OFF=(1,3,8,9,10,11,13)
cd 0 0 X 1
c’d 0 0 0 1

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Ex: F=a’b’d’ + abd’ +a’b

a’b’ ab’ab a’b Primes = a’d’,bd’,a’b,bc

c’d’ 1 0 1 1
cd’ 1 0 1 1 Minimum cover
(solución) is
cd 0 0 X 1
F =a’d’+bd’+a’b
c’d 0 0 0 1

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