VHDL

TECNOLÓGICO NACIONAL DE MÉXICO
INSTITUTO TECNOLÓGICO DE TUXTLA GUTIÉRREZ
INGENIERÍA ELECTRÓNICA
Materia: Diseño digital con VHDL
Trabajo a realizar:
Diseño de un circuito sumador y comparador con PLD
Alumno:
CABRERA ESQUIVEL MARIO ALBERTO
DÍAZ OLETA OSCAR DANIEL
LÓPEZ GÓMEZ CARLOS ALBERTO
Catedrático:
ING. DOMÍNGUEZ ZENTENO JOAQUIN EDUARDO
Tuxtla Gutiérrez, Chiapas, a 11 de septiembre del 2018

Diseño de Circuito Comparador.
se trata de una descripción funcional de dos bits porque expone la forma en que
trabaja el sistema; es decir, las descripciones consideran la relación que hay entre
las entradas y las salidas del circuito, sin importar cómo esté organizado en su
interior.
Si a = b la salida c será = 1
Si a ≠ B la salida c será = 0.
Para esta práctica se usaron los siguientes componentes.
-PLD GAL 16v8, - Leds diferentes colores, -Switch, -Bornera, -Resistencias y cables
Código usado.
library ieee;
use ieee.std_logic_1164.all;
entity comp is
port (a, b: in bit;
c:out bit);
end comp;
architecture funcional of comp is
begin
compara: process (a, b)
begin
if a = b then
c <='1';
else
c<='0';
end if;
end process compara;
end funcional;
Archivo RPT.
| | | | | | |
_________________
-| |-
-| |-
-| |-
-| CYPRESS |-
-| |-
-| |- Warp VHDL Synthesis Compiler: Version 6.1 IR 28
-| |- Copyright (C) 1991-2001 Cypress Semiconductor
|_______________|
| | | | | | |
======================================================================
Compiling: compara.vhd
Options: -yu -e10 -w100 -o2 -ygs -fP -v10 -dc16v8 -ppalce16v8-15pc/pi -b
compara.vhd -u contador.hie
======================================================================
vhdlfe V6.1 IR 28: VHDL parser

Sun Sep 09 19:02:53 2018
Library 'work' => directory 'lc16v8'

Linking 'C:\Archivos de programa\Cypress\Warp\bin\std.vhd'.
Linking 'C:\Archivos de programa\Cypress\Warp\lib\common\cypress.vhd'.
Linking 'C:\Archivos de programa\Cypress\Warp\lib\common\work\cypress.vif'.
Library 'ieee' => directory 'C:\Archivos de programa\Cypress\Warp\lib\ieee\work'
Linking 'C:\Archivos de programa\Cypress\Warp\lib\ieee\work\stdlogic.vif'.
vhdlfe: No errors.
tovif V6.1 IR 28: High-level synthesis

Sun Sep 09 19:02:53 2018

tovif: No errors.
topld V6.1 IR 28: Synthesis and optimization

Sun Sep 09 19:02:53 2018

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------
------------------------------------------------------
Alias Detection
------------------------------------------------------
------------------------------------------------------
Aliased 0 equations, 0 wires.
------------------------------------------------------
----------------------------------------------------------
Circuit simplification
----------------------------------------------------------
----------------------------------------------------------
Circuit simplification results:
Expanded 0 signals.
Turned 0 signals into soft nodes.
Maximum expansion cost was set at 10.
----------------------------------------------------------
Created 3 PLD nodes.
topld: No errors.
----------------------------------------------------------------------------
PLD Optimizer Software: DSGNOPT.EXE 31/03/2000 [v4.02 ] 6.1 IR 28
DESIGN HEADER INFORMATION (19:02:55)
Input File(s): compara.pla

Device : c16v8
Package : palce16v8-15pc/pi
ReportFile : compara.rpt
Program Controls:
COMMAND LANGUAGE_VHDL
COMMAND PROPERTY BUS_HOLD ENABLE
Signal Requests:
GROUP USEPOL ALL
GROUP FAST_SLEW ALL
Completed Successfully
----------------------------------------------------------------------------
OPTIMIZATION OPTIONS (19:02:55)
Messages:
Information: Optimizing logic using best output polarity for signals:
c
Summary:
Error Count = 0 Warning Count = 0
----------------------------------------------------------------------------
PLD Optimizer Software: MINOPT.EXE 01/NOV/1999 [v4.02 ] 6.1 IR 28
LOGIC MINIMIZATION ()
Messages:
Summary:
----------------------------------------------------------------------------
Messages:
Summary:
----------------------------------------------------------------------------
PLD Compiler Software: PLA2JED.EXE 31/03/2000 [v4.02 ] 6.1 IR 28
DESIGN EQUATIONS (19:02:55)
c =
a * b
+ /a * /b
----------------------------------------------------------------------------
DESIGN RULE CHECK (19:02:55)
Messages:
None.
Summary:
----------------------------------------------------------------------------
PINOUT INFORMATION (19:02:55)
Messages:
Information: Checking for duplicate NODE logic.
None.
C16V8A
__________________________________________
b =| 1| |20|* not used
a =| 2| |19|= c
not used *| 3| |18|* not used
not used *|10| |11|* not used
__________________________________________
Summary:
----------------------------------------------------------------------------
RESOURCE UTILIZATION (19:02:55)
Information: Macrocell Utilization.
Description Used Max

______________________________________
| Dedicated Inputs | 2 | 10 |
| Output Macrocells | 1 | 2 |
| I/O Macrocells | 0 | 6 |
______________________________________
3 / 18 = 16 %
Information: Output Logic Product Term Utilization.
Node# Output Signal Name Used Max

________________________________________
| 12 | Unused | 0 | 7 |
| 13 | Unused | 0 | 7 |
| 14 | Unused | 0 | 7 |
| 15 | Unused | 0 | 7 |
| 16 | Unused | 0 | 7 |
| 17 | Unused | 0 | 7 |
| 18 | Unused | 0 | 7 |
| 19 | c | 2 | 7 |
________________________________________
2 / 56 = 3 %
----------------------------------------------------------------------------
JEDEC ASSEMBLE (19:02:55)
Messages:
Information: Output file 'compara.jed' created.
Summary:
Completed Successfully at 19:02:55
Diseño de Circuito Sumador.

El objetivo del desarrollo de un circuito sumador es una vez dadas las entradas en
este caso el circuito estará compuesta por cuatro bits entradas, este devuelva la
suma de ambas entradas en tres bits.
Para esta práctica se usaron los siguientes componentes.
-PLD GAL 16v8, - Leds diferentes colores, -Switch, -Bornera, -Resistencias y cables
Código usado.
library ieee;
use ieee.std_logic_1164.all;
entity sum is
port (a: in bit_vector(3 downto 0);
s: out bit_vector(2 downto 0));
end sum;
architecture sumar of sum is
begin
process (a)
begin
case a is
when "0000" => s <= "000";

when "0001" => s <= "001";
when "0100" => s <= "001";
when "0010" => s <= "010";
when "0101" => s <= "010";
when "1000" => s <= "010";
when "0011" => s <= "011";
when "0110" => s <= "011";
when "1001" => s <= "011";
when "1100" => s <= "011";
when "0111" => s <= "100";
when "1010" => s <= "100";
when "1101" => s <= "100";
when "1011" => s <= "101";
when "1110" => s <= "101";
when others => s <= "110";
end case;
end process;
end sumar;
Archivo RPT.
| | | | | | |
_________________
-| |-
-| |-
-| |-
-| CYPRESS |-
-| |-
-| |- Warp VHDL Synthesis Compiler: Version 6.1 IR 28
-| |- Copyright (C) 1991-2001 Cypress Semiconductor
|_______________|
| | | | | | |
======================================================================
Compiling: SUMAS.vhd
Options: -yu -e10 -w100 -o2 -ygs -fP -v10 -dc16v8 -ppalce16v8l-15pc -b SUMAS.vhd
-u Sumador.hie
======================================================================
vhdlfe V6.1 IR 28: VHDL parser

Mon Sep 10 18:43:27 2018
Library 'work' => directory 'lc16v8'

Library 'ieee' => directory 'C:\Archivos de programa\Cypress\Warp\lib\ieee\work'
vhdlfe: No errors.
tovif V6.1 IR 28: High-level synthesis

Mon Sep 10 18:43:28 2018

tovif: No errors.
topld V6.1 IR 28: Synthesis and optimization

Mon Sep 10 18:43:28 2018

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------
------------------------------------------------------
Alias Detection
------------------------------------------------------
------------------------------------------------------
Aliased 0 equations, 0 wires.
------------------------------------------------------
----------------------------------------------------------
Circuit simplification
----------------------------------------------------------
----------------------------------------------------------
Circuit simplification results:
Expanded 0 signals.
Turned 0 signals into soft nodes.
Maximum expansion cost was set at 10.
----------------------------------------------------------
Created 7 PLD nodes.
topld: No errors.
----------------------------------------------------------------------------
DESIGN HEADER INFORMATION (18:43:30)
Input File(s): SUMAS.pla

Device : c16v8
Package : palce16v8l-15pc
ReportFile : SUMAS.rpt
Program Controls:
COMMAND LANGUAGE_VHDL
COMMAND PROPERTY BUS_HOLD ENABLE
Signal Requests:
GROUP USEPOL ALL
GROUP FAST_SLEW ALL
----------------------------------------------------------------------------
Messages:
Information: Optimizing logic using best output polarity for signals:
s(0) s(1) s(2)
Summary:
----------------------------------------------------------------------------
PLD Optimizer Software: MINOPT.EXE 01/NOV/1999 [v4.02 ] 6.1 IR 28
LOGIC MINIMIZATION ()
Messages:
Summary:
----------------------------------------------------------------------------
Messages:
Summary:
----------------------------------------------------------------------------
DESIGN EQUATIONS (18:43:30)
s(0) =
/a(0) * a(2)
+ a(0) * /a(2)
s(1) =
a(0) * a(1) * a(2) * a(3)
+ a(0) * /a(1) * a(2) * /a(3)
+ /a(0) * /a(1) * a(3)
+ /a(1) * /a(2) * a(3)
+ /a(0) * a(1) * /a(3)
+ a(1) * /a(2) * /a(3)
s(2) =
a(0) * a(2) * a(3)
+ a(0) * a(1) * a(2)
+ a(1) * a(3)
----------------------------------------------------------------------------
DESIGN RULE CHECK (18:43:30)
Messages:
None.
Summary:
----------------------------------------------------------------------------
PINOUT INFORMATION (18:43:30)
Messages:
Information: Checking for duplicate NODE logic.
None.
C16V8A
__________________________________________
a(3) =| 1| |20|* not used
a(2) =| 2| |19|= s(1)
a(1) =| 3| |18|* not used
a(0) =| 4| |17|* not used
not used *| 8| |13|= s(0)
not used *| 9| |12|= s(2)
not used *|10| |11|* not used
__________________________________________
Summary:
----------------------------------------------------------------------------
RESOURCE UTILIZATION (18:43:30)
Information: Macrocell Utilization.
Description Used Max

______________________________________
| Dedicated Inputs | 4 | 10 |
| Output Macrocells | 2 | 2 |
| I/O Macrocells | 1 | 6 |
______________________________________
7 / 18 = 38 %
Information: Output Logic Product Term Utilization.
Node# Output Signal Name Used Max

________________________________________
| 12 | s(2) | 3 | 7 |
| 13 | s(0) | 2 | 7 |
| 14 | Unused | 0 | 7 |
| 15 | Unused | 0 | 7 |
| 16 | Unused | 0 | 7 |
| 17 | Unused | 0 | 7 |
| 18 | Unused | 0 | 7 |
| 19 | s(1) | 6 | 7 |
________________________________________
11 / 56 = 19 %
----------------------------------------------------------------------------
JEDEC ASSEMBLE (18:43:30)
Messages:
Information: Output file 'SUMAS.jed' created.
Summary:
Completed Successfully at 18:43:30

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TECNOLÓGICO NACIONAL DE MÉXICO

INSTITUTO TECNOLÓGICO DE TUXTLA GUTIÉRREZ

Materia: Diseño digital con VHDL

Diseño de un circuito sumador y comparador con PLD

ING. DOMÍNGUEZ ZENTENO JOAQUIN EDUARDO

Tuxtla Gutiérrez, Chiapas, a 11 de septiembre del 2018

vhdlfe V6.1 IR 28: VHDL parser

Library 'work' => directory 'lc16v8'

tovif V6.1 IR 28: High-level synthesis

Linking 'C:\Archivos de programa\Cypress\Warp\bin\std.vhd'.

topld V6.1 IR 28: Synthesis and optimization

Linking 'C:\Archivos de programa\Cypress\Warp\bin\std.vhd'.

DESIGN HEADER INFORMATION (19:02:55)

Input File(s): compara.pla

OPTIMIZATION OPTIONS (19:02:55)

OPTIMIZATION OPTIONS (19:02:55)

DESIGN EQUATIONS (19:02:55)

DESIGN RULE CHECK (19:02:55)

PINOUT INFORMATION (19:02:55)

RESOURCE UTILIZATION (19:02:55)

Information: Macrocell Utilization.

Description Used Max

Information: Output Logic Product Term Utilization.

Node# Output Signal Name Used Max

JEDEC ASSEMBLE (19:02:55)

Completed Successfully at 19:02:55

Diseño de Circuito Sumador.

port (a: in bit_vector(3 downto 0);

s: out bit_vector(2 downto 0));

architecture sumar of sum is

when "0000" => s <= "000";

when "0100" => s <= "001";

when "0010" => s <= "010";

when "0101" => s <= "010";

when "1000" => s <= "010";

when "0011" => s <= "011";

when "0110" => s <= "011";

when "1001" => s <= "011";

when "1100" => s <= "011";

when "0111" => s <= "100";

when "1010" => s <= "100";

when "1101" => s <= "100";

when "1011" => s <= "101";

when "1110" => s <= "101";

when others => s <= "110";

vhdlfe V6.1 IR 28: VHDL parser

Library 'work' => directory 'lc16v8'

tovif V6.1 IR 28: High-level synthesis

Linking 'C:\Archivos de programa\Cypress\Warp\bin\std.vhd'.

topld V6.1 IR 28: Synthesis and optimization

Linking 'C:\Archivos de programa\Cypress\Warp\bin\std.vhd'.

DESIGN HEADER INFORMATION (18:43:30)

Input File(s): SUMAS.pla

OPTIMIZATION OPTIONS (18:43:30)

OPTIMIZATION OPTIONS (18:43:30)

DESIGN EQUATIONS (18:43:30)

DESIGN RULE CHECK (18:43:30)

PINOUT INFORMATION (18:43:30)

RESOURCE UTILIZATION (18:43:30)

Information: Macrocell Utilization.

Description Used Max

Information: Output Logic Product Term Utilization.

Node# Output Signal Name Used Max

JEDEC ASSEMBLE (18:43:30)