REPORTE DEL CIRCUITO ELECTRNICO DIGITAL

Elaborado por:
Cristbal Galileo Mendoza Prez

Octubre del 2016

0

NDICE
NDICE

MATERIAL Y EQUIPO

CLCULOS CON LGEBRA DE BOOLE

ELEMENTOS UTILIZADOS EN EL CIRCUITO

FUNCIONAMIENTO DEL CIRCUITO

APLICACIN

SOLUCIN DE ELEMENTOS QUE INTEGRAN UN CIRCUITO ELECTRNICO

DIGITAL SECUENCIAL
6
DIAGRAMA DEL CIRCUITO ELECTRNICO DIGITAL

FUENTES DE INFORMACIN

FOTOGRAFAS DEL CIRCUITO Y DE LA SECUENCIA DEL ARMADO DEL

CIRCUITO

CONCLUSIN

10

HOJAS DE ESPECIFICACIONES

11

MATERIAL
Circuitos integrados
1
1
1
1

7490
7404
7408
7432

Resistencias
5
470R
1
33R
Leds
4
1
1

Rojo
Naranja Ultra
Display DC05

Varios
7
1
1
1
1

Bases para CI de 14 terminales

Placa fenlica 10 x 10 cm
Tira te terminales hembra
Soldadura con aleacin estao/plomo (60/40)
Alambre No.22 (metro)

EQUIPO
1
1
1
1
1

Cautn tipo Lpiz

pinzas de corte
Pinzas de punta
taladro de mano
broca de 1mm de dimetro

CLCULOS CON LGEBRA DE BOOLE

El circuito decodificador, se dise a partir de una tabla de verdad, tomando
elementos de entrada los 2 bits, menos significativos provenientes del contador de
dcadas (7490), y como elementos de salida las terminales del display de 7
segmentos, estableciendo el orden de encendido de acuerdo los caracteres que se
deberan observar en el desplaye (0, 1, 2 y 3). Para simplificar el circuito se utiliz
el lgebra de Boole como se muestra en las ecuaciones siguientes.
Ecuaciones que generan el circuito digital
a = d = ab + ab + ab
b = ab + ab + ab + ab
c = ab + ab + ab
e = ab + ab
f = a b
b = ab + ab

a b g f

e d c b a display

0
0
1
1

1
0
1
0

0
1
0
1

0
0
1
1

1
0
0
0

1
0
1
1

1
1
0
1

1
1
1
1

1
0
1
1

0
1
2
3

Simplificando las ecuaciones con mapas de Karnaugh.

A
A

B
1
1

B
0
1

a = B + A

A
A

B
1
1

B
0
0

e = B

A
A

B
1
1

B
1
1

b = A + A

A
A

B
1
0

f = AB

B
0
0

A
A

B
1
0

B
1
1

c = A + B

A
A

B
0
1

A
A

B
1
1

B
0
1

d = B + A

B
0
1

g = B + A

Ecuaciones simplificadas que generan el circuito digital

a = d = b + a
b = a + a
c = a + b
e = b
f = a b
g=a

ELEMENTOS UTILIZADOS EN EL CIRCUITO

FUENTE DE ALIMENTACIN
Se emplea una fuente de alimentacin de 5 volts con una capacidad de
corriente a suministrar de 1 Ampere, la cual circula a travs de las diferentes etapas
del circuito general.
CIRCUITO RLC
Para este circuito se utiliza un circuito integrado 555, en configuracin
astable, para generar la seal de reloj, para la sincronizacin.
CIRCUITO CONTADOR
Este circuito tiene la funcin de generar un conteo en binario de 2 dgitos (0
a 3).
CIRCUITO DECODIFICADOR
un circuito lgico combinacional, compuesto por las compuertas lgicas OR,
AND y NOT, se encargan de decodificar el conteo binario, de manera que la salida
de este sea utilizada por el display de 7 segmentos, para visualizar el conteo binario
en el sistema decimal.

FUNCIONAMIENTO DEL CIRCUITO

La fuente de alimentacin se encarga de generar la energa necesaria para
el funcionamiento del circuito general en sus diferentes etapas, la primera etapa es
el circuito RLC, el cual est compuesto por un circuito oscilador 555 en configuracin
astable, que genera una seal cuadrada con frecuencia y ciclo de trabajo regulable,
la segunda etapa la compone un contador de dcada 7490 el cual utiliza la seal
que proviene del circuito oscilador para generar un conteo en binario de 0 a 9, donde
se utilizan los 2 bits menos significativos para alimentar un circuito decodificador en
la etapa 3, el cual est compuesto por circuitos integrados 7432 (OR), 7404 (NOT)
y 7408 (AND) y display de 7 segmentos ctodo comn, para visualizar el conteo en
decimal, la etapa 4, es la etapa del circuito electrnico de potencia que activa un
moto reductor al recibir la seal, cundo se alcanza un conteo de 3.

Fuente de
alimentacion
5 Volt a 1A

Etapa 1
circuito oscilador
(RLC)
Genera la senal de reloj

Etapa 2
contador de decada
(7490)
genera el conteo
bianario a partir de la
senal de reloj

Etapa 3
circuito
combinacional
(decodificador)
formado por las
compuertas logicas

Etapa 4
Display de 7
Segmentos
Despliega el conteo en
sitema decimal

0, 1, 2, 3

APLICACIN
La aplicacin que se le dar a este circuito, ser la de accionar una banda
transportadora despus de 3 segundos de iniciar un proceso anterior.
Propuesta de mejora
Cambiando la configuracin del circuito oscilador a monoestable el conteo no
sera por tiempo sino de eventos

SOLUCIN DE ELEMENTOS QUE INTEGRAN UN CIRCUITO

ELECTRNICO DIGITAL SECUENCIAL
Una solucin alternativa, a los elementos que integran el circuito electrnico
digital, seria utilizar un circuito microcontrolador, PIC o ATMEL, acoplado al circuito
electrnico de potencia, lo cual reducira considerablemente la cantidad de circuitos
integrados utilizados, ya que las etapas 1, 2 y 3 se reducira a una sola.

DIAGRAMA DEL CIRCUITO ELECTRNICO DIGITAL

FUENTES DE INFORMACIN

Sistemas digitales, principios y aplicaciones, tocci, widmer, prentice hall,

8va. ed., 2003

http://socrates.berkeley.edu/~phylabs/bsc/pdffiles/dm7490a.pdf

http://www.ti.com/lit/ds/symlink/sn74ls04.pdf

http://www.ti.com/lit/ds/symlink/sn74ls08.pdf

http://www.ti.com/lit/ds/symlink/sn74ls32.pdf

FOTOGRAFAS DEL CIRCUITO Y DE LA SECUENCIA DEL

ARMADO DEL CIRCUITO
1)

4)

2)

3)

5)

6)

CONCLUSIN
Un circuito lgico digital, trabaja con informacin codificada en lenguaje
binario es decir valores de 1 y 0 representados usualmente con el encendido y
apagado de un diodo emisor de luz, tomando en cuenta que este tipo de circuitos
utiliza dos tipos de niveles, el nivel alto que es representado con el numero 1
(encendido), mientras que el nivel bajo es representado con el numero 0 (apagado).
Para convertir un conteo en binario proveniente del contador de dcadas a
visualizarlo en sistema decimal, se utilizaron 3 tipos de compuertas lgicas, AND,
OR y NOT, en el planteamiento original del circuito digital era muy extenso, pero
con la simplificacin utilizando algebra de Boole, se pudo reducir el circuito de
manera considerable

10

HOJAS DE ESPECIFICACIONES
Hojas de especificaciones de los circuitos integrados

7404
7408
7432
7490

11














 



SDLS029C DECEMBER 1983 REVISED JANUARY 2004

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI: 04, S04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
LS04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. This are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

SN7404

SN5404
VCC
VIH

Supply voltage

VIL
IOH

Low-level input voltage

IOL
TA

Low-level output current

High-level input voltage

MIN

NOM

MAX

MIN

NOM

MAX

4.5

5.5

4.75

5.25

High-level output current

55

V
V

0.8

0.8

0.4

0.4

mA

16

mA

70

16

Operating free-air temperature

UNIT

125

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
TEST CONDITIONS

PARAMETER
VIK
VOH

VCC = MIN,
VCC = MIN,

II = 12 mA
VIL = 0.8 V,

VOL
II

VCC = MIN,
VCC = MAX,

VIH = 2 V,
VI = 5.5 V

IIH
IIL

VCC = MAX,
VCC = MAX,

VI = 2.4 V
VI = 0.4 V

IOS
ICCH

VCC = MAX

ICCL

VCC = MAX,
VCC = MAX,

MIN

SN5404
TYP

MAX

MIN

SN7404
TYP

1.5
IOH = 0.4 mA
IOL = 16 mA

2.4

3.4
0.2

1.5
2.4

0.4

3.4
0.2

20
VI = 0 V
VI = 4.5 V

MAX

UNIT
V
V

0.4
1

V
mA

40

40

1.6

1.6

mA

55

mA

55

18

12

12

mA

18

33

18

33

mA

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at VCC = 5 V, TA = 25C.
Not more than one output should be shorted at a time.

POST OFFICE BOX 655303

DALLAS, TEXAS 75265














 



SDLS029C DECEMBER 1983 REVISED JANUARY 2004

switching characteristics, VCC = 5 V, TA = 25C (see Figure 1)

PARAMETER
tPLH
tPHL

FROM
(INPUT)

TO
(OUTPUT)

SN5404
SN7404

TEST CONDITIONS
MIN
RL = 400 ,

CL = 15 pF

UNIT

TYP

MAX

12

22

15

ns

recommended operating conditions (see Note 3)

SN74LS04

SN54LS04
VCC
VIH

Supply voltage

VIL
IOH

Low-level input voltage

IOL
TA

High-level input voltage

MIN

NOM

MAX

MIN

NOM

MAX

4.5

5.5

4.75

5.25

UNIT
V
V

0.7

0.8

High-level output current

0.4

0.4

mA

Low-level output current

mA

70

Operating free-air temperature

55

125

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

VIK
VOH

SN54LS04
MIN TYP
MAX

TEST CONDITIONS

PARAMETER
VCC = MIN,
VCC = MIN,

II = 18 mA
VIL = MAX,

SN74LS04
MIN TYP
MAX

1.5
IOH = 0.4 mA
IOL = 4 mA

2.5

3.4
0.25

1.5
2.7

3.4

0.4

UNIT
V
V

0.4

VOL

VCC = MIN,

VIH = 2 V

II
IIH

VCC = MAX,
VCC = MAX,

VI = 7 V
VI = 2.7 V

0.1

0.1

20

20

IIL
IOS

VCC = MAX,
VCC = MAX

VI = 0.4 V

0.4

0.4

mA

ICCH
ICCL

VCC = MAX,
VCC = MAX,

VI = 0 V
VI = 4.5 V

IOL = 8 mA

0.25

20

100

20

0.5

V
mA

100

mA

1.2

2.4

1.2

2.4

mA

3.6

6.6

3.6

6.6

mA

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at VCC = 5 V, TA = 25C.
Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.

switching characteristics, VCC = 5 V, TA = 25C (see Figure 2)

PARAMETER
tPLH
tPHL

FROM
(INPUT)

TO
(OUTPUT)

TEST CONDITIONS

SN54LS04
SN74LS04
MIN

RL = 2 k,

POST OFFICE BOX 655303

CL = 15 pF

DALLAS, TEXAS 75265

UNIT

TYP

MAX

15

10

15

ns














 



SDLS029C DECEMBER 1983 REVISED JANUARY 2004

recommended operating conditions (see Note 3)

SN74S04

SN54S04
MIN

NOM

MAX

MIN

NOM

MAX

4.5

5.5

4.75

5.25

UNIT

VCC
VIH

Supply voltage

VIL
IOH

Low-level input voltage

0.8

0.8

High-level output current

mA

IOL
TA

Low-level output current

20

mA

70

High-level input voltage

20

Operating free-air temperature

55

125

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
TEST CONDITIONS

PARAMETER
VIK
VOH

VCC = MIN,
VCC = MIN,

II = 18 mA
VIL = 0.8 V,

VOL
II

VCC = MIN,
VCC = MAX,

VIH = 2 V,
VI = 5.5 V

IIH
IIL

VCC = MAX,
VCC = MAX,

VI = 2.7 V
VI = 0.5 V

IOS
ICCH

VCC = MAX

ICCL

VCC = MAX,
VCC = MAX,

MIN

SN54S04
TYP
MAX

MIN

SN74S04
TYP
MAX

1.2
IOH = 1 mA
IOL = 20 mA

2.5

3.4

40
VI = 0 V
VI = 4.5 V

1.2
2.7

3.4

UNIT
V
V

0.5

0.5

V
mA

50

50

mA

100

mA

100

40

15

24

15

24

mA

30

54

30

54

mA

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at VCC = 5 V, TA = 25C.
Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.

switching characteristics, VCC = 5 V, TA = 25C (see Figure 1)

FROM
(INPUT)

TO
(OUTPUT)

tPLH
tPHL

RL = 280 ,

CL = 15 pF

tPLH
tPHL

RL = 280 ,

CL = 50 pF

PARAMETER

SN54S04
SN74S04

TEST CONDITIONS
MIN

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

UNIT

TYP

MAX

4.5

4.5
5

ns
ns

SN5408, SN54LS08, SN54S08

SN7408, SN74LS08, SN74S08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SDLS033 DECEMBER 1983 REVISED MARCH 1988

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SN5408, SN54LS08, SN54S08

SN7408, SN74LS08, SN74S08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SDLS033 DECEMBER 1983 REVISED MARCH 1988

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SN5408, SN54LS08, SN54S08

SN7408, SN74LS08, SN74S08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SDLS033 DECEMBER 1983 REVISED MARCH 1988

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Revised September 1998

DM7490A
Decade and Binary Counter
General Description
The DM7490A monolithic counter contains four masterslave flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter for which the
count cycle length is divide-by-five.
The counter has a gated zero reset and also has gated setto-nine inputs for use in BCD nines complement applications.
To use the maximum count length (decade or four-bit
binary), the B input is connected to the QA output. The
input count pulses are applied to input A and the outputs

are as described in the appropriate truth table. A symmetrical divide-by-ten count can be obtained from the counters
by connecting the QD output to the A input and applying the
input count to the B input which gives a divide-by-ten
square wave at output QA.

Features
Typical power dissipation
90A

145 mW

Count frequency 42 MHz

Ordering Code:
Order Number
DM7490AN

Package Number

Package Description

N14A

14-Lead Plastic Dual-In-Line Package, JECEC MS-001, 0.300 Wide

Connection Diagram
Dual-In-Line Package

1998 Fairchild Semiconductor Corporation

DS006533.prf

www.fairchildsemi.com

DM7490A Decade and Binary Counter

August 1986

DM7490A

Function Tables

(Note 1)

Logic Diagram

BCD Count Sequence (Note 2)

Count

Outputs
QD

QC

QB

QA

BCD Bi-Quinary (5-2) (Note 3)

Count

Outputs
QA

QD

QC

QB
L

L
The J and K inputs shown without connection are for
reference only and are functionally at a high level.

Reset/Count Function Table

Reset Inputs

Outputs

R0(1)

R0(2)

R9(1)

R9(2)

QD

QC

QB

QA
L

COUNT

COUNT

COUNT

COUNT

Note 1: H = High Level, L = Low Level, X = Dont Care.

Note 2: Output QA is connected to input B for BCD count.
Note 3: Output QD is connected to input A for bi-quinary count.

www.fairchildsemi.com

Supply Voltage

Operating Free Air Temperature Range

7V

Input Voltage

0C to +70C
-65C to +150C

Storage Temperature Range

5.5V

Recommended Operating Conditions

Symbol

Parameter

VCC

Supply Voltage

VIH

High Level Input Voltage

Min

Nom

Max

4.75

5.25

Units
V
V

VIL

Low Level Input Voltage

0.8

IOH

High Level Output Current

0.8

mA

IOL

Low Level Output Current

fCLK

Clock Frequency

(Note 5)
Pulse Width
(Note 5)

tW

16

mA

32

MHz

16

15

30

Reset

15

tREL

Reset Release Time (Note 5)

25

TA

Free Air Operating Temperature

ns
ns
70

Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.
Note 5: TA = 25C and VCC = 5V.

DC Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Conditions
Parameter

Min

Typ

Max

Units

1.5

(Note 6)
VI

Input Clamp Voltage

VCC = Min, II = 12 mA

VOH

High Level Output

VCC = Min, IOH = Max

Voltage

VIL = Max, VIH = Min

VOL
II

2.4

Low Level Output

VCC = Min, IOL = Max

Voltage

VIH = Min, VIL = Max (Note 7)

Input Current @ Max

VCC = Max, VI = 5.5V

3.4
0.2

V
0.4

mA

Input Voltage
IIH

IIL

IOS
ICC

High Level Input

VCC = Max

80

Current

VI = 2.7V

Reset

40

120

Low Level Input

VCC = Max

3.2

Current

VI = 0.4V

Reset

1.6

4.8

Short Circuit

VCC = Max

DM54

-20

-57

Output Current

(Note 8)

DM74

18

57

Supply Current

VCC = Max (Note 9)

29

42

mA
mA
mA

Note 6: All typicals are at VCC = 5V, TA = 25C.

Note 7: QA outputs are tested at IOL = Max plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability.
Note 8: Not more than one output should be shorted at a time.
Note 9: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V, and all other inputs grounded.

www.fairchildsemi.com

DM7490A

Absolute Maximum Ratings(Note 4)