Reloj 24

entity contdos is

Port ( clk : in STD_LOGIC;

puls : inout STD_LOGIC_VECTOR (3 downto 0);

dis : inout STD_LOGIC_VECTOR (3 downto 0);

disp : inout STD_LOGIC_VECTOR (6 downto 0);

pulso2 : inout STD_LOGIC_VECTOR (3 downto 0);

deci : inout STD_LOGIC_VECTOR (3 downto 0);

hora : inout STD_LOGIC_VECTOR (3 downto 0);

decihora : inout STD_LOGIC_VECTOR (3 downto 0);

pulso : inout STD_LOGIC_VECTOR (3 downto 0));

end contdos;

architecture Behavioral of contdos is

signal count : integer :=1;

signal count2 : integer :=1;

begin

process(clk)

begin

if(clk'event and clk='1') then

count <=count+1;

if(count = 500000) then

pulso<= pulso +1;

count <=1;

if (pulso=9) then pulso <= pulso-9; deci<=deci+1; end if;

if (deci=5 and pulso=9) then deci <= deci-5; hora<=hora+1; end if;

if (hora=9 and deci=5 and pulso=9) then hora <= hora-9; decihora<=decihora+1; end if;

if (decihora="0010" and hora="0011" and deci="0101" and pulso="1001") then pulso<="0000"; deci<="0000";
hora<="0000";decihora<="0000"; end if;

end if;

end if;

end process;

process(clk)

begin

if(clk'event and clk='1') then

count2 <=count2+1;

if(count2 = 4000) then

pulso2<= pulso2 +1;

count2 <=1;

if (pulso2=0) then dis<="1110"; puls<=pulso;end if;

if (pulso2=1) then dis<="1101"; puls<=deci;end if;

if (pulso2=2) then dis<="1011"; puls<=hora;end if;

if (pulso2=3) then dis<="0111"; puls<=decihora; pulso2 <= pulso2-3;end if;

end if;

end if;

end process;

process(puls)begin

if puls="0000" then disp <= "0000001";

elsif puls="0001" then disp <= "1001111";

elsif puls="0010" then disp <= "0010010";

elsif puls="0011" then disp <= "0000110";

elsif puls="0100" then disp <= "1001100";

elsif puls="0101" then disp <= "0100100";

elsif puls="0110" then disp <= "0100000";

elsif puls="0111" then disp <= "0001111";

elsif puls="1000" then disp <= "0000000";

elsif puls="1001" then disp <= "0000100";

else disp <= "1111111";

end if;

end process;

end Behavioral;

net "dis[0]" loc = "f17";

net "dis[1]" loc = "h17";

net "dis[2]" loc = "c18";

net "dis[3]" loc = "f15";

net "disp[6]" loc = "l18";

net "disp[5]" loc = "f18";

net "disp[4]" loc = "d17";

net "disp[3]" loc = "d16";

net "disp[2]" loc = "g14";

net "disp[1]" loc = "j17";

net "disp[0]" loc = "h14";

net "clk" loc = "b8";

divisor jk

entity ffdivisor is

port ( pulso : inout std_logic:='0';

j,k: in std_logic;

reset:in std_logic;

clock_enable:in std_logic;

clock:in std_logic;

output: inout std_logic;

output1: inout std_logic;

output2: inout std_logic;

output3: inout std_logic;

clk : in std_logic);

end ffdivisor;

architecture Behavioral of ffdivisor is

signal count : integer :=1;

signal temp :std_logic;

signal temp1 :std_logic;

signal temp2 :std_logic;

signal temp3 :std_logic;

begin

process(clk) begin

if(clk'event and clk='1') then

count <=count+1;

if(count = 50000000) then --count = frec de reloj/frec deseada

PULSO <= not PULSO;

count <=1;

end if;

end if;

end process;

jk:process (PULSO) begin

if(PULSO'event and PULSO='1') then

if reset='0' then

temp<='0';

elsif (j='0' and k='1')then

temp<='1';

elsif (j='1' and k='0')then

temp<= '1';

elsif (j='1' and k='1')then

temp<= not (temp);

end if;

end if;

end process jk;

output <= temp;

jk1:process (output) begin

if(output'event and output='1') then

if reset='0' then

temp1<='0';

elsif (j='0' and k='1')then

temp1<='1';

elsif (j='1' and k='0')then

temp1<= '1';

elsif (j='1' and k='1')then

temp1<= not (temp1);

end if;

end if;

end process jk1;

output1 <= temp1;

jk2:process (output1) begin

if(output1'event and output1='1') then

if reset='0' then

temp2<='0';

elsif (j='0' and k='1')then

temp2<='1';

elsif (j='1' and k='0')then

temp2<= '1';

elsif (j='1' and k='1')then

temp2<= not (temp2);

end if;

end if;

end process jk2;

output2 <= temp2;

jk3:process (output2) begin

if(output2'event and output2='1') then

if reset='0' then

temp3<='0';

elsif (j='0' and k='1')then

temp3<='1';

elsif (j='1' and k='0')then

temp3<= '1';

elsif (j='1' and k='1')then

temp3<= not (temp3);

end if;

end if;

end process jk3;

output3 <= temp3;

end Behavioral;