Lenguaje VHDL

Diseo de sistemas digitales

secuenciales

Flip-Flop D
library ieee;
use ieee.std_logic_116.all;
entity d_!! is
port"
cl#$ in std_logic;
d$ in std_logic;
%$ out std_logic
&;
end d_!!;
arc'itecture arc' o! d_!! is
begin
process"cl#&
begin
i! "cl#(e)ent and cl#*(1(&
t'en
% +* d;
end i!;
end process;
end arc';
D Q Q(t+1)
0 0 0
0 1 0
1 0 1
1 1 1
D
,loc#
-
-.
-1
-/
0
6
1
/
.
"a& ,ircuit
D 1
1
"b& 2rap'ical symbol
,loc#
1
1


Flip-!lop con reset as3ncrono
library ieee;
use ieee.std_logic_116.all;
entity d_!!_reset is
port"
cl#4 reset$ in std_logic;
d$ in std_logic;
%$ out std_logic
&;
end d_!!_reset;
arc'itecture arc' o! d_!!_reset is
begin
process"cl#4reset&
begin
i! "reset*(1(& t'en
% +*(5(;
elsi! "cl#(e)ent and cl#*(1(& t'en
% +* d;
end i!;
end process;
end arc';

Flip-!lop con enable s3ncrono
library ieee;
use ieee.std_logic_116.all;
entity d_!!_en is
port"
cl#4 reset$ in std_logic;
en$ in std_logic;
d$ in std_logic;
%$ out std_logic
&;
end d_!!_en;
arc'itecture arc' o! d_!!_en is
begin
process"cl#4reset&
begin
i! "reset*(1(& t'en
% +*(5(;
elsi! "cl#(e)ent and cl#*(1(& t'en
i! "en*(1(& t'en
% +* d;
end i!;
end i!;
end process;
end arc';

1ui6

Disee un !lip-!lop 784 la tabla de )erdad se

muestra a continuaci9n.
,L: 1
7 1;
8
<1
FF87
S R Q Qt+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 X
1 1 1 X

7egistros
cl# %"=$5&
d"=$5&
reset
<1
reg_reset
library ieee;
use ieee.std_logic_116.all;
entity reg_reset is
port"
cl#4 reset$ in std_logic;
d$ in std_logic_)ector"= do>nto 5&;
%$ out std_logic_)ector"= do>nto 5&
&;
end reg_reset;
arc'itecture arc' o! reg_reset is
begin
process"cl#4reset&
begin
i! "reset*(1(& t'en
% +*"ot'ers*?(5(&;
elsi! "cl#(e)ent and cl#*(1(& t'en
% +* d;
end i!;
end process;
end arc';

7egistro de corrimiento
cl# %";-1$5&
ctrl"1$5&
d";-1$5&
reset
<1
uni)_s'i!t_reg
library ieee;
use ieee.std_logic_116.all;
entity uni)_s'i!t_reg is
generic";$ integer $* @&;
port"
cl#4 reset$ in std_logic;
ctrl$ in std_logic_)ector"1 do>nto 5&;
d$ in std_logic_)ector";-1 do>nto 5&;
%$ out std_logic_)ector";-1 do>nto 5&
&;
end uni)_s'i!t_reg;
arc'itecture arc' o! uni)_s'i!t_reg is
signal r_reg$ std_logic_)ector";-1 do>nto 5&;
signal r_neAt$ std_logic_)ector";-1 do>nto 5&;
begin
-- register
process"cl#4reset&
begin
i! "reset*(1(& t'en
r_reg +* "ot'ers*?(5(&;
elsi! "cl#(e)ent and cl#*(1(& t'en
r_reg +* r_neAt;
end i!;
end process;
-- neAt-state logic
>it' ctrl select
r_neAt +* r_reg >'en B55B4 --no op
r_reg";-/ do>nto 5& C d"5& >'en B51B4 --s'i!t le!t;
d";-1& C r_reg";-1 do>nto 1& >'en B15B4 --s'i!t rig't;
d >'en ot'ers; -- load
-- output
% +* r_reg;
end arc';

,ontadores
library ieee;
use ieee.std_logic_116.all;
use ieee.numeric_std.all;
use DEEE.8FD_LG2D,_<;8D2;ED.HLL;
entity counter is
generic ";$integer$*&;
port"
cl#$ in std_logic;
%$ inout std_logic_)ector";-1 do>nto 5&
&;
end counter;
arc'itecture arc' o! counter is
begin
process"cl#& begin
i! "cl#(e)ent and cl#*(1(& t'en
% +* %I1;
end i!;
end process;
end arc';

Ejercicio

Disee un circuito %ue muestre la cuenta de 5 a

F "a un Hert6& en uno de los cuatro displays4 la
selecci9n se reali6a empleando las seales de
entrada sel.
,ontador a 1 H6
@
,l#
7eset
8el5
8el1
an
/

,ontador upJdo>n
library ieee;
use ieee.std_logic_116.all;
use ieee.numeric_std.all;
use DEEE.8FD_LG2D,_<;8D2;ED.HLL;
entity counter_ud is
generic ";$integer$*&;
port"
cl#4 reset4 up$ in std_logic;
%$ inout std_logic_)ector";-1 do>nto 5&
&;
end counter_ud;
arc'itecture arc' o! counter_ud is
begin
process"cl#4reset4up& begin
i! "reset*(1(& t'en
%+*"ot'ers*?(5(&;
end i!;
i! "cl#(e)ent and cl#*(1(& t'en
i! "up*(1(& t'en
% +* %I1;
else
% +* %-1;
end i!;
end i!;
end process;
end arc';

KL%uinas de Kealy y Koore

Diagramas de estado

Definicin de tipos y seales

type estados is "s54 s14 s/4 s.&;
signal edo_presente4 edo_!uturo$estados;

El proceso %ue de!ine el comportamiento del

sistema4 debe considerar %ue el estado_!uturo
depende del estado_presente y de las
entradas.
process"edo_presente4a4b&

Diagramas de estado
library ieee;
use ieee.std_logic_116.all;
entity !sm is
port"
cl#4 reset$ in std_logic;
a4 b$ in std_logic;
y54 y1$ out std_logic
&;
end !sm;

process"edo_presente4a4b&
begin
y5 +* (5(; -- de!ault 5
y1 +* (5(; -- de!ault 5
case edo_presente is
>'en s5 *?
y1 +* (1(;
i! a*(1( t'en
i! b*(1( t'en
edo_!uturo +* s/;
y5 +* (1(;
else
edo_!uturo +* s1;
end i!;
end i!;
>'en s1 *?
y1 +* (1(;
i! "a*(1(& t'en
edo_!uturo +* s5;
end i!;
>'en s/ *?
edo_!uturo +* s5;
end case;
end process;
end t>o;
arc'itecture t>o o! !sm is
type estados is "s54 s14 s/&;
signal edo_presente4 edo_!uturo$ estados;
begin
process"cl#4reset&
begin
i! "reset*(1(& t'en
edo_presente +* s5;
elsi! "cl#(e)ent and cl#*(1(& t'en
edo_presente +* edo_!uturo;
end i!;
end process;

Kejor
implementaci9n
process"edo_presente4a4b&
begin
y5 +* (5(; -- de!ault 5
y1 +* (5(; -- de!ault 5
case edo_presente is
>'en s5 *?
y1 +* (1(;
i! a*(1( t'en
i! b*(1( t'en
edo_!uturo +* s/;
else
edo_!uturo +* s1;
end i!;
-- no else branc'
end i!;
>'en s1 *?
y1 +* (1(;
i! "a*(1(& t'en
edo_!uturo +* s5;
else
edo_!uturo +* s1;
end i!;
>'en s/ *?
y5 +* (1(;
edo_!uturo +* s5;
end case;
end process;
end t>o_seg_arc';
library ieee;
use ieee.std_logic_116.all;
entity !sm is
port"
cl#4 reset$ in std_logic;
a4 b$ in std_logic;
y54 y1$ out std_logic
&;
end !sm;
arc'itecture t>o_seg_arc' o! !sm is
type estados is "s54 s14 s/&;
signal edo_presente4 edo_!uturo$ estados;
begin
process"cl#4reset&
begin
i! "reset*(1(& t'en
edo_presente +* s5;
elsi! "cl#(e)ent and cl#*(1(& t'en
edo_presente +* edo_!uturo;
end i!;
end process;
555
551
111
511
515
115
151
115

Ejercicio
555
551
111
511
515
115
151
115

,ircuito anti-rebote

Disear el c9digo en VHDL para un

circuito anti-rebotes.
F
F
F
F
process "edo_presente4 pbsync& begin
pulse+*(5(;
case edo_presente is
>'en s5 *?
i! "pbsync*(5(& t'en
edo_!uturo+*s5;
else
edo_!uturo+*s1;
pulse+*(1(;
end i!;
>'en s1*?
pulse+*(5(;
i! "pbsync*(1(& t'en
edo_!uturo+*s1;
else
edo_!uturo+*s5;
end i!;
end case;
end process;
end cartasm;
library DEEE;
use DEEE.std_logic_116.all;
use DEEE.std_logic_arit'.all;
use DEEE.std_logic_unsigned.all;
entity antirebote is
port "
cl#4 reset4pbsync$ in 8FD_LG2D,;
pulse$ out 8FD_LG2D,&;
end antirebote;
arc'itecture cartasm o! antirebote is
type estados is "s54s1&;
signal edo_presente4 edo_!uturo$ estados;
begin
process "cl#4 reset& begin
i! "reset*(1(& t'en
edo_presente+*s5;
elsi! "cl#(e)ent and ,L: * (1(& t'en
edo_presente+*edo_!uturo;
end i!;
end process;