Un multiplicador de m x n bits en VHDL

Celda multiplicadora de 1 bit library IEEE; use IEEE.STD_LOGIC_1164.ALL; ENTITY celda IS PORT ( M : IN std_logic; Q : IN std_logic; PPIN : IN std_logic; CIN : IN std_logic; COUT : OUT std_logic; PPOUT : OUT std_logic ); END celda; ARCHITECTURE Comportamiento OF celda IS Definimos una seal intermedia PROD: SIGNAL prod : std_logic; BEGIN Describimos el circuito en modo puertas lgicas prod <= M AND Q; PPOUT <= (prod XOR PPIN) XOR CIN; COUT <= (prod AND PPIN) OR (prod AND CIN) OR (PPIN AND CIN); END Comportamiento; Multiplicador M(m) x Q(n) library IEEE; use IEEE.STD_LOGIC_1164.ALL; ENTITY multiplicador IS Definicin de genricos para los buses: GENERIC( m : positive := 8; q : positive := 8);

 Definicin de los puertos del componente MULTIPLICADOR: PORT( Mx : IN std_logic_vector( m-1 DOWNTO 0 ); Qx : IN std_logic_vector( q-1 DOWNTO 0 ); Px : OUT std_logic_vector( ((m+q)-1) DOWNTO 0 ) ); END multiplicador; ARCHITECTURE Behavioral OF multiplicador IS Usamos un componente celda: COMPONENT celda IS PORT ( M : IN std_logic; Q : IN std_logic; PPIN : IN std_logic; CIN : IN std_logic; COUT : OUT std_logic; PPOUT : OUT std_logic ); END component; Definimos dos tipos auxiliares para controlar los buses intermedios: TYPE matrix IS ARRAY (q-1 DOWNTO 0) OF std_logic_vector (m DOWNTO 0); TYPE matrix1 IS ARRAY (q DOWNTO 0) OF std_logic_vector (m DOWNTO 0); SIGNAL c : matrix; Bus matricial de acarreos SIGNAL pp : matrix1; Bus matricial de productos parciales BEGIN Inicializacin de los primeros productos parciales a cero pp(0) <= ( others => 0 ); fila : FOR i IN (q-1) DOWNTO 0 GENERATE Al inicio de cada fila, el acarreo q introducimos es cero c(i)(0) <= 0; Al final de cada fila, el pp_salida es el de entrada de la fila de abajo pp(i+1)(m) <= c(i)(m);

columna : FOR j IN (m-1) DOWNTO 0 GENERATE Instanciamos cada celda: celda_matriz : celda PORT MAP( M => Mx(j), Q => Qx(i), PPIN => pp(i)(j+1), CIN => c(i)(j), COUT => c(i)(j+1), PPOUT => pp(i+1)(j) ); END GENERATE; END GENERATE; Recorremos todas las posibles salidas (los 16 bits) salidas : FOR i IN (m+q-1) DOWNTO 0 GENERATE salidas_1 : IF ( i < q ) GENERATE Px(i) <= pp(i+1)(0); END GENERATE; salidas_2 : IF ( i > (m-1) ) GENERATE Px(i) <= pp(m)( i-(q-1) ); END GENERATE; END GENERATE; END Behavioral;