Cargas by Minh Khang

A 6.5–12.5-Gbs Half-Rate Single-Loop All-Digital CDR

A 6-Gbs Wireline Receiver Equalizer and CDR

A_5.0-to-12.5-Gb_s_1.7-pJ_b_0.66-s_Lock-time_Reference-less_Sub-sampling_CDR_with_Beat_Detection_FLL_in_28nm_CMOS

A_1.6823.2-Gb_s_Reference-Less_Half-Rate_Receiver_With_an_ISI-Tolerant_Unlimited_Range_Frequency_Detector

A_1.45-pJ_b_16-Gb_s_Edge-Based_Sub-Baud-Rate_Digital_CDR_Circuit

A_1.1-pJ_b_8-to-16-Gb_s_Receiver_With_Stochastic_CTLE_Adaptation

A_0.0285-mm2_0.68-pJ_bit_Single-Loop_Full-Rate_Bang-Bang_CDR_Without_Reference_and_Separate_FD_Pulling_Off_an_8.2-Gb_s_s_Acquisition_Speed_of_the_PAM-4_Input_in_28-nm_CMOS

A 0.8-to-6.5 Gbs Continuous-Rate Reference-Less Digital CDR With Half-Rate Common-Mode Clock-Embedded Signaling

A 0.5-to-2.5 Gbs Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance

180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance

250 Mbps–5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 um CMOS

0.6–2.7-Gbs Referenceless Parallel CDR With a Stochastic Dispersion-Tolerant Frequency Acquisition Technique

radio-frequency