By Santhosh Doopati (08J91A0442) Department of Electronics & Communications Vidya Bharathi Institute of Technology, Jangaon.

CONTENTS

Introduction History Main Challenges in Todays Architecture Sequential Semantics ILP Branch Unpredictability Memory dependencies

Memory Latency NEED FOR ITANIUM IA-64 Architecture Performance Features EPIC Overall Architecture Applications Conclusion References

INTRODUCTION
Itanium is a 64-bit microprocessor
It has IA-64 architecture The Itanium architecture is based on

explicit instruction-level parallelism execute up to six instructions per clock cycle

HISTORY
In 1994, Hewlett-Packard and Intel Corporation

agreed to jointly design EPIC Using EPIC concepts, HP and Intel then jointly defined Itaniums 64-bit Itanium Processor architecture The first Itanium processor, codenamed Merced, was released in 2001 Later other versions of Itanium are released

THE MAIN CHALLENGES IN TODAYS ARCHITECTURE

Sequential Semantics of the ISA
Low Instruction Level Parallelism(ILP) Unpredictable Branches, Memory dependencies Ever Increasing Memory Latency, Ever increasing

Memory Limited Resources Procedure call,Loop pipelining Overhead

Sequential Semantics
High performance needs parallel execution which in

turn needs independent instructions. So independent instructions must be rediscovered by the hardware Consider the code: Dependent Independent add r1=r2,r3 add r1=r2,r3 sub r4=r1,r2 sub r4=r11,r2 shl r5=r4,r8 shl r5=r14,r8

Low Instruction Level Parallelism(ILP)

Wider machines need more parallel instructions. So

ILP across the branches need to be exploited.

Branch Unpredictability
Branch predictions are not perfect in older processors

Memory dependencies
Usually load instructions are at the top of a chain of

instructions. ILP requires moving these loads. Store instructions are also a barrier

Memory Latency
Though the speed of A.L.U, decoders and other

execution units have increased with time, the advances in technologies related to memories is not in pace with it

NEED FOR ITANIUM

Computer applications are dealing with ever-

increasing quantities of data Itaniums ability to address a flat 64-bit memory address space in the millions of gigabytes has been the focus of attention Epic architecture speculation, predication, large register files, a register stack and advanced branch architecture fast interrupt response

IA-64 ARCHITECTURE PERFORMANCE FEATURES

Explicitly Parallel Instruction Semantics
Predication Control/Data Speculation Massive Resources(registers,memory) Register Stack and its Engine Memory Hierarchy Management Support Software Pipelining Support

EPIC
EPIC stands for Explicitly Parallel Instruction

Computing EPIC technology enables greater instruction level parallelism than previous processor architectures, supporting higher levels of performance in targeted application segments EPIC is based on a unique combination of innovative features such as predication, speculation and explicit parallelism enabling world-class performance for the high-end enterprise class of computing

EPIC Instruction Word Format

SPECULATION
The latency of memory problem is solved by technique

called Speculation Speculation initiates loads from memory earlier in the instruction stream

Predication
Predication is a compiling technique used in the Itanium

that optimizes or removes branching code Minimize the time it takes to run if-then-else situation and uses processor width to run both the 'then' and 'else' in parallel Consider code: I1:mov r2,r1 I2:cmp r2,r1 I3:if (r1==r3) I4:add r5,r7 I5:else I6:mul r8,r9

Cache
Uses 3-level cache L1,L2,and L3

L1- 16KB L2- 96kb L3- 2mb or 4mb

Registers
128 64-bit general purpose registers
128 82-bit floating point registers 64 1-bit predicate registers 8 64-bit branch registers 8 64-bit kernel registers 64-bit CFM register 64-bit IP, Instruction Pointer

Overall Archtecture

SPECIFICATIONS
Physical Characteristics 25.4M transistors .18micron CMOS process 6 metal layers Floating Point Units 2 extended and double precision FMACs (Floatingpoint Multiply Add Calculators) 2 additional single precision FMACs 6.4 GFLOPS of peak single precision floating point performance total at 800MHz

Applications
Databases
High-Performance Computing Enterprise Resource Planning, Supply Chain

Management Mechanical Computer Aided Engineering(MCAE),Intensive Custom Applications(financial, petroleum, others) Business Intelligence Security Transactions

COMPATIBILITY
The Itanium is fully x86 compatible in hardware.

Applications and operating systems can run without any changes. A decoder internal to the CPU decodes x86 instructions into EPIC instructions

CONCLUSION
First processor with Itanium architecture. Developed,

manufactured, and marketed by Intel The Itanium has a complex, forward looking processor family that holds promise for huge gains in processing power. The processor uses the entirely new EPIC architecture that has the potential to deliver large improvements in processor parallelism

REFERENCES
www.intel.com
www.intel.com/design/itanium/manuals/iiasdmanual.

htm www.devoloper.intel.com www.en.wikipedia.org www.ieee.org

QUESTIONS?