Synchronization enhancement using IEEE 1588

CONTENTS
Introduction Problem Definition Aim Design Approach Implementation Result observations Conclusion References

Introduction
Data communication in industries are defined by a fixed structured network. These networks uses Physical link for Data communication. More accurate than wireless networks. Cost effective under distributed system having sensitive data transmission. commonly used in industrial communication.

Problem Definition
Even though wired network are currently been used for reliable data transfer they are non-synchronous in nature due to multiple sources. In industry multiple units transfer information simultaneously. Synchronizing these multiple links result in inconsistency problem. Inconsistency result in wrong operation reducing system performance. Priority based or FCFS communication results in delayed communication.

Aim
To develop an approach for simultaneous data transfer in multi source design in a faster way. Develop IEEE-1588 standards to realize a fast mode of communication. To develop a Best Master clock approach for high speed clock synchronization. To develop the approach for Ethernet link points with multiple node points. To develop the data communication model with and without synchronizing protocol for time performance evaluation.

Design Approach
For the realization of the suggested approach following communication architecture is been used as mentioned. communication Model:
IU IU
LP LP LP LP

Network Processor

IU
IU

IU-Individual Units

LP-link points (Ethernet links)

Links are the communication points for NP from IU. They consist of Ethernet communication logic. Each link point get synchronized from the NP unit individually. Communicate with NP using Internet protocol. Each source communicate with the receiving point at different data rate. Network processor is synchronized with the individual link points using their existing operational time period.

 The network processor get synchronized with the operational clock cycle based on the transmitting node frequency. As the nodes are working in different clock cycle the datas are communicated in a time delay. The transmission or reception may be in round robin fashion or priority based approach. In both the approach the system is required to be in queue until the turn comes.

 In case of a network having sensors output which are more sensitive for operation a delay may result in a abrupt operation. To achieve a faster data transfer these networks are designed with a new synchronizing protocol called IEEE-1588 protocol. IEEE-1588 protocol is a clock synchronization protocol under different source mode communication. The protocol works on the concept of the best master clock operation.

IEEE 1588 SYNCHRONIZATION

The synchronization of the 1588 protocol is defined as; Step 1: Organize the clocks into a master-slave hierarchy (based on observing the clock property information contained in multicast Sync messages) Step 2: Each slave synchronizes to its master (based on Sync, delay_Req, Follow-Up, and Delay_Resp messages exchanged between master and its slave)

Offset and Delay measurement For the chosen delay all the slave clocks are updated to this offset value to synchronize the received data into a common master clock frequency.

SYNCHRONIZATION APPROACH

For the synchronization of the nodes a communication approach is suggested as explained; Sync Messages: Issued by clocks in the Master state Contain clock characterization information Contain an estimate of the sending time (~t1) When received by a slave clock the receipt time is noted Can be distinguished from other legal messages on the network For best accuracy these messages can be easily identified and detected at or near the physical layer and the precise sending (or receipt) time recorded.

 Follow-Up messages: Issued by clocks in the Master state Always associated with the preceding Sync message Contain the precise sending time= (t1)as measured as close as possible to the physical layer of the network When received by a slave clock the precise sending time is used in computations rather than the estimated sending time contained in the Sync message

 Delay_Req Messages: Issued by clocks in the Slave state The slave measures and records the sending time (t3) When received by the master clock the receipt time is noted (t4) Can be distinguished from other legal messages on the network For best accuracy these messages can be easily identified and detected at or near the physical layer and the precise sending (or receipt) time recorded

 Delay_Resp messages: Issued by clocks in the Master state Always associated with a preceding Delay_Req message from a specific slave clock Contain the receipt time of the associated Delay_Req message (t4) When received by a slave clock the receipt time is noted and used in conjunction with the sending time of the associated Delay_Req message as part of the latency calculation

MASTER CLOCK SELECTION

A clock at startup listens for a time Sync_receipt_timeout A master clock (clock in the PTP_MASTER state) issues periodic Sync messages (period is called the sync interval) A master clock may receive Sync messages from other clocks (who for the moment think they are master) which it calls foreign masters Each master clock uses the Best Master Clock algorithm to determine whether it should remain master or yield to a foreign master. Each non-master clock uses the Best Master Clock algorithm to determine whether it should become a master.

SYSTEM DESIGN For the development of the suggested design architecture the a multi port Ethernet points with link unit is used as shown below.
LINK
Ethernet Transmitter 1 Ethernet Transmitter 2 Ethernet Transmitter 3 Ethernet Transmitter 4

Ethernet Receiver 1

Ethernet Receiver 2

Ethernet Receiver 3

Ethernet Receiver 4

Interface

(IEEE 1588)

Network Processor

LINK POINT
The Link points are designed with the Ethernet logic. The transmission block is as shown below;
S_out Parallel -Serial P2s_en FIFO rd/wr F_en

H O S T

CRC

Generator Crc_en Fr_en

Frame Builder status

Data length

Controller

Transmission Unit

 The Ethernet unit communicate using the data frame structure as shown below;
SOF Preamble Type Source Address Destination Address Data Length EOF

Data

3 bits

7 bits

4 bits

8 bits

8 bits

4 bits

variable

2 bits

Start-of-frame delimiter (SOF) The SOF is an alternating pattern of ones and zeros, ending with two consecutive 1-bits indicating that the next bit is the left-most bit in the left-most byte of the destination address. Preamble (PRE) The PRE is an alternating pattern of ones and zeros that tells receiving stations that a frame is coming, and that provides a means to synchronize the frame-reception portions of receiving physical layers with the incoming bit stream. TypeThe Type field is used to indicate if the packet is control packet or data packet.

Source addresses (SA) The SA field identifies the sending station. The SA is always an individual address and the left-most bit in the SA field is always 0. Destination address (DA) The DA field identifies which station(s) should receive the frame. The left-most bit in the DA field indicates whether the address is an individual address (indicated by a 0) or a group address (indicated by a 1). The second bit from the left indicates whether the DA is globally administered (indicated by a 0) or locally administered (indicated by a 1). The remaining 46 bits are a uniquely assigned value that identifies a single station, a defined group of stations, or all stations on the network. LengthThis field indicates either the number of MAC-client data bytes that are contained in the data field of the frame DataIs a sequence of n bytes of any value, where n is less than or equal to 8. Frame check sequence (FCS) This sequence contains a 32-bit cyclic redundancy check (CRC) value, which is created by the sending MAC and is recalculated by the receiving MAC to check for damaged frames. The FCS is generated over the DA, SA, Length/Type, and Data fields.

S_in

Serialparallel Rd/wr

FIFO F_en Fr_en

Frame reader Match

Address match logic

S2p_en

FCS

crc checker Crc_en

controller Crc_err

Receiver unit
Ethernet receiver receives the data frame and the frame reader is used to divide the frame into the 7 fields transmitted. Address match logic is used to match the destination address with the address of the receiver and if it matches then only the frame is accepted. CRC checker is used to check for the faults in the data frame and if any then the frame is discarded. Controller is used to deliver control signals to all the units at correct intervals so that the receiver performs its operation correctly.

Communication Unit With IEEE-1588

LINK
Ethernet Transmitter 1 Ethernet Transmitter 2 Ethernet Transmitter 3 Ethernet Transmitter 4

Ethernet Receiver 1

Ethernet Receiver 2

Ethernet Receiver 3

Ethernet Receiver 4

INTERFACE Synchronization Unit

Clock Generation Unit

Network Processor

Frame format for IEEE-1588 protocol

Synchronization Preamble SOF Type Source Address 8 bits Destination Address 8 bits Data Time stamp 7 bits Prop delay 4 bits 2 bits EOF

3 bits

7 bits

4 bits

8 bits

The frame consists of 2 internal fields one is the time stamp and the second is the propagation delay. These two fields specify the two values that is the offset value and the propagation delay value of the slave clocks from the master clock. The devices which receive this packet will take these two fields and corrects its clock to the master clock.

Result observations

Simulation result of the communication model showing the communication time for the designed unit in a nonsynchronized mode. The observed time for the communication of 4 nodes data to the receiver unit is observed as, 5580ns.

Simulation result of the communication model showing the communication time for the designed unit with synchronization Protocol. The observed time for the communication of 4 nodes data to the receiver unit is observed as, 1445ns.

Observations
dlc=3bytes Best master clock (BMC)= min ( tstamp ) Default clock = ck1 (under asynchronous mode communication ) Frequency selection method = round robin Total number of communicating nodes = 4 Total amount of data generated per node = 3 bytes Total amount of expected data in processor = 12 bytes Total time taken = 5580 ns (under non synchronous round robin based comm) (total time = processing time + comm Time) Total time taken = 1445 ns (under 1588 synchronous mode comm) Total time saved (ts)= 4135 ns Total clock cycles saved = ts / BMC = 4135 / 10 413 cycles

Implementation

without IEEE 1588

with IEEE 1588

Logical Implementation of the developed system on targeted FPGA. (xc3s1500-5fg456)

Conclusion
The IEEE 1588 protocol has been designed, verified functionally in the VHDL simulator, and synthesized on Xilinx Project Navigator 9.1. The functional verification were made and the total communication time were observed. It is observed that the system with IEEE-1588 protocol works at a faster rate as compared to the existing system. The overall resource required for the implementation is about 5000 gate count more than the existing link units. The operable frequency with which the system can operate under practical condition is observed to be 68.885MHz.

References
[1] IEEE 1588* in Network Processors for Next-Generation Industrial Automation Solutions, Puneet Sharma, Technical Marketing Engineer, Digital Enterprise Group, Intel Corporation, May 2005. [2] Special Focus: Understanding the IEEE 1588 Precision Time Protocol Developer Zone, National Instruments, February 2006.. [3] Hardware-Assisted IEEE 1588* Implementation in the Intel IXP46X Product Line, White Paper, March 2005. [4] IEEE 1588 : Running Real-time on Ethernet, Dirk.S.Mohl, Hirschmann Electronics, The Online Industrial Ethernet Book, Issue 17, November 2003.

Thank You