Design of a Digital Alarm Clock Using VHDL

Submitted by
NAME ARKADIP GHOSH JOYSREE MUKHERJEE SOUMYAJIT DAS BIKIRON JASU SANNIV GHOSH DASTIDAR JIT PAL ROLL NO 08144003039 08144003036 08144003010 08144003044 08144003051 08144003032

In partial fulfillment for the award of the degree Of BACHELOR OF ENGINEERING IN ELECTRONICS & COMMUNICATION ENGINEERING Under the guidance of Mr. Mridanku Shekhar Pramanick (Assist. Prof. ECE Dept, ITME)

INSTITUTE OF TECHNOLOGY & MARINE ENGINEERING

What Is Clock??
 Instrument used to indicate, keep, and co-ordinate time  The biggest digital clock is the Lichtzeitpegel  Josef Pallweber produced a mechanic-digital clock model in 1956  In 1970, the first digital wristwatch with an LED display was massproduced

Types of clock
    Analog clocks Indicate time using angles. Italian 6 hour clock was developed in the 18th century. Type of analog clock is the sundial.

 Digital clocks  Display a numeric representation of time.  Most digital clocks use an LCD, LED, or VFD display.  Auditory clocks  Auditory clocks present the time as sounds.

Aim of Project
 Displays time in hours and minutes and minutes and second mode  Implement timer to the display device available on the XILINX Spartan-3 FPGA Starter Kit

 We set clock with real time form from the external slide switches and push button available on the XILINX Spartan-3 FPGA Starter Kit  A Calendar  In the final phase we will implement alarm in this clock

Adding modes to the Clock

HH:MM mode: The clock will display Hour and Minute components of the time. MM:SS mode: The clock will display Minute and Second components of the time. Alarm mode: We set our clock in a time and the buzzer will rang out.

What is FPGA??
 Ability to reconfigure its circuitry for a desired application or function at any time after manufacturing  Adaptive hardware that continuously changes in response to the input data or processing environment  Combination of general-purpose processors and ASICs  Quick reconfiguration time, in order of 100 QS to 1 mS

Basic FPGA Design and Structure

 A myriad of Configurable Logic Blocks  The CLBs may have functionality of either adding or comparing two numbers  Connection between CLBs are established through signal controlled grid connections

'Field Programmable' meansmeans Program defined by user rather than the manufacturer  Program can be burned permanently or semi permanently  Program can be loaded from an external memory each time the device is powered up

Creation of FPGA Programs

Advantages of FPGA
 Reconfiguration ability enables performing specific computational tasks.

 Certain function implementations lead to reduction in die area Easy to implement Die area is not a constraint

Disadvantages of FPGA
 Hardware is not ASIC which can lead to non-optimized performance and density.  Reconfiguration time is longer compared to loading software  High power consumption during reconfiguration

Switches
 Slide Switches: Spartan-3 Starter Kit board has eight slide switches

 Push Button Switches: Spartan-3 Starter Kit board has four momentary-contact push button switches

LEDs
 Spartan-3 Starter Kit board has eight individual surface-mount LEDs located above the push button switches.

 The cathode of each LED connects to ground via a 270 ohm resistor

Clock Source
Spartan-3 Starter Kit board has a dedicated 50 MHz clock oscillator source.

FourFour-Digit, Seven-Segment LED SevenDisplay

 Spartan-3 Starter Kit board has a four-character, seven segment LED display controlled by FPGA user-I/O pins

 Each digit shares eight common control signals to light individual LED segments A through G and DP

FPGA Connections to SevenSevenSegment Display

lists the FPGA connections that drive the individual LEDs comprising a seven segment character List the connections to enable a specific character

The patterns required to display hexadecimal characters

LED Control Signals

Why VHDL??
 Multipurpose  Portable  IEEE and ANSI standard  Medium between chip vendors and CAD tool users

Part wise Design of Digital Clock

Design counter, clock generator and real time set up

entity clk is port( clk50 tset ssin rst sec min hr end clk; architecture Behavioral of clk is signal bcdint_s : std_logic_vector(7 downto 0):=(others=>'0') ; signal bcdint_hm : std_logic_vector(15 downto 0):=(others=>'0') ; signal sys : std_logic_vector(1 downto 0):=(others=>'0') ; begin process (clk50,rst,tset,ssin) begin if rst = '1' then : in std_logic ; : in std_logic_vector(1 downto 0); : in std_logic_vector(7 downto 0); : in std_logic; :out std_logic_vector(7 downto 0); :out std_logic_vector(7 downto 0); :out std_logic_vector(7 downto 0));

bcdint_s <= (others => '0') ; bcdint_hm <= (others => '0') ; elsif tset="01" then bcdint_hm(7 downto 0) <= ssin; elsif tset="10" then bcdint_hm(15 downto 8) <= ssin; elsif clk50'event and clk50 = '1' then if sys(0) = '0' then if bcdint_s(3 downto 0) = "1001" then if bcdint_s(7 downto 4) = "0101" then if bcdint_hm(3 downto 0) = "1001" then if bcdint_hm(7 downto 4) = "0101" then if (bcdint_hm = "0010001101011001" and bcdint_s = "01011001" ) then bcdint_hm <= "0000000000000000" ; elsif (bcdint_hm(11 downto 8) = "1001") then bcdint_hm <= (bcdint_hm(15 downto 12) + 1) & "000000000000" ; else bcdint_hm <= bcdint_hm(15 downto 12) & (bcdint_hm(11 downto 8) + 1) & "00000000" ; end if ;

else bcdint_hm <= bcdint_hm(15 downto 8) & (bcdint_hm(7 downto 4) + 1) & "0000" ; end if ; else bcdint_hm <= bcdint_hm(15 downto 4) & (bcdint_hm(3 downto 0) + 1); end if ; bcdint_s <= "00000000" ; else bcdint_s <= (bcdint_s(7 downto 4) + 1) & "0000" ; end if ; else bcdint_s <= bcdint_s(7 downto 4) & (bcdint_s(3 downto 0) + 1) ; end if ; end if; end if ; end process ;

process(rst,clk50) begin if rst = '1' then sys <= (others => '0') ; elsif clk50'event and clk50 = '1' then sys <= sys + 1 ; end if ; end process ; sec<=bcdint_s; min<=bcdint_hm(7 downto 0); hr<=bcdint_hm(15 downto 8); end Behavioral;

WAVEFROM

Moved the led counter every second in both direction

entity led_1 is port ( clk50 rst led_out end led_1; : in std_logic ; : in std_logic; : out std_logic_vector(7 downto 0));

architecture Behavioral of led_1 is signal c : integer:=0; signal sys : std_logic_vector(1 downto 0):="00" ; signal led : std_logic_vector(7 downto 0):="00000001" ; begin -- moved the led counter every second. process (clk50, rst) begin if rst = '1' then led <= "00000001" ; c<=0;

elsif clk50'event and clk50 = '1' then if (sys(1 downto 0) = "10")then if(c<7) then led <= led(6 downto 0) & led(7) ; c<=c+1; elsif (c<14) then led <= led(0) & led(7 downto 1) ; c<=c+1; else c<=0; end if; end if ; end if ; end process ;

process(rst,clk50) begin if rst = '1' then sys <= (others => '0') ; elsif clk50'event and clk50 = '1' then sys <= sys + 1 ; end if ; end process ; led_out<=led; end Behavioral;

WAVEFROM

Assigning Pin Location Constraints

 Verify that clock is selected in the Sources window  Double-click the Floor plan Area/IO/Logic  Select the Package View tab  In the Design Object List window, enter a pin location for each pin in the Loc column  Select File Save

Download Design to Spartan-3 kit Spartan Connect the 5V DC power cable to the power input on the demo board  Connect the download cable between the PC and demo board  Select Implementation from the drop-down list in the Sources window  Select counter in the Sources window  In the Welcome dialog box, select Configure devices using BoundaryScan (JTAG)  Verify that automatically connect to a cable and identify BoundaryScan chain is selected Click Finish

 If you get a message saying that there are two devices found, click OK to continue.  The devices connected to the JTAG chain on the board will be detected and displayed in the iMPACT window.  The Assign New Configuration File dialog box appears. To assign a configuration file  If you get a Warning message, click OK.  Select Bypass to skip any remaining devices.  Right-click on the xc3s200 device image, and select Program... The Programming Properties dialog box opens.  Click OK to program the device.  When programming is complete, the Program Succeeded message is displayed

CONCLUSION & FUTURE SCOPE

 What has been achieved in phase I  Using phase We study and results for phase II that is- phase we will implement alarm in this clock, A Calendar

REFERENCES
BOOKS: Vikas Publishing House PVT LTD- Digital Circuits And Design, Edition 2007(3rd), Reprint in 2009, by S.Salivahanan and S.Arivazhagan J.Bhasker, A VHDL Primer, Pearson publication /BS Publications www.xilinx.com Spartan-3 FPGA Starter Kit Board User Guide