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Learning Objectives
Describe in simple terms the fetch / decode / execute / reset cycle and the effects of the stages of the cycle on specific registers.
Program Counter Memory Address Register Memory Data Register Current Instruction Register
MAR
MDR
CIR
Idle Registers
Note that during the Fetch - Decode Execute - Reset cycle demonstrated on the following slides, some registers are idle (not being used). This will be discussed and resolved in the next lesson.
Fetch
CPU
MAR
Memory
Copy of instruction in memory address held in MAR
MDR
Instruction
CIR
Decode
CPU
MAR
PC
MDR
CIR
Split instruction into operation code & address if present. Then decode operation code.
Execute
CPU
MAR
PC
MDR
CIR
Jump Input / Load (number directly) Input / Load (from memory) Store Add (a number directly) Add (a number from memory) Output (directly from accumulator) Output (from memory)
Jump instruction
Execute Diagram
Execute Jump
CPU
MAR
PC
MDR
CIR
Back to list of instructions
CPU
PC MAR MDR Accumulator
Number inputted / to be loaded.
CIR
Back to list of instructions
You will find that the contents of the MDR may be modified for similar reasons during other later instructions.
Back to list of instructions
CPU
MAR
Memory
Copy of data in address held in MAR
PC
You will find that the contents of the MAR may be modified for similar reasons during other later instructions.
Back to list of instructions
Store instruction
Execute Diagram Assume data has either been inputted, loaded (directly or from memory) or a calculation has been performed. Any of the above will mean there is data in the accumulator and it is this data that will be stored.
Execute Store
CPU
MAR
Memory
Copy of data in MDR stored in memory address held in MAR
PC
CPU
PC MAR
MDR
ALU
Accumulator
NB. The ALU now does the arithmetic. Accumulator value is now the result of the addition. i.e. Accumulator = Accumulator + contents of MDR
Number to be added.
CIR
Back to list of instructions
CPU
MAR
Memory
Copy of number in memory address held in MAR
PC
MDR
ALU
Accumulator
NB. The ALU now does the arithmetic. Accumulator value is now the result of the addition. i.e. Accumulator = Accumulator + contents of MDR
CIR
Back to list of instructions
CPU
PC
Output data in accumulator
MAR MDR
Accumulator
CIR
Back to list of instructions
Memory
CPU
MAR
Copy of data in memory address held in MAR
PC
MDR
Accumulator
CIR
Back to list of instructions
Reset
CPU
PC
Cycle is reset (restarted) by passing control back to the PC.
Idle Registers
Note that during the Fetch - Decode Execute - Reset cycle demonstrated on the previous slides, some registers were idle (not being used). This will be discussed and resolved in the next lesson.
i.e.
What you will have to do when answering an exam question.
So that the control unit can fetch the instruction from the right part of the memory.
2. Copy the instruction/data that is in the memory address given by the MAR into the MDR. Fetch
MDR is used whenever anything is to go from the CPU to main memory, or vice versa. So that it contains the address of the next instruction, assuming that the instructions are in consecutive locations.
3. Increment the PC by 1.
4. Load the instruction/data that is now in the MDR into the CIR.
Thus the next instruction is copied from memory -> MDR > CIR.
5. Contents of CIR split into operation code and address if present e.g. store, add or jump Decode instructions. 6. Decode the instruction that is in the CIR.
6. Execute the instruction but what is involved in this depends on the instruction being executed (there are several different instructions you need to know about). If the instruction is a jump instruction then
Load the address part of the instruction in the CIR into the PC.
Execute
If the instruction is an input / load (directly) instruction then take data input and place in accumulator. If the instruction is a load (from memory) instruction.
Copy address part of the instruction (to load from) in the CIR into MAR. Copy data from memory address held in MAR to MDR. Copy data in MDR into accumulator.
Copy address part of the instruction (to store in) in the CIR into MAR. Copy data in accumulator to MDR. Copy data in MDR into memory address held in MAR.
Execute
Copy address part of the instruction (of number to add) in the CIR into MAR. Copy number from memory address held in MAR into MDR. Add number in MDR to number in accumulator (accumulator will now hold the result).
If the instruction is an output (directly from accumulator) then output number in accumulator.
Execute
Reset
7.
Plenary
Describe the fetch / decode part of the fetch / decode / execute / reset cycle, explaining the purpose of any special registers that you have mentioned.
Plenary
Contents of PC loaded into MAR PC is incremented Contents of address stored in MAR loaded into MDR Contents of MDR loaded into CIR Instruction in CIR is decoded. PC (program counter) stores the address of the next instruction to be executed. MAR (memory address register) holds the address in memory that is currently being used MDR (memory data register) holds the data (or instruction) that is being stored in the address accessed by the MAR. CIR (current instruction register) holds the instruction which is currently being executed.