CSCE 211 Digital Design

Lecture 16
Programmable Logic Devices
PROMs, PLAs, PALS, …
Topics
 Review of shift registers, ROMS
 ALU Design

Readings: 8.5, 9.1

October 19, 2010

Overview
Last Time
 State machine construction
 $.35 toll booth (=coke machine with no change)

New
 Two–dimensional ROMs
 Overview Field Programmable Gate Arrays

Next Time:
 Test 2 : Thursday Nov 9, Review ???

CSCE 211H Fall 2010

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Read Only Memory Functionality
Figure 9-1

Nota Bene! Figure are from last years version

In which this chapter was Chap 10 now this is in Chap 9.
CSCE 211H Fall 2010
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3-Input 4-Output ROM

OR D0
A0
A0 OR D1
A1 3x8
decoder OR D2
A2
OR D3 CSCE 211H Fall 2010
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Construction of a 2 x n ROM

d0
d1
A0 2x4 d2
A1 decoder
d3

Zap some connections

during construction
Denoted “x”

Y0 Y1 Y2 Yn-1

CSCE 211H Fall 2010

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2x4 Decoder with Output-Polarity Control
Figure 9-2

CSCE 211H Fall 2010

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Implementing
Implementing Arbitrary
Arbitrary Boolean
Boolean functions
functions with
with ROMs
ROMs

CSCE 211H Fall 2010

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Multipliers in ROM
Figure 9-4

CSCE 211H Fall 2010

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Fig 9-5 Logic Diagram of 8x4 diode ROM

74LS138 =1-OF-8 DECODER/

DEMULTIPLEXER

CSCE 211H Fall 2010

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 Two-Dimensional Decoding

CSCE 211H Fall 2010

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 Field Programmable Gate Arrays
Xilinx Spartan-3 FPGA family.
 Download circuits onto the chip
 FPGA
 Field
 Programmable
 Gate array

Spartan-3 FPGAs with 1 million system gates for under

$12.00

CSCE 211H Fall 2010

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 Xilinx FPGA

CSCE 211H Fall 2010

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 Configurable Logic Blocks

CSCE 211H Fall 2010

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 LUTs – Look Up Tables
Circuits are built in FPGA using Look Up Tables or
LUTs.
A lut is just a sequence of storage cells and then a
collection of multiplexers select which storage cell is
routed to the output,

CSCE 211H Fall 2010

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 LUT Structure
(Pawel
(Pawel Chodowiec
Chodowiec -- Architecture
Architecture of
of Xilinx
Xilinx FPGA devices))
FPGA devices

CSCE 211H Fall 2010

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 CLB for Functions of 5 variables

CSCE 211H Fall 2010

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 DL – Diode Logic Gates
Or Gate

AND Gate

Diagrams from play-hookey.com CSCE 211H Fall 2010

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 74x138 – 3x8 Decoder / Demultiplexer
x

How a demux?

CSCE 211H Fall 2010

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 Two-Dimensional Decoding Again
128x1 ROM
High order 3
address
bits used to
select one
of 8 words
Low order 4
bits used to
select one
of these
bits for the
output

CSCE 211H Fall 2010

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 Memory (RAM) Access
x

CSCE 211H Fall 2010

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 ROM Timing Diagrams

CS_L – Chip select (Low)

OE_L -
CSCE 211H Fall 2010
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 EPROMS
x

CSCE 211H Fall 2010

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 Hooking Microprocessor to ROM
x

CSCE 211H Fall 2010

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 Programmable Logic Array - PLA
x

CSCE 211H Fall 2010

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 PLA implementation
x

CSCE 211H Fall 2010

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 PLA Example: O1 = …
x

CSCE 211H Fall 2010

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 Programmable
xArray Logic –
PAL16L8

CSCE 211H Fall 2010

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 CSCE 211H Fall 2010
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 CSCE 211H Fall 2010
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 Last Year’s Test2, Another test is on
Website/Handouts/test2Short.pdf
1. Carry Lookahead
2. 4 bit multi-function register
3. Sequential design problem
4. State Diagram  transition table
5. Transition table  excitation table
6. Xilinx
7. Missing?
a. ROM: how they work?
b. Design ROM to implement circuit (diagram)
c. PLAs, PALS
d. ???
CSCE 211H Fall 2010
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