Accessing I/O devices

V. Saranya
AP/CSE
Sri vidya College of Engg & Tech
• I/O devices accessed through I/O interface.
• Requirements for I/O interface:
– CPU communication
– Device communication
– Data buffering
– Control and timing
– Error detection.
CPU Communication:
• Processor sends commands to the I/O system
which are generally the control signals on the
control bus.
• Exchange of data between the processor and
the I/O interface over the data bus.
• Check whether the devices are ready or not.
Data Buffering:
• Data transfer rate is too high .
• Data from processor and memory are sent to
an I/O interface, buffered and then sent to the
peripheral device at its data rate.
Error Detection:
• I/O interface is responsible for error detection
• Used to report errors to the processor.
• Types of errors:
– Mechanical, electrical malfunctions, bad disk
track, unintentional changes.
 I/O interface Block diagram
Data Register
Data Data
Lines

Status/Control Register

Address Lines Status

Address
Decoder External
Device
Interface Control
Control Lines Logic
• Data Register: holds the data being
transferred to or from the processor.
• Status/Control Register: contains
information relevant to the operation.
• Data and status/control registers: are
connected to the data bus.
• Address decoder: enables the device to
recognize its address.
 I/O interface for Input Device
Address Lines
BUS
Data Lines

Control lines

Data & Status

Address Decoder Control Circuits
Registers

I/O
interface
Input Device
 I/O interface for Output Device
Address Lines

BUS
Data Lines

Control lines

Data & Status

Address Decoder Control Circuits
Registers

I/O
interface
Output Device
I/O interface Techniques
 I/O Ports
• 4 registers - status, control, data-in, data-out
– Status - states whether the current command is
completed, byte is available, device has an error, etc
– Control - host determines to start a command or
change the mode of a device
– Data-in - host reads to get input
– Data-out - host writes to send output
• Size of registers - 1 to 4 bytes

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I/O devices can be interfaced to a computer
system I/O in 2 ways:

• Memory Mapped I/O

• I/O mapped I/O

Memory-Mapped I/O (1)
Memory Address Space

I/O Address Space

(a) Separate I/O and memory space

(b) Memory-mapped I/O
(c) Hybrid 12
 Memory Mapped I/O
• No need of special I/O instructions.
• Memory related instructions are used for I/O
related operations.
 I/O Mapped I/O

Memory Address
Space I/O address Space

Total Address Space

 I/O Mapped I/O
• If we want to reduce the memory address
space, we allot a different I/O address space,
apart from total memory space.

Memory related instructions do not work here

Processor use these mode only for I/O Read, I/O
Write.
Difference between Memory Mapped
I/O & I/O mapped I/O
Memory Mapped I/O
Memory & I/O share the entire address
range of processor
Processor provides more address lines
for accessing memory
More Decoding is required
Memory control signals used to control
Read & Write I/O operations
I/O Mapped I/O
Processor provides separate address
range for memory & I/O
Less address lines for accessing I/O
Less decoding is required
I/O control signals are used to control
Read & Write I/O operations
Programmed I/O
• I/O operation means
– A data transfer between an I/O device & memory
or
– Between I/O device & Processor.
• If any I/O operations are completely
controlled by processor, then the system is
said to be using “ Programmed I/O”
– Processor has to check I/O system periodically
until the operation completes  “POLLING”
– Microprocessor has to check if any device need
service.
 Programmed I/O
j
& Int A?

Service
& routine A
Address
Decoder
Int C?
j
& Service
routine C

Int Z?
j
Service
routine Z
Priority:
The Routines assigns priority to the different
I/O devices
Port A is always checked 1st.
Then Port B
Then Port C
Order may change by changing routine.
• When Programmed I/O techniques is used:
– Processor fetches I/O related instructions from
memory and Issues I/O commands to I/O system
to execute the instruction.
– Memory Mapped I/O & I/O mapped I/O
technique may apply.
– Processor has 2 separate instructions IN & OUT
for data transfer.
– When the I/O instruction is encountered by the
processor the I/O port is expected to be ready to
response.
Processor is usually programmed to test the I/O
device status before initiating a data transfer.