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Email: gcetstld@gmail.com
Linear seperability
networks
Prepared by : Prof. K S Rao 2
Reference Books:
Text Books:
Switching and Finite Automata Theory
second edition by Zvi Kohavi – Chapter 7
x2 w2 T y
wn
xn
Example: y = f (x1,x2,x3) = (1,2,3,6,7) = x1’x3 + x2
x1
-1
x2 2 1_ y
2
1
4 x3
Prepared by : Prof. K S Rao
Capabilities and Limitations of
Threshold Logic
Threshold gate: Comparing the conventional gates,
• More powerful than conventional gates because it can realize
a larger class of functions
• Any conventional gate can be realized with a threshold gate
• Thus, threshold gates are functionally complete
5
Prepared by : Prof. K S Rao
Capabilities and Limitations of
Threshold Logic
8
Prepared by : Prof. K S Rao
x
Elementary Properties
9
Prepared by : Prof. K S Rao
Important Conclusions
10
Prepared by : Prof. K S Rao
x
Important Property
Thus, f’ is realizable by V2
11
Prepared by : Prof. K S Rao
Synthesis of Threshold Networks
13
Prepared by : Prof. K S Rao
Geometric Representation
A single variable function can be represented by a Straight line.
A two variable function can be represented by a plane.
A three variable function can be represented by a cube.
A four variable function can be represented by a cube inside other cube.
The requirement in all the above representations is - any two side by side
vertices should differ by one bit change only.
If we mark the true vertices and the false vertices on the Geometric
representation, and if all true vertices can be separated from the false
vertices by a line on a plane or by a plane in a cube, then that function is
known as linearly separable and it can be implemented by a Threshold
function.
00 01 00 01 00 01
Not Linearly
OR Gate AND Gate XOR Gate .
Separable15
Linearly separable and implementable.
Three variable functions (a cube):
Four variable
function (a
cube in another
cube)
15
Prepared by : Prof. K S Rao
Geometric Representation
n-cube: contains 2n vertices, each of which represents an
assignment of values to n variables and thus corresponds to a
minterm
• a line is drawn between every pair of vertices which differ
in just one variable
• a plan is identified between four vertices which differ in
two variables.
Vertices for which the
function is 1 (0) called: true
(false) vertices
Example: Three-cube representation
If
forthis
f =cube
x’y’ +isxz
separatable by a hyper
plane, such that all the true vertices
fall one side of this cut plane and all
false vertices are on other side of this
cut plane, then that function is
16
realizable with Threshold gates. Prepared by : Prof. K S Rao
x
Partial Ordering
Partial-ordering relation between vertices of the n-cube:
(a1,a2, …,an) (b1,b2, …,bn)
if and only if for all i, ai bi
• Partially ordered set of vertices: a lattice
• (0,0, …,0): least vertex
• (1,1, …,1): greatest vertex
• Some pair of variables incomparable: e.g., (0,0, …,0,1) and (1,0, …,0,0)
17
Prepared by : Prof. K S Rao
Unate Function Theorem
Theorem 1: f(x1,x2, …,xn) is unate if and only if it is not a tautology and the above
partial ordering exists, such that for every pair of vertices, (a1,a2, …,an) and
(b1,b2, …,bn), if (a1,a2, …,an) is a true vertex and
(b1,b2, …,bn) (a1,a2, …,an), then (b1,b2, …,bn) is also a true vertex of f
Minimal true vertex: A true vertex Si is said to be minimal if no other true
vertex Sj < Si
18
Prepared by : Prof. K S Rao
Linear Separability
For an n-cube representation for threshold functions:
linear equation given by (w1x1 + w2x2 + … + wnxn = T)
corresponds to an (n - 1)-dimensional hyperplane that cuts through
the n-cube
• Since f = 0 when w1x1 + w2x2 + … + wnxn < T,
and f = 1 when w1x1 + w2x2 + … + wnxn > T
the hyperplane separates the true vertices from the false ones
Such a function is called a linearly separable function
• Thus, every threshold function is linearly separable, and vice
versa
19
Prepared by : Prof. K S Rao
Linear Separability
22
Prepared by : Prof. K S Rao
Identification Example
Procedure:
1. Start with a multi-output algebraically-factored switching
network G
2. Process each primary output of G
• If the node represents a binate function, split into
multiple nodes and process recursively
• If the node is unate and is also a threshold function,
save it in the threshold network and process its input
nodes recursively
• Else, split the unate node into two or more nodes
that are threshold functions
3. Terminate procedure when all the nodes in G are
25
mapped to threshold nodes Prepared by : Prof. K S Rao
Synthesis of Threshold Functions
1 W2 + W3 W3 + W4 5
2 W1 + W3 T W2 + W4 6
3 W1 + W4 W1 7
4 W1 + W2
All weights are +ve. Let W4 = 1,
1 & 5 W2 > W4
W2 = W3 = 2, W1 = 3
1 & 6 W3 > W4
T = Average of [Minimum value of left of the
2 & 5 W1 > W4
above 1, 2, 3 & 4 + Maximum value of the
2 & 6 W1 > W2 x1
right of 5, 6 & 7]. i.e.
2 & 7 W3 > 0 x2 g
T = [4 + 3]/2 = 7/2. 3
3 & 5 W1 > W3
2
3 & 6 W1 > W2 T=7/2
3 & 7 W4 > 0 2
4 & 7 W2 > 0 1
x3
x4
Prepared by : Prof. K S Rao
Synthesis of Threshold Functions
Threshold gate for
f function: x1
f = x1’x3’ + x2x3’ + x1’x4 + x1’x2
-2
1
x3
x4 f function
01 0 1 0 5 0 9
11
0 13
Maximum False vertices are
0 1 1 1 11
10
3 7 15
(0,0,1,1),(0,1,1,0) and (1,1,0,1)
0 2 0 6 1 14 1 10 Prepared by : Prof. K S Rao
Synthesis of Threshold Functions
Weights for gØ W3 + W4 5
1 W2 + W3 + W4 T W2 + W3 6
2 W1 + W3 W1 + W2 + W4 7
Let W2 = W4 = 1, W1 = 2, W3 = 3
T = Average of [Minimum value of left of
the above 1, & 2 + Maximum value of the
1 & 7 W3 > W1 right of 5, 6 & 7]. i.e.
1 & 6 W4 > 0 T = [5 + 4]/2 = 9/2. x
1 & 5 W2 > 0
x 1
2 & 5 W1 > W4 2 gØ
2 1
2 & 6 W3 > W2 T=9/2
2 & 7 W3 > W2+W4 3
x 1
Threshold gate for
gØ function: 3
x gØ function
gΦ = x1x3 + x2x3x4 4
Prepared by : Prof. K S Rao
Synthesis of Threshold Functions
x1
Threshold gate for
g function:
x2
g = x1’x3 + x2x3x4
-2
1
T=5/2
g
3
1
x3
x4 g function
X3x4
8 X3x4
0 4 1 12 0 0 0 4 0 12 0 8
00 5 9 00
1 13
01 01 0 1 0 5 1 13 0 9
1 11
11 3 7 15
11 0 3 0 7 1 15 1 11
10 2 6 1 14 1 10 10 0 2 0 6 1 14 0 10
x2 x2
-2 2
1 1
T=5/2 T=5/2 f function
3
1
3
-1
1
x3
x3
h function
x4 g function x4
1 1 1 1 1 1 1 1
1 1 1
Prepared by : Prof. K S Rao
Synthesis of Multi-level
Majority/Minority Networks
Realizable pattern: pattern of 1 cells realizable by a majority gate
• For three-input positive functions: 10 realizable patterns
• Removing the restriction that function be positive: 38 realizable
patterns
x1x2 x1x2 x1x2
x3 00 01 11 10 x3 00 01 11 10 x3 00 01 11 10
0 1 1 0 1 1 0
1 1 1 1 1 1 1 1 1 1 1
x1 = M(x1, 1, 0) = M(x1, 0, 1) x2 = M(1, x2, 0) = M(0, x2,1) x3 = M(1, 0, x3) = M(0, 1, x3)
0 1 1 0 1 1 1 0 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1
x1x2 x1x2
x3 00 01 11 10 x3 00 01 11 10
0 1 0
1 1 1 1 1
x1x2 x1x2
x3 00 01 11 10 x3 00 01 11 10
0 0 1
1 1 1 1 1 1 1 36
x2x3= M(0, x2, x3) Prepared by : Prof. K S Rao
x1x2 + x1x3 +x2x3 = M(x1, x2, x3)
Another Synthesis Example
Example: For f(x1,x2,x3,x4) = (3,5,7,10,12,14,15),
find a minimal
x1 x2
x3 x4
threshold-logic realization x1
x3
00 01 11 10 x4
00 1 x1
x2
x4
01 1 x2
x3 f
x4
11 1 1 1
x1
x2
x4
10 1 1
x1
x3
x4
(a) Map showing a minimal set of prime (b) AND-OR realization of f
implicants which cover f.
x1 x2
x3 x4 00 01 11 10
00 1 x1 x1
x2 x2
01 1 -1 2
1 g 1
1 1 1
2 32 2 f
1 2 1 2
11 1 1 1 x3 2 -1
x3
1 1 x4 x4
10
(d) A threshold-logic realization of f
x1
x2 x1 f1
x2 M x1 f1
x3
x3 x2 m
x1 x3
x2 x1 f2
x3 x2 M M f x1 f2
x1 x3 x2 m m f
f
x2 x3
x1 f3
x3 x2 x1
M f3
x1 x3 x2 m
x2 x3
x3
(b) (c)
(a)
38
Prepared by : Prof. K S Rao
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General Synthesis Procedure
Procedure:
1. Start with a multi-output algebraically-factored switching network G
2. Decompose G into a network in which nodes have at most three inputs
• If the node represents a majority function, move on to the next node
• If a common literal exists in all the product terms of the node
function, factor it out and perform AND/OR mapping on it
• If a common literal does not exist, check to see if the node can be
implemented with fewer than four AND/OR nodes
• Else, map the node onto at most four majority gates using a
Karnaugh-map based procedure
Example: Consider f = x1x2’+ x2’x3
• With AND/OR mapping, three majority gates are
needed:
– f1 = x1x2’, f2 = x2’x3, f = f1 + f2
• However, since literal x2’ can be factored out: f = f1x2’
where f1 = x1+x3
– This requires only two majority gates 39
Prepared by : Prof. K S Rao
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K-map based Procedure
1 1 1 1 1 1 1
n = x1x2 x3 + x1 x2x3 + x1 x2x3 + x1 x2x3 f1 = x1 x2+ x2x3 + x1x3= M(x1, x2, x3)
(a) (b) (c)
x1 f1
x2 M
Compute 0 x1x2 Step 2: find f2 Update 1 x3
x1x2 x1x2
00 01 11 10 x3 00 01 11 10 00 01 11 10 x1
x3 x3 f2
x2 M M f
0 0 0 1 0 1
x3
1 1 1 1 1 x1 f3
1 1
x2 M
f2 = x1x2+ x2 x3+ x1x3 = M(x1, x2, x3) x3
(d) (e) (f)
1 0 1 1