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 Multi-valued logic and standard IEEE 1164

• How many logic values for modeling?

• Two ('0' and '1') or more?
• If real circuits have to be described, some abstraction of the
• resistance (inversely-related to the strength) is required.
•  We introduce the distinction between:
• the logic level (as an abstraction of the voltage) and
• the strength (as an abstraction of the current drive capability) of
a signal.
• The two are encoded in logic values.

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 1 signal strength

• Logic values '0' and '1'.

• Both of the same strength.
• Encoding false and true, respectively.

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 2 signal strengths (1)
•Many subcircuits can Open-collector Tristate
effectively disconnect
themselves from the
rest of the circuit (they
provide „high
impedance“ values to
the rest of the circuit).
•Example: subcircuits
with open collector or
tri-state outputs.

 We introduce signal value 'Z', meaning „high impedance “

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 2 signal strengths (2)

•We introduce an operation #, which generates the effective

signal value whenever two signals are connected by a wire.
•#('0','Z')='0'; #('1','Z')='1'; '0' and '1' are „stronger“ than 'Z'

According to the partial order

in the diagram, # returns the
larger of the two arguments.
1 strength
In order to define #('0','1'), we
introduce 'X', denoting an
undefined signal level.
'X' has the same strength as '0'
and '1'.

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 Application example

input(s)

signal value on bus = #(value from left subcircuit, value from right subcircuit)
#('Z', value from right subcircuit)
value from right subcircuit
„as if left circuit were not there“.

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 3 signal strengths

•Current values insufficient

for describing real circuits:

Depletion transistor contributes a weak value to be

considered in the #-operation for signal A
 Introduction of 'H', denoting a weak signal of the same
level as '1'.
#('H', '0')='0'; #('H,'Z') = 'H'
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 3 signal strengths
•There may also be weak signals
of the same level as '0'
• Introduction of 'L', denoting a
weak signal of the same level as
'0': #('L', '0')='0'; #('L,'Z') =
'L';
• Introduction of 'W', denoting a
weak signal of the same level as
'X': #('L', 'H')='W'; #('L,'W') =
'W';
•# reflected by the partial order
shown.
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 4 signal strengths (1)

•Current values
insufficient for
describing pre-
charging:

Pre-charged '1'-levels weaker than any of the values

considered so far, except 'Z'.
 Introduction of 'h', denoting a very weak signal of the
same level as '1'.
#('h', '0')='0'; #('h','Z') = 'h'
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 4 signal strengths (2)
•There may also be weak signals
of the same level as '0'
• Introduction of 'l', denoting a
very weak signal of the same level
as '0': #('l', '0')='0'; #('l,'Z') =
'l';
• Introduction of 'w', denoting a
very weak signal of the same level
as 'W': #('l', 'h')='w'; #('h','w')
= 'w'; ...
•# reflected by the partial order
shown.
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 5 signal strengths

•Current values
insufficient for
describing strength
of supply voltage

Supply voltage stronger than any voltage considered so far.

 Introduction of 'F0' and 'F1', denoting a very strong signal
of the same level as '0 ' and '1'.
 Definition of 46-valued logic, also modeling uncertainty
(Coelho); initially popular, now hardly used.
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 IEEE 1164

• VHDL allows user-defined value sets.

•  Each model could use different value sets (unpractical)
•  Definition of standard value set according to standard IEEE
1164:
• {'0', '1', 'Z', 'X', 'H', 'L', 'W', 'U', '-'}
• First seven values as discussed previously.
• : Everything said about 7-valued logic applies.
• : Combination of pre-charging and depletion transistors
cannot be described in IEEE 1164.
• 'U': un-initialized signal; used by simulator to initialize all not
explicitly initialized signals.

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 Input don‘t care

•'-' denotes input don't care.

•Suppose: f ( a, b, c)  a b  bc. f undefined for a=b=c='0';
•Then, we could like specifying this in VHDL as
•f <= select a & b & c
• '1' when "10-" -- first term
• '1' when "-11" -- second term
• 'X' when "000"
•Simulator would check if a & b & c = "10-", i.e. if c='-'.
•Since c is never assigned a value of '-', this test would always fail.
Simulator does not know that '-' means either '1' or '0', since
it does not include any special handling for '-'.

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 Modeling logic gate values: std_ulogic

TYPE std_ulogic IS ( -- Unresolved LOGIC

‘Z’, -- High Impedance (Tri-State)
‘1’, -- Forcing 1
‘H’, -- Weak 1

‘X’, -- Forcing Unknown: i.e. combining 0 and 1

‘W’, -- Weak Unknown: i.e. combining H and L

Example:
‘L’, -- Weak 0
multiple drivers
‘0’, -- Forcing 0 0 1
1 X
‘U’, -- Un-initialized 1
‘-’, -- Don’t care 1 0
);
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 The rising transition signal

Vcc=5.5 25°C

1
> 3.85 Volts

H
Unknown
X W
2.20 Volt
L gap

< 1.65 Volts

0

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 Multiple output drivers: Resolution Function

U X 0 L Z W H 1 -
U U U U U U U U U U
X U X X X X X X X X
0 U X 0 0 0 0 0 X X
L U X that0
Suppose L L W W 1 X
Z U the first
X 0 gateLoutputsZ a1W H 1 X
the second gate outputs a 0
W U
then X 0 W W W W 1 X
H U the mult-driver
X 0 W output
H is XW H 1 X
X: forcing unknown value by
1 U X X
combining 1 1and 0 1together
1 1 1 X
- U X X X X X X X X
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 Multiple output drivers: Resolution Function

U X 0 L Z W H 1 -
U U U U U U U U U U
X X X X X X X X X
0 0 0 0 0 0 X X
L L L W W 1 X
Observe that 0
Z Z W H 1 X
pulls down all
W weak signals to 0 W W 1 X
H H 1 X
H <driving> L => W
1 1 X
- X
• Note the multi-driver resolution table is symmetricalPage 33
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 Resolution Function: std_logic buffer gate

1 1
H std_logic 1
W, Z X
L
std_ulogic 0
0 0

input: U 0 L W X Z H 1 -
output: U 0 0 X X X 1 1 X

0 or L becomes 0 H or 1 becomes 1

Transition zone becomes X

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 Resolving input: std_logic AND GATE

std_ulogic std_logic
W std_logic
X
std_ulogic X
1 1 std_logic

Process each input as an unresolved to resolved buffer.

Then process the gate as a standard logic gate { 0, X, 1, U }

For example, let’s transform z <= ‘W’ AND ‘1’;

z <= ‘W’ AND ‘1’; -- convert std_ulogic ‘W’ to std_logic ‘X’
z <= ‘X’ AND ‘1’; -- now compute the std_logic AND
z <= ‘X’;

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