CIRCUIT

CHARACTERIZATION OF
CMOS CIRCUITS

1
Course Emphasis
 For this course, we’ll emphasize on
Digital IC System
 Discussions will be both at transistor
level and gate/system level

2
Design Abstraction Levels
SYSTEM

MODULE
+

GATE

CIRCUIT

DEVICE
G
S D
n+ n+

3
 Fundamental Parameters
Parameters needed to be considered when
designing an integrated circuit:
 Functionality
 Reliability, Robustness static behavior
 Area
 Die size reflects the fabrication cost and speed.
 Performance
 Speed (delay)
 Power Consumption Dynamic response
 Energy

4
Overview: Chapter 1
 This chapter will introduce the concept of
noise margin and NM optimization techniques
 Power dissipation of CMOS circuits and
looking at power-speed trade-off and delay-
reduction techniques
 Case Study: looking at NM, delay, and power
dissipation in a CMOS inverter
 Scaling of CMOS circuits

5
1.1 NOISE MARGIN

NMH and NML

6
Noise in Digital Integrated Circuits
•A challenge in high-performance circuit design
VDD
v(t)
i(t)

(a) Inductive coupling (b) Capacitive coupling (c) Power and ground
noise

•Source for (a) and (b): e.g. 2 wires placed side by side
>> Dv or Di on one wire will influence signals on neighboring wire
•Capacitive coupling will cause feedback from output to input. BAD!!!
•For (c), will cause noise on power and ground rails
7
 Analog and Digital signals

"1"
V
OH
V(y)
Slope = -1
Digital: nominal
V
IH
V
OH “1” and “0” only.
Undefined Analog: all signal
Region levels
Slope = -1
V
IL VOL
"0"
V
OL V V V(x)
IL IH

• Steady-state signals are to avoid UNDEFINED REGION to

ensure proper circuit operation
• VIL and VIH are defined as the point on the VTC (Voltage
Transfer Characteristics) where dVout/dVin = -1
8
 Definition of Noise Margins
"1"
V
OH
NMH
V
Noise Margin High IH
Undefined
(size of legal “1”)
Region
Noise Margin Low
(size of legal “0”) NML V
IL
V
OL
"0"

Gate Output Gate Input

9
Def’n of NM… cont’d
 NM represent levels of noise that can be
sustained when gates are cascaded
 “0” and “1” intervals must be as large as
possible for a gate to be robust and
insensitive to noise disturbances
 Else, small perturbation at any node internal
or external to the circuit could change logic
level and cause device to give misleading
response
10
 Def’n of NM… cont’d
 To be robust and insensitive to noise
 VTC gain >> 1 in UNDEFINED REGION
 VTC gain < 1 in legal zones (“0” and “1”)
 NM property of a circuit could be
illustrated using CMOS regenerative
property (next slide)
 NMH (Noise Margin High) = VOH – VIH
 NML (Noise Margin Low) = VIL – VOL
 Logic Swing = VOH - VOL
11
 The Regenerative Property
Ensures a disturbed signal converges back to one of the
nominal voltage levels after passing through a number
of logical stages
...
v0 v1 v2 v3 v4 v5 v6

(a) A chain of inverters.

v1, v3, ... v1, v3, ...
v3 finv(v)
f(v)

v1 v1
finv(v) v3 f(v)

v2 v0 v0, v2, ... v0 v2 v0, v2, ...

(b) Regenerative gate (c) Non-regenerative gate
12
 Regenerative Property… cont’d
 Consider graph of a regenerative gate:
 v0 = initial input
 v3 = converged nominal voltage
 Consider graph of a non-regenerative gate:
 v0 = initial input
 v3 = output after two stages, still not able to converge
to one of nominal voltage levels, looping around.
Having difficulties converging!!!
 Regenerative Property prevent a design/signal
from going into undefined region due to noise
disturbances / interferences
13
Noise Margin
 Could be obtained from a circuit’s VTC
 Steps
 determine VOH, VOL, VIH, VIL by Mapping on
VTC
 Determine NMH and NML

14
 At a glance: VTC of an Ideal Gate
Vout

Ri = 

Ro = 0
g= 

Vin

 Characteristics:
 Infinite impedance in transition region
 VM in the middle of logic swing
 NMH = NML = ½ logic swing
 Input impedance = infinity
 Output impedance = 0
15
VTC of Real Gate (Inverter)
5.0

4.0 NML

3.0
Vout (V)

2.0
VM
NMH
1.0

0.0 1.0 2.0 3.0 4.0 5.0

Vin (V)

NOTE THE DIFFERENCE!!! WHY? DISCUSS…

16
1.2 DELAY

17
 Delay Definitions
Vin

50%

t
t t
pHL pLH
Vout
90%

50%

10% t
tf tr

Delay: time difference between 50% of signal in to 50% of

signal out. Divided into tpLH and tpHL
Rise time, tr: 10% to 90%
Fall time, tf: 90% to 10% 18
 e.g.Ring Oscillator
Take ring oscillator as an example.
•made up of an odd number of inverter stages (for static inverted
based oscillator) or even number of inv stages (for differential
based oscillator)
•Delay through the oscillator, T = 2 x tp x N. Why multiply by 2?

v0 v1 v2 v3 v4 v5

v0 v1 v5

T = 2  tp  N 19
1.3 Power Dissipation

20
Power Dissipation
 Affects
 Feasibility
 Cost
 Reliability.
 How?

21
Power Dissipation

22
Power Dissipation
 Peak power
 The value is used to determine e.g. power line
sizing
 Average power
 Used to determine cooling, battery requirements
 Power-Delay Product
 tp is determined by speed at which a given amount
of energy can be stored on gate capacitors
 PDP is normally a constant for a technology /
topology

23
CMOS Power Sources
 Power in CMOS
 Static
 e.g. leakage current, sub-threshold current
 Dynamic
 Charging of capacitors and temporary current
paths between supply rails when both PUN and
PDN are on simultaneously (creating a short
between supply rails)

24
1.4 Case Study:
CMOS INVERTER
NM, delay, power

25
CMOS Properties
 Full rail-to-rail swing -> high noise margin!
 Symmetrical VTC
 Propagation delay function of load capacitance and
resistance of transistors
 No static power dissipation
 Direct path current during switching
 Low output impedance
 Less sensitive to noise
 High input resistance
 Gate is virtually a perfect insulator. Draws no dc input
current

26
 The CMOS Inverter: A First Glance
VDD

Vin Vout

CL

Made up of a PMOS (PUN) and an NMOS (PDN). CL is the

lumped load capacitance (modeling wire and interconnect
capacitances)
27
Switch Model of CMOS Transistor
For digital applications, a CMOS transistor can be
modeled as a switch.
|V GS|

Ron

|VGS| > |VT|

|VGS| < |VT|

28
 CMOS Inverter: Steady State Response
Ideally, when input is HIGH, PMOS is off, NMOS is on, modeled as
a closed switch with an on-resistance (VOL = 0). When input is
LOW, PMOS is on and NMOS is off (VOH = VDD).
VDD VDD

Ron
VOH = VDD
Vout
Vout VOL= 0

Ron VM = f(Ronn,Ronp)

Vin = V DD Vin = 0
29
CMOS Inverter: Transient Response
VDD

tpHL = f(Ron.CL)
= 0.69 RonCL

Vout
Vout ln(0.5)
CL
1 VDD
Ron

0.5
0.36

Vin = V DD
t
RonCL

30
 CMOS Transient Response
 Delay = 0.69 RC, and in the case of an
inverter, R is the on-resistance, while C is the
load capacitance.
 This suggests that to reduce delay, we can reduce
R or C. Can we?
 Ron is inversely proportional to W/L. Increasing
W/L will reduce Ron but what about CL? What
would be the best approach, then?

31
Voltage Transfer
Characteristic

32
 CMOS Inverter Load Characteristics
In,p
V in = 0 Vin = 5

NMOS
PMOS

Vin = 4 Vin = 1 Vin = 4

Vin = 3 Vin = 2 Vin = 3 Vin = 2

Vin = 4 Vin = 2 Vin = 1

V in = 3
Vin = 5 Vin = 0

VTC can be determined using the graph above, or through mathematical

analysis. For this course, we’ll look at the mathematical approach – to be
discussed later. 33
 CMOS Inverter VTC
Vou t NMOS off
PMOS lin

5 NMOS sat
PMOS lin
4

NMOS sat
3

PMOS sat
2

NMOS lin
PMOS sat NMOS lin
1

PMOS off

1 2 3 4 5 Vin

CMOS inverter VTC. How to get the points? Check each of the
5 regions and verify the operating mode. 34
 Gate Switching Threshold – NM
performance
4.0

3.0
VM

2.0

1.00.1 0.3 1.0 3.2 10.0

kp/kn

• VM is a point on the VTC. For max NM performance, VM must be ½ Vswing.

We should make Kp = Kn to achieve this goal.
• Increasing PMOS or NMOS widths moves VM towards VDD or GND,
respectively.
• Size properly to maximize NM and obtain symmetrical characteristics. 35
MOS Transistor Small Signal Model
G D
+
vgs gmvgs ro
-

36
 Determining VIH, VIL, and VM
To get the overall VTC of a static CMOS, we need to determine
VOH, VOL, VIH, VIL and VM. For CMOS, VOH = VDD, VOL = VSS. Now,
determine the other 3 points. We know the fact that

This is the point where small signal gain g = -1. Consider:

(eqn 1)
37
 Determining VIH, VIL, and VM.. Cont’d
 Consider VIH
 for Vin=VIH, PMOS is in saturation, NMOS is in linear regions
(refer to p.35).
 This results in (based on table on p.37):
 gmn=knVout
 gmp=kp(VDD-VIH-|VTp|)
 ron=1/[kn(VIH-Vout-VTn)
 rop=
 Substitute the expressions above into (eqn 1). We’ll get:
k nVout  k p (VDD  VIH  | VTp |)
g  ( g mn  g mp )  (ron || rop )    1
k n (VIH  Vout  VTn ) (eqn 2)
 Vout 2  k p
k n (VIH  VTn )Vout   (VDD  VIH  | VTp |) 2 (eqn 3)
 2  2
38
Determining VIH, VIL, and VM.. Cont’d
 Solving Vout from (eqn 2) and substituting the result into (eqn 3)
results in a second-order equation with one root between 0 and
VDD.
 Now consider VIL. When Vin=VIL, NMOS will be in saturation
whereas PMOS will be in linear region. Therefore:

g mn  k n (VIL  VTn )
g mp  k p (VDD  Vout )
ron  
1
rop 
k p (Vout  VIL  | VTp |)
39
 Determining VIH, VIL, and VM.. Cont’d
Therefore:
k n (VIL  VTn )  k p (VDD  Vout )
g  ( g mn  g mp )  (ron || rop )  
k p (Vout  VIL  | VTp |)
 1 (eqn 4)
 (VDD  Vout ) 2  k n
k p (VDD  VIL  | VTp |)(VDD  Vout )   (VIL  VTn ) 2 (eqn 5)
 2  2

 Solving Vout from (eqn 4) and substituting the result into (eqn 5)
results in a second-order equation with one root between 0 and
VDD. This root is the VIL.

Eqn 5 is obtained by equating currents that flow through PMOS

and NMOS transistors

40
 Determining VIH, VIL, and VM.. Cont’d
VM (inverter threshold) is defined as the point where Vin=Vout. It
could be obtained graphically or through analysis.

When Vin = Vout, PMOS and NMOS are in saturation region. Therefore,
we can obtain VM by equating currents flowing through the
transistors (just like what we did to solve for VIH and VIL).
kn kp
(VM  VTn )   (VDD  VM  | VTp |) 2
2

2 2
this results in:
r (VDD  | VTp |)  VTn kp
VM  where r
1 r kn

41
VIH, VIL, VM
 From previous equation, we can
conclude that it is a good idea to make
PMOS kn’/kp’ times wider than NMOS in
order to maximize noise margins and
obtain symmetrical characteristics

42
Propagation Delay:
CMOS Inverter

43
CMOS Inverter: Transient Response
VDD

tpHL = f(Ron.CL)
= 0.69 RonCL

Vout
Vout ln(0.5)
CL
1 VDD
Ron

0.5
0.36

Vin = V DD
t
RonCL

44
CMOS Inverter Propagation Delay
VDD Also:

tpHL = CL Vswing/2
Iav

Vout CL
~
Iav CL kn VDD
Therefore, increase VDD to
reduce delay. If you increase
VDD, what about Power
Vin = V DD Dissipation??? 45
 Computing the Capacitances
VDD VDD

M2
Cdb2 Cg4 M4
Cgd12
Vin Vout Vout2

Cdb1 Cw Cg3
M1 M3
Interconnect

Fanout
Vin Vout
Simplified
Model CL

CL = total of wire cap, interconnect cap, and gate cap of next

stage. Remember from prev. discussion that we can increase W/L
to reduce resistance. Will this improve MOS gate capacitance? See
next slide…
46
Computing the Capacitances
Typical first order parasitic capacitance equations.
For rough analysis…

Recall: W/L , Ron , CL , Delay? Power?

47
 Impact of Rise Time on Delay
Other than CL, Ron, and VDD, it was found that rise
time also affects delay.
0.35

0.3
tpHL(nsec)

0.25

0.2

0.15
0 0.2 0.4 0.6 0.8 1
trise (nsec)

The equation was obtained from analytical studies, tpHL based on non-
zero tr. For best performance, make tr = tf (balanced) 48
Delay as a function of VDD
28

24

20
Normalized Delay

16

12

0
1.00 2.00 3.00 4.00 5.00
VDD (V)

VDD , Delay , Power

49
Where Does Power Go in CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors

• Short Circuit Currents

Short Circuit Path between Supply Rails during Switching

• Leakage
Leaking diodes and transistors
(sub-threshold current + drain leakage current + junction leakage
current -> caused by thermally generated carriers)

50
Dynamic Power Dissipation
Vdd

Vin Vout

CL

Energy/transition = CL * Vdd2

Power = Energy/transition * f = CL * Vdd2 * f

Need to reduce CL, Vdd, and f to reduce power.

Speed-Power trade-offs!
Want speed, gotta sacrifice power, can we have both?
51
1.5 Technology Scaling
and its Impact

52
 Technology Evolution

Channel length scaling down, notice the changes in VDD, VT, and
gate oxide.
53
Technology Scaling

Minimum Feature Size

54
 Technology Scaling

Number of components per chip

MOSFET is the fastest growing process. Gate length is shrinking

much faster than anticipated. Will there be a limit?
55
 Propagation Delay Scaling

Delay seems to be improving, i.e. with shrinking device size, we’ll get
faster circuits. 56
Technology Scaling Models
In general, there are 3 scaling models:
• Full Scaling (Constant Electrical Field)
ideal model — dimensions and voltage scale
together by the same factor S

• Fixed Voltage Scaling

most common model until recently —
only dimensions scale, voltages remain constant

• General Scaling
most realistic for todays situation —
voltages and dimensions scale with different factors
57
Technology Scaling
 Full scaling
 Purpose of full scaling is to keep electric field
pattern in scaled devices identical to that of the
original devices.
 However, not feasible. We could not have all the
parameters scale down by the same factor. Else,
what would happen to, say, supply voltage or
oxide thickness?

58
Scaling Relationships for Long Channel Devices

59
 Scaling of Short Channel Devices
Scaling model for short channel devices is different than that of
long channel devices.
For short channel devices, we need to consider other secondary
effects such as (i) mobility degradation, (ii) velocity saturation
(reduces voltage dependency of Iav from quadratic to linear), (iii)
series resistance, (iv) drain-induced barrier lowering

60