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• Therefore:
ECE-E434
Digital Electronics
Memory Circuits– Ch. 16
Sense Amplifier
1. Word line is activated; The desired cell is activated;
2. During the read operation the voltage of the lines changes by small value of DV;
3. fs is activated; Q6 and Q5 connect the sense amplifier (latch) to VDD and GND;
4. The positive feedback loop in the SA (latch) pushes the voltages of bit lines to the
desired value.
ECE-E434
Digital Electronics
Memory Circuits– Ch. 16
Transconductance of QN
Calculated at VDD/2
Transconductance of QN
Calculated at VDD/2
ECE-E434
Digital Electronics
Memory Circuits– Ch. 16
ECE-E434
Digital Electronics
Memory Circuits– Ch. 16
ECE-E434
Digital Electronics
Memory Circuits– Ch. 16
• The W operation delay is equal to the time required for regenerating signal to
propagate around the feedback loop. We calculated this for SRFF previously.
ECE-E434
Digital Electronics
Memory Circuits– Ch. 16
ECE-E434
Digital Electronics
Memory Circuits– Ch. 16
Dynamic RAM
• There may be leakage Cs loses its voltage.
• Note: Cells need to be refreshed every few milli-seconds.
ECE-E434
Digital Electronics
Memory Circuits– Ch. 16