03EC 7903 SEMINAR II

A 65-nm CMOS Constant Current Source With

Reduced PVT Variation

Presented by
Archana S
Roll No:02
S3 M-tech ,VLSI & ES
 INTRODUCTION

A new nanometer based low power constant current reference with

small Process-Voltage Temperature variations.
 PROBLEM FORMULATION

V th based current reference : process independent, has temperature

dependency

Current summing design: High Power consumption and cost

Current generation using constant overdrive voltage : Supply voltage

dependent.

As technology is scaled down to 100 nm performance degraded due to

the shot channel effects
65 nm CMOS CONSTANT CURRENT
REFERENCE

Pre -regulator

Process tolerant current and process tracking

voltage bias circuit

Temperature compensated VI converter

 The current generation - process tolerant temperature compensated
VI converter.

It establishes a constant Vtho reference compensation voltage in series

with another auxiliary compensation voltage

These combined temperature coefficients will match with the linear &
non linear Temperature coefficients of the series resistor in the VI
converter.

The outcome leads to a constant current reference with reduced PVT

variation
 ADVANTAGES

Low power

65 nm CMOS technology is used

Better sensitivity figure of merit

With the embedded pre regulator the current reference gives

good line sensitivity
 LIMITATION

It has relatively larger area and slightly higher supply voltage due to the
pre regulator stage,

this can be overcome by replacing, the pre regulator stage with a simple
equivalent circuit.
 SOFTWARE TOOL

Tanner/ Micro wind

Simulation: Monte Carlo simulation
 CONCLUSION

It offers better sensitivity figure of merit compared to other technologies.

 REFERENCE
1. A. Bendali and Y. Audet, A 1-V CMOS current reference with temperature
and process compensation, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54,
no. 7, pp. 14241429, Jul. 2007.

2. K. Ueno et al., A 46-ppm/C temperature and process compensated current

reference with on-chip threshold voltage monitoring circuit, in Proc. IEEE Asian
Solid-S tate Circuits Conf., Nov. 2008, pp. 161164.

3. K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, A 1-W 600-ppm/C current

reference circuit consisting of subthreshold CMOS circuits, IEEE Trans.
Circuits Syst. II Express Briefs, vol. 57, no. 9, pp. 681685, Sep. 2010.

4. H. Kayahan, O. Ceylan, M. Yazici, S. Zihir, and Y. Gurbuz, Wide range,

process and temperature compensated voltage controlled current source, IEEE
Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 5, pp. 13451353, May 2013.

5. C. Yoo and J. Park, CMOS current reference with supply and temperature
compensation, Electron. Lett., vol. 43, no. 25, pp. 14221424, Dec. 2007.
THANK YOU