16ECU19 - VLSI Design and VHDL

MAP Code: C ( Theory Concepts)

Google Code: vhi5lf
Unit I -Introduction and basic concept of
VHDL
Session I

M.Selvam.M.Sc.,D.IT.,M.Phil..,M.E.,NET.
Assistant Professor/Department of ECS

Selvam/SKASC/II BSc ECS/UNIT I/S1 8/28/2017 1

 OUTLINE

Introduction to VLSI and VHDL

What is VLSI ?
Role of HDL in VLSI
History of VHDL
Comparison of VHDL and Verilog
Capabilities of VHDL
Hardware abstraction

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 Introduction

What is VLSI ?

It is abbreviated as Very Large Scale

Integration .
A Technique to integrate the large Scale
Integration to most of components in a circuit
to single silicon chip.
This Concept increase the number of
Components on a chip with Speed and Power
optimization.

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 Types of Integration
SSI (Small Scale Integration)
MSI (Medium Scale Integration)
LSI (Large Scale Integration)
VLSI (Very Large Scale Integration)

4
HDL ? ??
 Role of HDL in VLSI

Over the Time Different methods of Digital Circuits Design have Come
into picture Like
I. Manual Paper and Pen Method
II. Computer Aided Design (CAD Tools ) Method

Manual Pen Paper method for Circuit design now obsolete because of
its incompetence to capture Complex designs.
CAD tools method lead the Automation of the design process. In digital
design and Automation process it had 2 phases.

Schematic Capture tools

Hardware Description Languages(HDL)

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 Schematic Capture tools for design automation were introduced in
1970.
The tools are like

Orcad
PSPICE
Espresso and may on.

These Tools were follows drag down approach wherein large,

Complex circuits designed by simple predefined components from the
list .

Those Circuits were verified via simulation process to verify their

functionality.

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 The next breakthrough in digital automation was HDL in 1980s

It allowed flexibility in the in the digital circuits to be designed at a

higher level of Functionality before getting converted in the form of
basic gates and flip flops.

It is also meant building of complex circuits from the basic components

HDL Process

System Simulation Synthesis

Design

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 Introduction to HDL s

The Hardware Description Language(HDL) is a language that is used for

the design of electronic circuits, describing its interface operation and
verification of its functionality.
It is a text base language to design a circuit. It is similar programming
languages but used to describe the Hardware.
It follows these features
It have the ability of describing Hardware structure of the circuit
to be designed .
It able to abstract the behavior of the circuit.

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 Evolution of HDLs

1977- ISP by Carnegie Mellon University First HDL

1977- KARL University of Kaiserslautern
ISP were used to simulate the description and not synthesis it.
KARL used the interactive floor planning and calculus features
1980- ABL ( ABLED VLSI graphic Editor ) by a Telecommunication Center
CSELT at Torino.
Later 80s Cadence introduced Verilog XL was introduced.
But many of the HDL was inadequate to describe the complex hardware
design. It requires an another language VHDL

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 HDL Examples
AHDL
Altera HDL

CDL: Computer Description Language

1965

ISPS: Instruction Set Processor Specification

AHPL: A Hardware Programming Language
Abel
Small designs such as state machines

DSD 2010 11
 WHAT IS VHDL ??....

Is it
VERY
HARD
DIFFICULT
LANGUAGE
??????.....
 Contd..
I think most of the students at the first instance feel like this

But , is it true ???

No !! Not at All
 VHDL is an acronym of

V : Very High Speed Integrated

Circuit
H : Hardware
D : Description
L : Language
 Contd
A Language developed to describe the complex
digital circuits.

It is a C like language that supports wide range of

description styles(Structural description, data flow
description, behavioral description and mixed
description)
FLASH BACK
 HISTORY OF VHDL

VHDL (VHSIC Hardware Description Language) is a hardware

description language used in electronic design automation to
describe digital and mixed-signal systems such as field-programmable
gate arrays and integrated circuits. VHDL can also be used as a general
purpose parallel programming language.

Very High Speed Integrated Circuit (VHSIC) Program

Launched in 1980
Aggressive effort to advance state of the art
Object was to achieve significant gains in VLSI technology
Need for common descriptive language

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 In July 1983, a team of Intermetrics, IBM and Texas Instruments were
awarded a contract to develop VHDL by DoD of U.S
In August 1985, the final version of the language under government
contract was released: VHDL Version 7.2
In December 1987, VHDL became IEEE Standard 1076-1987 and in 1988
an ANSI approved standard
In September 1993, VHDL was standardized to clarify and enhance the
language (IEEE Standard 1076-1993)

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 IEEE 1076.1 VHDL Analog and Mixed-Signal (VHDL-AMS)
IEEE 1076.1.1 VHDL-AMS Standard Packages (stdpkgs)
IEEE 1076.2 VHDL Math Package
IEEE 1076.3 VHDL Synthesis Package (vhdlsynth)
IEEE 1076.3 VHDL Synthesis Package - Floating Point (fphdl)
IEEE 1076.4 Timing (VHDL Initiative Towards ASIC Libraries: vital)
IEEE 1076.6 VHDL Synthesis Interoperability
IEEE 1164 VHDL Multivalue Logic (std_logic_1164) Packages

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 WHY USE VHDL ?

Allows for various design methodologies

Provides technology independence
Describes a wide variety of digital hardware
Eases communication through standard language
Allows for better design management
Provides a flexible design language

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 Hello World!
VHDL vs. Verilog
VHDL Verilog
------------------------------------------ //-----------------------------------------------------
-- Design Name : hello_world // This is my first Verilog Program
-----------------------------------------
// Design Name : hello_world
entity hello_world is // File Name : hello_world.v
end; // Function : This program will print 'hello
world
architecture hello_world of hello_world is // Coder : Deepak
begin //-----------------------------------------------------
stimulus : process
begin
assert false report "Hello World By module hello_world ;
Deepak initial begin
severity note; $display ("Hello World by Deepak");
wait;
end process stimulus; #10 $finish;
end hello_world; end
endmodule // End of Module hello_world

DSD Ref: www.asic-world.com 2013 21

 VHDL vs. Verilog
All abstraction levels All abstraction levels
Designed for Designed for hardware
documentation design
Ada based constructs C and Ada constructs
High level & system Gate & structural
descriptor descriptor
No PLI Very powerful PLI

DSD 2010 22
 VHDL vs. Verilog
Behavioral

Dataflow
VHDL
Verilog
Structural
& Gate

Switch

DSD 2010 23
 VHDL vs. Verilog
VHDL, More popular in Europe
Verilog, In USA, Japan

DSD 2010 24
 CAPABILITIES OF VHDL

The following are the major capabilities that the language provides along
with the features that differentiate it from other hardware description
languages.

as an exchange medium between chip vendors and CAD tool users.

as a communication medium between different CAD and CAE tools,
The language supports hierarchy.
The language supports flexible design methodologies: top-down, bottom-
up, or mixed.

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 The language is not technology-specific, but is capable of supporting
technology-specific features.
It supports both synchronous and asynchronous timing models.
Various digital modeling techniques such as finite-state machine
descriptions (FSM) , algorithmic descriptions, and Boolean equations can
be modeled using the language.
A common language can be used to describe library components from
different vendors.

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 The language is publicly available

It supports a wide range, of abstraction levels

The language has elements that make large scale design modeling
easier.

Test benches can be written using the same language to test other
VHDL models.

Allows Various delay models.

Generics and attributes are also useful in describing

parameterized designs.

The capability of defining new data types .

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 HARDWARE ABSTRACTION

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 VHDL is used to describe a model for a digital hardware device.

This model specifies the external view of the device and one or more
internal views.

The internal view of the device specifies the functionality or structure,

while the external view specifies the interface of the device through which
it communicates with the other models in its environment.

The main abstraction of VHDL is the design entity, which identifies and
represents a single part of a design, executes a specific function, and has
well-defined inputs and outputs.
That is, an entity represents a black box; one or more input and output
lines enter and leave the black box, and a delay is identified with each
line.
A VHDL model consists of at least one design entity.

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 The entity is thus a hardware abstraction of the actual hardware
device. Each entity is described using one model that contains one
external view and one or more internal views

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There are two main elements that describe an entity:
1. entity declaration
2. architecture body.
The entity declaration contains the interface of the model to the environment,
attribute descriptions, specifications and further descriptions (i.e., assertions)
common to all architectures.
An architecture represents one possible implementation of the model.
Different implementations can result from different design variants or from
different levels of abstraction in the design process. Several architectures can
be associated with the same entity declaration

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 Popular Levels of
Abstraction
Behavioral

Data flow

problem
Structural

Switch

DSD 2010 33
 Popular Levels of
Abstraction (contd)
Behavioral

Data flow

problem
Structural

Switch

DSD 2010 34
 Popular Levels of
Abstraction (contd)
Behavioral

Data flow

problem
Structural

Switch

DSD 2010 35
 Popular Levels of
Abstraction (contd)
Behavioral

Data flow

problem
Structural

Switch

DSD 2010 36
Selvam/SKASC/II BSc ECS/UNIT I/S1 8/28/2017 37
 SUMMERY
VLSI ?
Types of Integration
HDL ?
CAD?
Role of HDL in VLSI
What is VHDL?
Genesis of VHDL
Capabilities
Hardware abstraction

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 MCQ

1. In____, VHDL was proposed as an IEEE standard.

a) 1985 b) 1980 c) 1986 d) 1987

2.All designs are expressed in terms of ____.

a) Entity b) Architecture c) key d)Generics

3.The primary design units are ____

a) Entity b) Architecture c) both a and b d)Generics

4.CAD stands for

a) Colour and Design b) Computer and design
c) Computer aided Design d) Compute and Design

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 5. Architecture body describes the ______ view of a Circuit under
design.
a) external b) internal c) classic d) black box

6. VHDL is ________ language.

a) event driven b) Structured c) Simulation d) Functional
7. HDL Stands for ________________.
a) Hardware description language
b) HART design Loop
c) Hardware design language
d) Hardware design loop
8. VHDL 7.2 was introduced in the year of _______.
a)1985 b) 1980 c) 1986 d) 1987

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 9.ASIC stands for ___________________.
a) Application Specific Integrated Circuit
b) Automotive Specific integrated circuit
c) Artistic Specific integrated circuit
d) both a and b

10. Which is the first HDL language?

a) ISP b) ABEL c) VHDL d) Verilog

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