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Figure 10-4 The output of a BPSK modulator circuit for a 1010101 input.
Figure 10-6 A BPSK receiver using coherent carrier recovery and a mixer circuit.
Figure 10-7 The QPSK phase constellation: (a) vector representation; (b) the data points.
Figure 10-7 (continued) The QPSK phase constellation: (a) vector representation; (b) the data points.
Figure 10-11 The QPSK constellation with noise at the receiver. The decision boundaries are shown by the different
shaded areas.
Figure 10-18 An implementation of a 7-bit PN sequence generator using Electronics Workbench TM Multisim.
Figure 10-19 The serial data output stream for the 7-bit PN sequence generator.
Figure 10-20 The PN sequence generator circuit structure for the connections listed in Table 10-2. The circuit shown is
connected with five shift registers (n = 5) and a maximal length of 31.
Figure 10-25 The waveforms for the BPSK output and the PN code.
Figure 10-26 The DSSS output signal generated by mixing the BPSK output and the PN code.
Figure 10-27 The DSSS signal input to the receiver and the recovered BPSK data.
Figure 10-29 The time domain waveforms for the BPSK and PN code outputs using the proper chip modulation rate
relationship.
Figure 10-32 Example of the OFDM transmission of the ASCII characters B, U, and Y.
Transmisor OFDM
Receptor OFDM
Figure 10-33 The RF spectrum for a hybrid (analog and digital) AM transmission.
Figure 10-34 The RF spectrum for a hybrid (analog and digital) FM transmission.
Figure 10-43 The phase relationship for the input and output of an inverting amplifier.
Figure 10-44 The oscilloscope view of the BPSK signal and the recovered data.