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INVERTER
i/p = 0 pMOS alone is ON
o/p driven by VDD i.e. O/p = 1
i/p = 1 nMOS alone is ON
o/p gets discharged i.e. o/p = 0
TRANSMISSION GATE
nMOS and pMOS connected in parallel.
Inputs to both MOSFETs are
complementary.
Bidirectional can carry current in either
directions.
Figure: 1
Working of D flip-flop...
Working of D flip-flop(contd.)
LHS latching circuit is enabled. It latches 1 which results in Q=0 (which is what it should be for
D = 0). It is to be noted that o/p arrives at positive edge of CLK. Hence its a positive edge
triggered flip flop.
Working of D flip-flop(contd.)
When CLK goes LOW, RHS latching circuit is enabled and there is no change in o/p
Any change in i/p is reflected at node Z which is reflected at the o/p at next positive edge of
CLK.
In summary, if D changes then the change would reflect at node Z when CLK is LOW and
would appear at the o/p when CLK goes HIGH.
TTX = TInitial
Negative Hold Time
METASTABILITY
How to determine whether the signal is
logic HIGH or logic LOW?
Voltage range and Threshold
The voltage levels falling between 0V to
Vol is taken to be logic LOW & the
TTL Voltage Levels
voltages lying between Voh to 5V is
taken to be logic HIGH. Any node
having voltage levels between Voh and
Vol is said to be in No Man's Land (in
other words Metastable).
CAUSE:
setup or hold violations for which the afected nodes doesn't get enough
time to settle to a stable voltage level.
CONSEQUENCES:
In flip flops, this leads to increase in C2Q delay and eventually leading to
capture of wrong data.
Figure Missing!!!
So, basically the reset logic is built upon the following basic Df/f
structure:
In addition to reset, preset can also be integrated into the D f/f. Lets
take a look!!!
Consider the case where the clock to flop B is inverted (or that the flop
is negative edge trigerred). In this particular case, the relevant edges
for setup/hold are as shown in the figure below.
In this scenario, the setup margin considering all the other parameters to
be the same is
Data Required time = (half_clock_period + clock insertion delay + Ck>Q delay of flop A - Setup time required for flop B) = 4 + 2 + 0.25 -0.1 =
6.15 ns
Since the Data Arrival time remains the same, i.e.
Data Arrival time = (Clock Insertion Delay + CK->Q Delay of the launch
flop + Combinational logic Delay) = 2 + 0.1 + 5 = 7.1 ns. there is a setup
violation of
Setup violation = 6.15 ns - 7.10 ns = -1.05 ns
There is no hold violation since the data arrival time remains the time but
the data expected time is any time after (Clock skew + Hold time
requirement of flop B)
Data expected time = 0.25 + 0.1 = 0.35 ns
Hold Margin = 7.10 - 0.35 = 6.75 ns