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# Latches

& Flip
Flops
A Presentation on the
combinational logic
circuits known as
latches and flip flops in
digital circuit design

which is constructed by the pair of. . coupled of NOR gate.Flip flop Flip flop • Logic circuits are classified into two groups i. Basic building block of combinational circuit is logic gates. Combinational circuit ii. •. counters and memory devices •. Flip flop has better and greater usage in shift register. It has two input and two output labeled as Q and Q’ •... serve as temporary buffer memory. neither crossed. It is a digital storage device. Normal and complement •. neither. while indeed the basic building block of Sequential circuit is flip flops •. Flip flop is a storage device which store one bit data •. Sequential circuit •. Latch: it is also building block of sequentional circuit.

It has two input S and R and two output Q and Q’. Clocked S-R flip flop ii. J-K flip flop . there are two NAND gates. if Q=1 then Q’=0. In flip flop output are always opposite. . D flip flop iii.S-R flip flop: . .In wiring diagram of R-S flip flop.Types of flip flop • There are three types of flip flop i.

Truth table of R-S flip flop Mode of operation S R Q Q’ Effect of output Prohibited 0 0 1 1 Prohibited do not use Set 0 1 1 0 For setting Q to 1 Reset 1 0 0 1 For setting Q to 0 Hold 1 1 Q Q’ Depend on privious state .

. D flip flop: • D stands for delay. • Output are labeled as Q & Q’. • It has only one data input D and a clock signal (CLK). • D flip flop may be formed as clocked signal R-S flip flop by adding an inverter. • Notice that output Q follows input D after one clock puls (see Qn+1 column).

• The JK is in R-S flip flop with feedback from Q & Q’. • Toggle means the output will change to the opposite state (0 to 1 or 1 to 0) after every clock transition. • J & K does not mean any special but J is equivalent to set and K is equivalent to reset. . • R=S=1 state has been replaced with a toggle state. J-K flip flop • J-K flip flop act as R-S flip flop except that it does not have a invalid state.

Difference between flip flop and latch • Flip flop and latch are two basic building blocks of sequentional circuit but there is suitable difference between the two is. . • Where as latch is a device which continuously checks all its inputs and correspondingly changes its output. independent of time determined by clocking signal. • A flip flop continuously checks its inputs and corresponding changes its output only at times determined by clocking the signal.

•A unique signal called “enable” is provided with latch. •Flip flop are edge trigger. . while latches are level trigger. •No change in output take place when the enable signal is inactive. •The output changes only when enable signal is active.

Level trigger (High or low) 2.Edge trigger (+ve or –ve going transition) . Setting the enable high allows the latch to be set or reset. the trigger is enable line. • In gated latches.Triggeringand and Triggering clocking clocking • A trigger is a control signal used to initiate an action. o There are two forms of trigger: 1.

calculator • They are a group of flip flop connected in chain so that output from one flip flop becomes the input of next flip flop.e. The word shift means the device which shift data right or left.Shift Register • Shift registers are type of sequentional logic circuits mainly for storage of digital data. . i. • Most of the register posses no characteristics internal sequence of states. • All the flip flop are driven by common clock and all are set or reset simultaneously.

Serial out (SISO) 2) Serial in. 1) Serial in. Parallel out (PIPO) 0 1 1 Serial out 0 Serial in 1 0 1 1 Parallel out 0 Parallel in1 0 1 1 Parallel in1 0 1 1 Parallel out 0 Serial in 1 0 Serial out .• There are four types of shift registers. Parallel out (SIPO) 3) Parallel in. Serial out (PISO) 4) Parallel in.

Pulse the CLK input once the output now will be 1000. while they are await a clock pulse.Serial load shift register • The serial load shift register is constructed from four D flip flop. D. C. • In table first clear (CLR input to 0) all output A. again pulse clocking 1100. It is called four bit shift register because it has four place to store data A. D to 00000. . B. C. B. • This output 00000 remains same.

Truth table Line no: Clear Data Clock pulse FF A FF B FF C FF D 1 0 0 0 0 0 0 0 2 1 1 0 0 0 0 0 3 1 1 1 1 0 0 0 4 1 1 2 1 0 0 0 5 1 1 3 1 1 1 0 6 1 0 4 0 1 1 1 7 1 0 5 0 0 1 1 8 1 0 6 0 0 0 1 9 1 0 7 0 0 0 0 10 1 0 8 0 0 0 0 11 1 1 9 1 0 0 0 12 1 0 10 0 1 0 0 13 1 0 11 0 0 1 0 14 1 0 12 0 0 0 1 15 1 0 13 0 0 0 0 .

. C. B. This is just like rectangular feature. D. • It permits only one bit of information at a time • And it losses all its data out the right side when it shift right. these inputs are data inputs A. • But in parallel load shift register given in figure it permits 4 bit at once. that would put output data back into so that is not lost. we studied last has two disadvantages.Parallel load shift register • The serial load shift register.

Truth table Lin Clea Dat e r a no A : Dat aB Data C Dat aD Clock pulse FF A FF B FF C FF D 1 1 1 1 1 1 0 1 1 1 0 2 0 1 1 1 1 0 0 0 0 0 3 1 1 0 1 1 0 0 1 0 0 4 1 1 1 1 1 1 0 0 1 0 5 1 1 1 1 1 2 0 0 0 1 6 1 1 1 1 1 3 1 0 0 0 7 1 1 1 1 1 4 0 1 0 0 8 1 1 1 1 1 5 0 0 1 0 9 0 1 1 1 1 0 0 0 0 10 1 1 0 0 1 0 1 1 0 11 1 1 1 1 1 6 0 0 1 1 12 1 1 1 1 1 7 1 0 0 1 13 1 1 1 1 1 8 1 1 0 0 .

To produce time delay. To simplify combinational logic iii. ii. •. This is bi directional shift register which allow shifting to both direction LR or RL. •. . Shift register have both parallel and serial input and outputs. To convert the serial data to parallel data.Application of shift register • There are so many applications of shift registers i.