Sequential Logic

[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]

Project Presentations
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Sequential Logic
Inputs

Outputs
COMBINATIONAL
LOGIC

Current State
Registers
Q

D
CLK

2 storage mechanisms
positive feedback
charge-based

Next state

V i2 5 V o1

V i2 5 V o1

Meta-Stability

B
V i1 5 V o2

B
V i1 5 V o2

Gain should be larger than 1 in the transition reg

Mux-Based Latches
Negative latch
Positive latch
(transparent when CLK=(transparent
0)
when CLK=

1
D

0
CLK

Q Clk Q Clk In

1
CLK

Q Clk Q Clk In

Mux-Based Latch

CLK

QM

CLK

QM

CLK

CLK

NMOS only

Non-overlapping clocks

Mux-Based Latch
CLK

Q
CLK
D

CLK

Writing into a Static Latch

Use the clock as a decoupling signal,
that distinguishes between the transparent and opaque states
CLK

CLK
Q
CLK

D
CLK

CLK

Converting into a MUX

Forcing the state

(can implement as NMOS-only)

Reduced Clock Load

Master-Slave Register
CLK
D

T1
CLK

CLK
I1
I2

T2
CLK

I3
I4

Avoid Clock Overlap

X

CLK

CLK
Q

A
B

CLK

CLK
(a) Schematic diagram

CLK

CLK
(b) Overlapping clock pairs

Storage Mechanisms

Dynamic (charge-based)

Static

CLK
CLK

Q
CLK
D

CLK

Very fast
CLK

Was popular, now too risky

Making a Dynamic Latch

Pseudo-Static
CLK

CLK

Weak inverter

SR-Flip Flop

0
1
0
1

0
0
1
1

Q
1
0
0

Q
0
1
0

1
0
1
0

1
1
0
0

Q
1
0
1

Q
0
1
1

Forbidden State

Forbidden State

Cross-Coupled NOR
Added clock

Cross-coupled NORs
S

VDD

M2

M4
Q

Q
R

Transistors M5-M8 are

CLK

M6

M5

M1

wider to switch the state

This is not used in datapaths any more,
but is a basic building memory cell

M3

M8

CLK

M7

Sizing Issues
2.0

3
Q

S
W = 0.5 m

W = 0.6 m
W = 0.7 m

Volts

Q (Volts)

1.5
1.0

W = 0.8 m

0.5

W = 0.9 m
0.0
2.0

2.5

3.0
W/L 5 and 6

3.5

4.0

(a)

Output voltage dependence

on transistor width

W= 1 m
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
time (ns)
(b)

Transient response
For various W/L 5 and 6

Naming Conventions
In our text:
a latch is level sensitive
a register is edge-triggered

There are many different naming conventions

For instance, many books call edge-triggered elements flipflops
This leads to confusion however

Latch versus Register

Latch
stores data when
clock is low

Register
stores data when
clock rises

D Q

D Q

Clk

Clk

Clk

Clk

Falls with data

Falls with clock

Latch-Based Design
N latch is transparent
when = 0

P latch is transparent
when = 1

N
Latch

Logic

Logic

P
Latch

Master-Slave
(Edge-Triggered) Register
Slave
Master
0
1
D

QM

D
QM
Q

CLK
CLK

Two opposite latches trigger on edge

Also called master-slave latch pair

Master-Slave Register
Multiplexer-based latch pair

I2

CLK

T2

I3

I5

T4

I4

T3

QM
I1

T1

I6

Timing Definitions

Set-up and hold times are needed to produce a stable outp

CLK
t
tsu
D

thold

DATA
STABLE
tc 2

Register

Q
CLK

DATA
STABLE

Propagation delay time affects the clock period

Characterizing Timing
tD 2
D

Clk
tC 2

Clk

Register

tC 2

Latch

Maximum Clock Frequency

FFs

LOGIC
tp,comb

tclk-Q + tp,comb + tsetup =

T

Minimum clock period

decides - the maximum
operating frequency of
a sequential circuit
Also:
tcdreg + tcdlogic > thold
tcd: contamination
delay = minimum
delay

Clk-Q Delay
2.5
CLK

Volts

D Q
1.5

0.5

2 0.5
0

tc 2

tc 2

q(lh)

0.5

1
1.5
time, nsec

Clk

q(hl)

2.5

Timing of Master-Slave
Register
In the multiplexer-based latch pair
assume that propagation delays of
inverters and transmission gates
D
are tpd_inv and tpd_tx

I2

I1

T2

T1

I3

QM

I5

T4

I4

T3

CLK

The setup time states how long before the rising edge of CLK data
D must
be stable. D has to propagate through I1, T1, I3, and I4 before the
rising edge of CLK, so tsetup=3 tpd_inv+tpd_tx
The propagation delay is the time to propagate signal from QM to
Q. Since
the output I4 is valid before the rising edge of the clock, so tcq=tpd_tx+tpd_inv
The hold time (time for the input to be stable after rising edge of
the clock)

I6

Setup Time
3.0

3.0
Q

2.5

QM
D

2.0
Volts

Volts

2.0
1.5

2.5

CLK

1.0
I 2 2 T2

0.5

CLK

1.0

QM

0.5

0.0
2 0.5
0

1.5

I 2 2 T2

0.0
0.2

0.4
0.6
time (nsec)

0.8

(a) Tsetup5 0.21 nsec

2 0.5
0

0.2

0.4
0.6
time (nsec)

0.8

(b) Tsetup5 0.20 nsec

Output failure

More Precise Setup Time

Clk
t
D
t
Q
t

1.05tC 2

tC 2

Setup and hold times

defined when delay
increases by 5%

delay
tSu

tD 2
tH

Setup/Hold Time Illustrations

Circuit before clock arrival (Setup-1
CN
case)
TG1

Inv2

SM

D1

QM

Clk-Q Delay

Inv1

CP
TClk-Q
TSetup-1

Data

Time

Clock

TSetup-1
t=0

Time

Setup/Hold Time Illustrations

Circuit before clock arrival (Setup-1
CN
case)
TG1

Inv2

SM

D1

QM

Clk-Q Delay

Inv1

CP
TClk-Q
TSetup-1

Data

Time

Clock

TSetup-1
t=0

Time

Setup/Hold Time Illustrations

Circuit before clock arrival (Setup-1
CN
case)
TG1

Inv2

SM

D1

QM

Clk-Q Delay

Inv1

CP

TClk-Q

TSetup-1

Data

Clock

TSetup-1
t=0

Time

Time

Setup/Hold Time Illustrations

Circuit before clock arrival (Setup-1
CN
case)
TG1

Inv2

SM

D1

Clk-Q Delay

QM

Inv1
TClk-Q

CP

TSetup-1

Data

Clock
TSetup-1
t=0

Time

Time

Setup/Hold Time Illustrations

Circuit before clock arrival (Setup-1
CN
case)
TG1

Inv2

SM

D1

Clk-Q Delay
TClk-Q

QM

Inv1

CP

TSetup-1

Data

Clock
TSetup-1
t=0

Time

Time

Setup/Hold Time Illustrations

Hold-1 case
CN
TG1
SM

D1

Inv2

Clk-Q Delay

QM

Inv1

CP

0
TClk-Q
THold-1

Clock

Data
THold-1
t=0

Time

Time

Setup/Hold Time Illustrations

Hold-1 case
CN
TG1
SM

D1

Inv2

Clk-Q Delay

QM

Inv1

CP

0
TClk-Q
THold-1

Clock

Data
THold-1
t=0

Time

Time

Setup/Hold Time Illustrations

Hold-1 case
CN
TG1
SM

D1

Inv2

Clk-Q Delay

QM

Inv1

CP

TClk-Q

THold-1

Clock

Data
THold-1
t=0

Time

Time

Setup/Hold Time Illustrations

Hold-1 case
CN

TG1
SM

D1

D
Inv1

Inv2

Clk-Q Delay

QM

TClk-Q

CP

THold-1

Clock

Data
THold-1
t=0

Time

Time

Setup/Hold Time Illustrations

Hold-1 case
CN
TG1
SM

D1

Inv2

Clk-Q Delay

QM

TClk-Q

Inv1

CP

THold-1

Clock

Data

THold-1
t=0

Time

Time

Other Latches/Registers: C2MOS

CLK

VDD

VDD

M2

M6

M4

D
CLK

M3
M1

CLK
X

M8
Q

CL1

CLK

M7

CL2

M5

Master Stage

Keepers can be added to make circuit pseudo-static

Insensitive to Clock-Overlap

VDD

VDD

VDD

VDD

M2

M6

M2

M6

M4

0
X

M8
Q

1 and M
1 time
CLK
C L3K 1 at the same
M1

M5

M1

(a) (0-0) overlap

CLK and C L K 0 at the same time

CLK

VDD

VDD

M2

M6

M4

CLK

M8

CLK

M7

D
CLK

M3
M1

Master Stage

CL1

M5

(b) (1-1) overlap

Q
CL2

Q
M7
M5

Other Latches/Registers: TSPC

VDD

VDD

VDD

VDD

Out
In

CLK

CLK

Positive latch
(transparent when CLK= 1)

In

CLK

CLK

Negative latch
(transparent when CLK= 0)

Only single phase clocks are used. When is high the latch is in th
evaluate mode. When is low the latch is in hold-mode.

Including Logic in TSPC

VDD

VDD

VDD
In1

PUN

VDD
In2

Q
In

CLK

CLK

PDN

Example: logic inside the latch

Q
CLK

CLK

In1

AND latch

TSPC Register
VDD
M3

CLK

VDD

VDD

M6

M9
Y

CLK

M2

M1

CLK

M5

M4

Q
Q

CLK

M8

M7

Master-Slave Flip-flops
VDD

VDD

(a) Positive edge-triggered D flip-flop

VDD

VD D

VDD

VDD

VDD

VDD

VDD
D

(c) Positive edge-triggered D flip-flop

using split-output latches

(b) Negative edge-triggered D flip-flop

Pulse-Triggered Latches
An Alternative Approach

Ways to design an edge-triggered sequential ce

Master-Slave
Latches
Data

Pulse-Triggered
Latch

L1

L2

D Q

D Q

Clk

Clk

Data
Clk

L
D Q
Clk

Clk

Need to generate the glitch pulse

Pulsed Latches
VDD

VDD

M3

M6

CLK

VDD

Q
D

CLKG

M2

CLKG

M1

(a) register

M5

M4

MP

MN

(b) glitch generation

CLKG

Pulsed Latches
Hybrid Latch Flip-flop (HLFF), AMD K-6 and K-7 :
CLK

P1

P3

M6

M3
D

M2
M1

P2

M5
M4

Hybrid Latch-FF Timing

3.0
2.5

Volts

2.0

Data not properly

captured due to
insufficient hold
time

1.5
1.0
0.5

CLK

CLKD

0.0
20.5
0.0

0.2

0.4
0.6
time (ns)

0.8

1.0

CLK

Reference

CLK

CLK

log

REG

REG
CLK

REG

CLK

Out

REG

log

REG

REG

CLK

REG

REG

Pipelining

CLK

CLK

Pipelined

Out

Latch-Based Pipeline
CLK

CLK

In

CLK

F
C1

C2

CLK
CLK

Compute F

Out

compute G

C3

Non-Bistable Sequential Circuits

Schmitt Trigger
In

Out

V OH

Vou t

VTC with hysteresis

V OL

Restores signal slopes

VM

VM+

Vi n

Noise Suppression using Schmitt

Trigger
Vin

Vout

VM

VM
t0

t 0 + tp

CMOS Schmitt Trigger

VDD

M2
Vin

M4
Vout

M1

M3

These transistors resist

the change in the X signa
Move switching threshold
of the first inverter

CMOS Schmitt Trigger

Increasing kn/kp ratio decreases the logical switching thre

If Vin=0 the Vout (connected to M4) is also zero

So effectively the input is connected to M2 and M4 in para
This increases kp and the switching threshold
V

If Vin=0 the situation is

reversed and kn increases
reducing the switching
threshold

M
V

D D

in

ou t

Schmitt Trigger Simulated VTC

2.5

2.5

2.0

2.0

Vout(V)

Vout(V)

VM1

1.5
1.0

1.5
1.0

VM2

0.5
0.0
0.0

k=1
k=2

0.5

0.5

1.0
1.5
Vin (V)

2.0

2.5

Voltage-transfer characteristics with hysteresis.

k=3
k=4

0.0
0.0

0.5

1.0
1.5
Vin (V)

2.0

2.5

The effect of varying the ratio of the

PMOS device M4. The width is k* 0.5m m.

CMOS Schmitt Trigger (2)

With input low and output high
X is charged to VDD Vth
M2 is cutoff until the input is
larger than VX +Vth
With output being pulled down
M5 is cut off and the output
transition is very rapid
This delays transition from high
to low values on the output.
Symmetrical analysis can be
performed for low to high output
transition

VDD
M4
M6
M3
In

Out
M2
X
M1

M5

VDD

Multivibrator Circuits
R
S
Bistable Multivibrator
flip-flop, Schmitt Trigger

T
Monostable Multivibrator
one-shot

Astable Multivibrator
oscillator

Transition-Triggered Monostable

In

DELAY
td

Out
td

Monostable Trigger (RC-based)

VDD
R

In

Out
(a) Trigger circuit.

RC delay regulates the

width of the generated
pulse

In

VM

Out

(b) Waveforms.

t
t1

t2

Astable Multivibrators
(Oscillators)
0

N-1

Ring Oscillator
V1

V (Volt)

5.0

V3

V5

3.0

1.0

-1.0

t (nsec)

simulated response of 5-stage oscillator

Relaxation Oscillator
Out1
I2

I1

Out2

C
Int

T = 2 (log3) RC

Voltage Controller Oscillator

(VCO)
VDD

VDD

M6

M4

Schmitt Trigger
restores signal slopes

M2

In
M1

Iref
Vcontr

M3

M5

tpH L (nsec)

Current starved inverter

Current Iref is a quadratic function

of Vcontr

6
4

This effects the delay time

0.0
0.5

Iref

1.5

Vcontr (V)

2.5

propagation delay as a function

of control voltage

Differential Delay Element and

VCO
in2

V o2

V o1

v1

in1

v2

v3

v4

two stage VCO

V ctrl

delay cell

3.0
2.5

V1 V2 V 3 V4

2.0
1.5
1.0
0.5
0.0
2 0.5
0.5

1.5

2.5
time (ns)

3.5

simulated waveforms of 2-stage VCO

JK- Flip Flop

(a)

S R

Q Q

1 1
0 1

Q Q
1 0

1 0
0 0

0 1
1 1

Jn

Kn

Qn+1

0
0
1
1

0
1
0
1

Qn
0
1
Qn
(c)

Q
(b)

For clock=0
S=R=1 and FF
maintains its
previous state

When J=K=1
then S=Q
and FF toggle

Problem if JK flip-flop in a toggle state (J=K=1) can flip a

For instance when Q=1, and J=K=1, then only R goes low
and Q changes to 0. If the clock is still high, the feedback
disables K and enables J and FF changes its output again

Other Flip-Flops
T

Toggle Flip-Flop

Delay Flip-Flop

(D-latch)

Race Problem
tloop
t

Signal can race around during = 1

Master-Slave Flip-Flop
SLAVE

MASTER

SI

RI

PRESET

CLEAR

Master transmits the signal

to the output during the
high clock phase and
slave is waiting for the
clock to change this
prevents race conditions

Propagation Delay Based EdgeTrigger

Circuit which produces

a short output impulse
In
used in edge triggered devices
N1
In

N2

tp LH

Out
Out

= Mono-Stable Multi-Vibrator

Edge Triggered Flip-Flop

J
S

No need for master-slave

configuration
K

Q
Q